JPH07193180A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPH07193180A
JPH07193180A JP33275493A JP33275493A JPH07193180A JP H07193180 A JPH07193180 A JP H07193180A JP 33275493 A JP33275493 A JP 33275493A JP 33275493 A JP33275493 A JP 33275493A JP H07193180 A JPH07193180 A JP H07193180A
Authority
JP
Japan
Prior art keywords
resin
lead
island
semiconductor element
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33275493A
Other languages
Japanese (ja)
Inventor
Michiyo Sasaki
美智世 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP33275493A priority Critical patent/JPH07193180A/en
Publication of JPH07193180A publication Critical patent/JPH07193180A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device whose package is adaptable for various chip sizes, holds leads firmly and withstands heat cycles. CONSTITUTION:A semiconductor device comprises a semiconductor chip 4; an island 3 smaller than the chip, on which the chip is mounted; leads 1 connected with electrodes 6 of the chip through electric conductors; and a plastic package 2. The leads are bent in the package: their outer ends of the leads are in a first horizontal plane that is half the height of the plastic package, while their inner ends are in a second horizontal plane at a lower level in the package. The island is at a level higher than the second plane. The conductors from the chip can be connected with the leads in either the first plane or the second plane depending on the size of the chip. The package has the same length above and below the electrodes of the chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は樹脂封止型半導体装置
に関し、特に半導体チップの多様なサイズに適用できる
リードフレーム構造を有する樹脂封止型半導体装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device having a lead frame structure applicable to various sizes of semiconductor chips.

【0002】[0002]

【従来の技術】近年リードフレームに半導体素子を搭載
し、ワイヤボンディングで接続した後トランスファモー
ルドで樹脂封止した半導体装置(もしくはパッケージ)
が広く使用されている。このパッケージはリード数やパ
ッケージサイズが標準化されており、新たな半導体素子
が開発された場合はこの標準化されたパッケージの中か
ら最も適合したサイズのものを選択するのが一般的であ
る。
2. Description of the Related Art In recent years, a semiconductor device (or package) in which a semiconductor element is mounted on a lead frame, connected by wire bonding, and then resin-sealed by transfer molding
Is widely used. In this package, the number of leads and the package size are standardized, and when a new semiconductor element is developed, it is general to select the most suitable size from the standardized packages.

【0003】ところがパッケージの選択要素としてリー
ド数とチップサイズがあり、同一リード数でも標準に比
べて大きいチップサイズの場合には、新たにリードフレ
ームを設計しなければならない。逆に同一リード数でも
標準に比べチップサイズがかなり小さい場合は、大きな
アイランドに小さな半導体チップを搭載する事になる。
この様な選択をした場合にはワイヤボンディングの長さ
が長くなり、ボンディングワイヤのアイランドタッチ
や、トランスファモールドの際リードが変形してリード
間がショートする等の不具合が生ずることがあった。
However, there are the number of leads and the chip size as the selection factors of the package, and when the number of leads is the same and the chip size is larger than the standard, a new lead frame must be designed. Conversely, if the chip size is considerably smaller than the standard even with the same number of leads, a small semiconductor chip will be mounted on a large island.
When such a selection is made, the length of wire bonding becomes long, which may cause problems such as island touch of the bonding wire or deformation of the leads during transfer molding and short-circuiting between the leads.

【0004】これを防止するためにはチップサイズに合
わせた専用のリードフレームを起こせばよいが、金型の
設計製作に多大な費用と時間を要し、リードフレームの
種類が増えるのでその管理も煩雑になるという欠点があ
った。
In order to prevent this, it is sufficient to raise a dedicated lead frame according to the chip size, but it takes a great deal of cost and time to design and manufacture a die, and the type of lead frame increases, so that management is also required. It had the drawback of becoming complicated.

【0005】そこで図4に断面図で示す様に、アイラン
ドをリードよりも上方に突出させて、このアイランドに
アイランドより外径が大きい半導体素子を搭載させる特
許出願もなされている(特開平5ー218274)。即
ち図4において11はリードで、樹脂封止体12の中に
延在している。13は前記リード11の先端部より上方
に保持されたアイランドで、このアイランド13にはこ
れより外径が大なる半導体素子14がAgペースト等の導
電性マウント材15で接続されている。前記半導体素子
14の外周は前記アイランド13よりはみ出し前記リー
ド11の先端部の上方に被っているが、アイランド13
がリード11の先端部より上方に位置しているので、前
記半導体素子14とリード11とが接触することは無
い。半導体素子14の電極16とリード11とはボンデ
ィングワイヤ17で接続されている。
Therefore, as shown in the cross-sectional view of FIG. 4, a patent application has been filed in which an island is projected above a lead and a semiconductor element having an outer diameter larger than that of the island is mounted on the island (Japanese Patent Laid-Open No. Hei. 218274). That is, in FIG. 4, 11 is a lead, which extends into the resin sealing body 12. Reference numeral 13 denotes an island held above the tip of the lead 11, to which a semiconductor element 14 having a larger outer diameter is connected by a conductive mounting material 15 such as Ag paste. Although the outer periphery of the semiconductor element 14 protrudes from the island 13 and covers the tip portion of the lead 11,
Is located above the tip of the lead 11, the semiconductor element 14 and the lead 11 never come into contact with each other. The electrode 16 of the semiconductor element 14 and the lead 11 are connected by a bonding wire 17.

【0006】従ってこの出願によれば多様なチップサイ
ズの半導体素子を共通のリードフレームに搭載すること
ができる。しかしながらこの構成では、半導体素子の電
極面上の樹脂封止厚18がアイランド下の樹脂封止厚1
9よりも小さいため、冷熱サイクル等が加わった場合に
ストレスの発生がパッケージの上下で不均等になり、パ
ッケージにクラックが生ずることがあった。
Therefore, according to this application, semiconductor elements of various chip sizes can be mounted on a common lead frame. However, in this configuration, the resin sealing thickness 18 on the electrode surface of the semiconductor element is equal to the resin sealing thickness 1 below the island.
Since it is smaller than 9, the occurrence of stress becomes uneven in the upper and lower parts of the package when a heat cycle or the like is applied, and cracks may occur in the package.

【0007】この問題を避けるためにアイランド13を
下方に下げることも考えられるが、リード11の樹脂封
止体12からの取り出し位置も下方に下がり、樹脂封止
体12によるリード11の保持力が落ちる。そのためリ
ード11の取り出し部で樹脂クラックが生ずる可能性も
あった。
In order to avoid this problem, it is conceivable to lower the island 13 downward, but the lead-out position of the lead 11 from the resin sealing body 12 is also lowered, and the holding force of the lead 11 by the resin sealing body 12 is reduced. drop down. Therefore, a resin crack may occur at the lead-out portion of the lead 11.

【0008】[0008]

【発明が解決しようとする課題】上記のように樹脂封止
型半導体装置には、標準のリードフレームに搭載しきれ
ない大きい半導体素子の場合は新たにリードフレームを
設計する必要があり、標準のリードフレームに標準より
小さな半導体素子を搭載する場合にはボンディングワイ
ヤのショート等が生じ、この問題を避ける為にはやはり
チップサイズやリード数に応じて専用のリードフレーム
を起こさねばならないという問題があった。 これを解
決するために小さなアイランドをリード面より上方に突
出させて、このアイランドの外径よりも大なる半導体素
子を搭載させる方法も考えられていたが、冷熱サイクル
に弱くパッケージにクラックが生ずるという問題があっ
た。
As described above, in the resin-encapsulated semiconductor device, in the case of a large semiconductor element that cannot be mounted on the standard lead frame, it is necessary to newly design the lead frame. When a semiconductor element smaller than the standard is mounted on the lead frame, a bonding wire short-circuit occurs, and in order to avoid this problem, there is a problem that a dedicated lead frame must be raised according to the chip size and the number of leads. It was In order to solve this problem, a method of projecting a small island above the lead surface and mounting a semiconductor element larger than the outer diameter of this island was also considered, but it is vulnerable to thermal cycling and cracks occur in the package. There was a problem.

【0009】本発明は上記事情に鑑みてなされたもの
で、多様なチップサイズの半導体素子を搭載でき、冷熱
サイクルにも強く、リードの樹脂による保持強度が高い
樹脂封止型半導体装置を提供しようとするものである。
The present invention has been made in view of the above circumstances and provides a resin-encapsulated semiconductor device capable of mounting semiconductor elements of various chip sizes, resistant to cooling / heating cycles, and high in holding strength of a lead resin. It is what

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に本発明では、半導体素子と、この半導体素子より外径
が小でこの半導体素子を搭載するアイランドと、前記半
導体素子の電極部と電気的接続部材で接続される複数の
リードとを樹脂封止してなる樹脂封止型半導体装置にお
いて、前記リードが樹脂封止体の厚さ方向のほぼ中央に
位置する第1の面内に保持されており、その一端が樹脂
封止内で前記第1の面より下方に段差を有する第2の面
内に折曲げ成形されており、前記アイランドが前記第2
の面より上方に位置することを特徴としている。
In order to achieve the above object, according to the present invention, a semiconductor element, an island having an outer diameter smaller than that of the semiconductor element and mounting the semiconductor element, an electrode portion of the semiconductor element, and an electrical component In a resin-sealed semiconductor device in which a plurality of leads connected by a static connection member are resin-sealed, and the leads are held in a first plane located substantially in the center in the thickness direction of the resin-sealed body. One end of the island is bent and molded into a second surface having a step below the first surface in the resin sealing, and the island is formed into the second surface.
It is characterized in that it is located above the plane.

【0011】加えて前記リードの前記電気的接続部材と
の接続点を、半導体素子の大きさに応じて前記第1の面
かあるいは前記第2の面に適宜選択できることを特徴と
している。さらに前記半導体素子電極面上の樹脂封止厚
と、前記アイランド下の樹脂封止厚がほぼ等しいことを
特徴としている。
In addition, the connection point of the lead with the electrical connection member can be appropriately selected on the first surface or the second surface according to the size of the semiconductor element. Further, the resin sealing thickness on the semiconductor element electrode surface and the resin sealing thickness under the island are substantially equal.

【0012】[0012]

【作用】上記のように本発明では、樹脂封止体内の第1
の面内に導入されたリードの先端を下方に段差を有した
第2の面内に折曲げ成形し、この第2の面より上方にア
イランドを配しているので、アイランドより大なる半導
体素子をこのアイランドに搭載しても、半導体素子とリ
ードが非接触の状態にすることができる。
As described above, according to the present invention, the first inside the resin-sealed body is used.
Since the tip of the lead introduced into the surface of the is bent and formed in the second surface having a step downward, and the island is arranged above the second surface, the semiconductor element larger than the island is formed. Even if is mounted on this island, the semiconductor element and the lead can be in a non-contact state.

【0013】加えて半導体素子が前記リードの第1の面
の部分に近接するほど大なる場合には、ボンデイングワ
イヤ(電気的接続部材)のリード側の接続点を前記第1
の面上に置くことにより、ボンディングワイヤの長さを
適切に保つことができる。半導体素子の外径がアイラン
ドの外径よりあまり大きくない場合には、ボンディング
ワイヤのリード側の接続点を前記第2の面におくことに
より、ボンディングワイヤの長さを適切にすることがで
き、トランスファモールド時のリード流れやリードショ
ートを防止することができる。
In addition, when the size of the semiconductor element becomes larger as it approaches the portion of the first surface of the lead, the connecting point on the lead side of the bonding wire (electrical connecting member) is set to the first point.
The length of the bonding wire can be properly maintained by placing the bonding wire on the surface. When the outer diameter of the semiconductor element is not much larger than the outer diameter of the island, the length of the bonding wire can be made appropriate by placing the connecting point on the lead side of the bonding wire on the second surface. It is possible to prevent lead flow and lead short-circuit during transfer molding.

【0014】さらに半導体素子の電極面上の樹脂封止厚
とアイランド下の樹脂封止厚をほぼ等しくなる様にアイ
ランドの位置を設定すれば、冷熱サイクル時の応力の発
生がパッケージの上下で均等化され、パッケージクラッ
ク等を防止することができる。
Further, if the island positions are set so that the resin sealing thickness on the electrode surface of the semiconductor element and the resin sealing thickness under the island are substantially equal, the stress generation during the cooling / heating cycle is even above and below the package. As a result, package cracks and the like can be prevented.

【0015】[0015]

【実施例】次に本発明の実施例を図を参照して説明す
る。図1は本発明の実施例に係わる樹脂封止型半導体装
置(表面実装型)を模式的に表した斜視図で、図2は本
発明の第1の実施例の要部断面図である(図1のA−A
線での断面図に相当)。なお図1と図2では同一部分に
は同一符号を付している。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a perspective view schematically showing a resin-sealed semiconductor device (surface mount type) according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an essential part of the first embodiment of the present invention ( A-A in FIG.
Equivalent to the cross-sectional view of the line). 1 and 2, the same parts are designated by the same reference numerals.

【0016】図2において1はFe-Ni 合金、Cu等からな
るリードで、エポキシ樹脂等の樹脂封止体2の厚さ方向
のほぼ中央に位置する第1の面内に導入され、その内部
の先端は下方に段差を有する如く折曲げ成形されて第2
の面内に延在している。3は前記リード1の先端部より
上方に保持されたアイランドで、このアイランド3には
これより外径が大なる半導体素子4がAgペースト等の導
電性マウント材5で接続されている。前記半導体素子4
の外周は前記アイランド3よりはみ出し前記リード1の
先端部の上方に被っているが、アイランド3がリード1
の先端部より上方に位置しているので、前記半導体素子
4とリード1とが接触することは無い。
In FIG. 2, reference numeral 1 is a lead made of Fe-Ni alloy, Cu or the like, which is introduced into the first surface of the resin encapsulation body 2 made of epoxy resin or the like, which is located substantially in the center in the thickness direction, and inside thereof. The tip of is bent and shaped so that it has a step on the lower side.
Extends in the plane. Reference numeral 3 denotes an island held above the tip of the lead 1. A semiconductor element 4 having an outer diameter larger than this is connected to the island 3 by a conductive mounting material 5 such as Ag paste. The semiconductor element 4
The outer periphery of the lead 1 protrudes from the island 3 and covers the tip of the lead 1.
Since the semiconductor element 4 and the lead 1 are located above the tip of the semiconductor element 4, they do not come into contact with each other.

【0017】次に半導体素子4の電極6と前記リード1
は、超音波ボンディング等の手段でボンディングワイヤ
7を介して接続されるが、リード1上の接続点は前記第
1の面上にとり、ボンディングワイヤが適切な長さにな
るよう構成している。
Next, the electrode 6 of the semiconductor element 4 and the lead 1
Are connected via a bonding wire 7 by means of ultrasonic bonding or the like, and the connection point on the lead 1 is located on the first surface so that the bonding wire has an appropriate length.

【0018】さらに半導体素子4の電極面上の樹脂封止
厚8と、アイランド3下の樹脂封止厚9がほぼ等しくな
るよう構成されている。従って冷熱サイクル等の熱スト
レスが加わった場合でも、パッケージ上下のストレスの
均等化が図られパッケージクラック等を防止することが
できる。またリード1の外部への導出は樹脂封止体2の
厚さ方向のほぼ中央からになっているので、樹脂封止体
2によるリード1の保持力も充分得られる。
Further, the resin sealing thickness 8 on the electrode surface of the semiconductor element 4 and the resin sealing thickness 9 below the island 3 are made substantially equal. Therefore, even when a thermal stress such as a cold heat cycle is applied, the stress on the upper and lower sides of the package can be equalized and a package crack or the like can be prevented. Further, since the lead 1 is led out to the outside from almost the center of the resin sealing body 2 in the thickness direction, a sufficient holding force of the lead 1 by the resin sealing body 2 can be obtained.

【0019】なおリード1の樹脂封止体2の外部の部分
の図示が省略されているが、外部リードを逆L字型にフ
ォーミングした挿入型、あるいはZ型にフォーミングし
た表面実装型のいずれにも適用することができる。
Although illustration of the portion of the lead 1 outside the resin encapsulant 2 is omitted, it may be either an insertion type in which the external lead is formed into an inverted L-shape or a surface mount type in which it is formed into a Z-shape. Can also be applied.

【0020】具体的には厚さ 1.0mmのパッケージを次
のようにして実現できる。即ち半導体素子4の電極面上
の樹脂封止厚7が 0.235mm、半導体素子4の厚さが0.
35mm、半導体素子4を接着するAgペーストの厚さが0.
03mm、アイランド3の厚さが0.15mm、アイランド3
下の樹脂封止厚8が 0.235mmである。アイランド3の
表面とリード1の先端部の第2の面との段差は0.05mm
程度とれば良い。図2の断面図の横方向の寸法について
は、アイランド3の辺長が 4.0mm、アイランド3とリ
ード1の先端との隙間が 1.0mm、リード1の第2の面
の平坦部が3.0mmにすれば、半導体素子4の辺長が最
大10.0mmまで適用が可能になる。
Specifically, a package having a thickness of 1.0 mm can be realized as follows. That is, the resin sealing thickness 7 on the electrode surface of the semiconductor element 4 is 0.235 mm, and the thickness of the semiconductor element 4 is 0.
35 mm, the thickness of Ag paste for bonding the semiconductor element 4 is 0.
03mm, thickness of island 3 is 0.15mm, island 3
The lower resin sealing thickness 8 is 0.235 mm. The step between the surface of the island 3 and the second surface of the tip of the lead 1 is 0.05 mm
Just take a degree. Regarding the lateral dimension of the cross-sectional view of FIG. 2, the side length of the island 3 is 4.0 mm, the gap between the island 3 and the tip of the lead 1 is 1.0 mm, and the flat portion of the second surface of the lead 1 is 3.0 mm. Then, the side length of the semiconductor element 4 can be applied up to 10.0 mm at the maximum.

【0021】次に本発明の第2の実施例を図3を参照し
て説明する。図3は図2と同様な要部断面図であり、図
2と同一箇所には同一番号を付してある。基本的な構成
は図2と同じであるが、半導体素子4のサイズがアイラ
ンドのサイズよりも若干大きい程度の場合である。
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of a main part similar to FIG. 2, and the same parts as those in FIG. 2 are denoted by the same reference numerals. The basic configuration is the same as that of FIG. 2, but the size of the semiconductor element 4 is slightly larger than the size of the island.

【0022】この様な場合ボンディングワイヤのリード
1への接続点を前記第1の面にとるとボンディングワイ
ヤ7の長さが長くなり過ぎ、トランスファモールド時に
ワイヤ流れを生じワイヤ間のショート等の不具合が発生
する。そこでこの実施例ではボンデイングワイヤ7のリ
ード1との接続点を前記第2の面上にとってボンディン
グワイヤ7の長さが適切となるよう構成している。
In such a case, if the connection point of the bonding wire to the lead 1 is set to the first surface, the length of the bonding wire 7 becomes too long, causing wire flow at the time of transfer molding, resulting in short circuit between wires. Occurs. Therefore, in this embodiment, the bonding wire 7 is connected to the lead 1 on the second surface so that the bonding wire 7 has an appropriate length.

【0023】さらに本実施例でも半導体素子4の電極面
上の樹脂封止厚8と、アイランド3下の樹脂封止厚9が
ほぼ等しくなるよう構成されている。従って冷熱サイク
ル等の熱ストレスが加わった場合でも、パッケージ上下
のストレスの均等化が図られパッケージクラック等を防
止することができる。またリード1の外部への導出は樹
脂成型体2の厚さ方向のほぼ中央からになっているの
で、樹脂成型体2によるリード1の保持力も充分得られ
る。
Further, in this embodiment as well, the resin sealing thickness 8 on the electrode surface of the semiconductor element 4 and the resin sealing thickness 9 below the island 3 are made substantially equal. Therefore, even when a thermal stress such as a cold heat cycle is applied, the stress on the upper and lower sides of the package can be equalized and a package crack or the like can be prevented. Further, since the lead 1 is led out to the outside from almost the center of the resin molded body 2 in the thickness direction, a sufficient holding force for the lead 1 by the resin molded body 2 can be obtained.

【0024】以上本発明の実施例を説明したが、本発明
は上記実施例に限られるものではなく、発明の主旨を逸
脱しない範囲で種々の変形を採り得る。例えば本実施例
ではリードが2方向にでるDIP(Dual Inline Packag
e )型で説明したが、リードが4方向にでるQFP(Qu
ad Flat Package )にも適用できることはいうまでもな
い。また電気的接続部材としてボンディングワイヤの例
を示したが、TAB(Tape Automated Bonding)方式を
適用することもできる。
Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. For example, in the present embodiment, the DIP (Dual Inline Packag) in which the leads are bidirectional
e) The QFP (Qu
It goes without saying that it can also be applied to ad Flat Package). Although an example of the bonding wire is shown as the electrical connection member, a TAB (Tape Automated Bonding) method can also be applied.

【0025】[0025]

【発明の効果】上記の如く本発明では、樹脂封止体の厚
さ方向のほぼ中央に位置する第1の面内に導入されたリ
ードの先端を下方に段差を有した第2の面内に折曲げ成
形し、この第2の面より上方にアイランドを配している
ので、アイランドより大なる半導体素子をこのアイラン
ドに搭載することができ、リードフレームの共通化が図
れる。
As described above, according to the present invention, the tips of the leads introduced into the first surface located substantially in the center in the thickness direction of the resin encapsulant are in the second surface having a step below. Since it is bent and formed, and the island is arranged above the second surface, a semiconductor element larger than the island can be mounted on this island, and the lead frame can be shared.

【0026】加えて半導体素子の大きさにより、ボンデ
イングワイヤのリード側の接続点を第1の面上もしくは
第2の面上と適宜切り換えることにより、ボンディング
ワイヤの長さを適切に保つことができるので、歩留およ
び信頼性を向上させることができる。
In addition, the length of the bonding wire can be appropriately maintained by appropriately switching the connection point on the lead side of the bonding wire to the first surface or the second surface depending on the size of the semiconductor element. Therefore, the yield and reliability can be improved.

【0027】さらに半導体素子の電極面上の樹脂封止厚
とアイランド下の樹脂封止厚をほぼ等しくなる様にアイ
ランドの位置を設定しているので、冷熱サイクル時等の
応力の発生がパッケージの上下で均等化され、パッケー
ジクラック等を防止することができる。
Further, since the position of the island is set so that the resin sealing thickness on the electrode surface of the semiconductor element and the resin sealing thickness under the island are substantially equal to each other, stress is generated during the heat / cool cycle of the package. The upper and lower sides are equalized, and package cracks and the like can be prevented.

【0028】またリードの樹脂成型体外部への導出は樹
脂成型体の厚さ方向のほぼ中央からになっているので、
樹脂成型体によるリードの保持力も充分得られ、リード
部からのクラック発生や耐湿劣化が防止され信頼性の高
い樹脂封止型半導体装置を得ることができる。
Further, since the lead is led out of the resin molded body from substantially the center in the thickness direction of the resin molded body,
It is possible to obtain a highly reliable resin-encapsulated semiconductor device in which the lead-holding force of the resin molded body is sufficiently obtained, cracking from the lead portion and moisture resistance deterioration are prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係わる樹脂型半導体装置の斜
視図。
FIG. 1 is a perspective view of a resin type semiconductor device according to an embodiment of the invention.

【図2】本発明の第1の実施例に係わる樹脂封止型半導
体装置の要部断面図で、図1のA−A線での断面図に相
当する。
FIG. 2 is a cross-sectional view of a main part of a resin-sealed semiconductor device according to a first embodiment of the present invention, which corresponds to the cross-sectional view taken along the line AA of FIG.

【図3】本発明の第2の実施例に係わる樹脂封止型半導
体装置の要部断面図で、図1のA−A線での断面図に相
当する。
FIG. 3 is a cross-sectional view of a main part of a resin-sealed semiconductor device according to a second embodiment of the present invention, which corresponds to the cross-sectional view taken along the line AA of FIG.

【図4】従来技術に係わる樹脂封止型半導体装置の要部
断面図。
FIG. 4 is a cross-sectional view of a main part of a resin-sealed semiconductor device according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 … リード 2 … 樹脂封止体 3 … アイランド 4 … 半導体素子 5 … 導電性マウント材 6 … 電極 7 … ボンディングワイヤ(電気的接続部材) 8 … 電極面上樹脂厚 9 … アイランド下樹脂厚 1 ... Lead 2 ... Resin sealing body 3 ... Island 4 ... Semiconductor element 5 ... Conductive mount material 6 ... Electrode 7 ... Bonding wire (electrical connection member) 8 ... Resin thickness on electrode surface 9 ... Resin thickness under island

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子と、この半導体素子より外径
が小でこの半導体素子を搭載するアイランドと、前記半
導体素子の電極部と電気的接続部材で接続される複数の
リードとを樹脂封止してなる樹脂封止型半導体装置にお
いて、前記リードが樹脂封止体の厚さ方向のほぼ中央に
位置する第1の面内に保持されており、その一端が樹脂
封止体内で前記第1の面より下方に段差を有する第2の
面内に折曲げ成形されており、前記アイランドが前記第
2の面より上方に位置することを特徴とする樹脂封止型
半導体装置。
1. A semiconductor element, a semiconductor element, an island having an outer diameter smaller than that of the semiconductor element, on which the semiconductor element is mounted, and a plurality of leads connected to an electrode portion of the semiconductor element by an electrical connection member with resin. In the resin-encapsulated semiconductor device as described above, the lead is held in a first surface located substantially in the center of the resin-encapsulated body in the thickness direction, and one end of the lead is in the resin-encapsulated body. Is bent and formed in a second surface having a step below the surface, and the island is located above the second surface.
【請求項2】 前記リードの前記電気的接続部材との接
続点が前記第1の面にあることを特徴とする請求項1記
載の樹脂封止型半導体装置。
2. The resin-encapsulated semiconductor device according to claim 1, wherein a connection point of the lead with the electrical connection member is on the first surface.
【請求項3】 前記リードの前記電気的接続部材との接
続点が前記第2の面にあることを特徴とする請求項1記
載の樹脂封止型半導体装置。
3. The resin-sealed semiconductor device according to claim 1, wherein the connection point of the lead with the electrical connection member is on the second surface.
【請求項4】 前記半導体素子電極面上の樹脂封止厚
と、前記アイランド下の樹脂封止厚がほぼ等しいことを
特徴とする請求項1乃至3記載の樹脂封止型半導体装
置。
4. The resin-encapsulated semiconductor device according to claim 1, wherein the resin encapsulation thickness on the semiconductor element electrode surface and the resin encapsulation thickness under the island are substantially equal to each other.
JP33275493A 1993-12-27 1993-12-27 Resin-sealed semiconductor device Pending JPH07193180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33275493A JPH07193180A (en) 1993-12-27 1993-12-27 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33275493A JPH07193180A (en) 1993-12-27 1993-12-27 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH07193180A true JPH07193180A (en) 1995-07-28

Family

ID=18258480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33275493A Pending JPH07193180A (en) 1993-12-27 1993-12-27 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH07193180A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051179A1 (en) * 1999-02-23 2000-08-31 Koninklijke Philips Electronics N.V. Method of manufacturing a leadframe assembly
KR20010008823A (en) * 1999-07-05 2001-02-05 이중구 BLP package
CN100464412C (en) * 2003-07-28 2009-02-25 旺宏电子股份有限公司 Chip packaging structure
JP2010245106A (en) * 2009-04-01 2010-10-28 Renesas Electronics Corp Magnetic storage device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000051179A1 (en) * 1999-02-23 2000-08-31 Koninklijke Philips Electronics N.V. Method of manufacturing a leadframe assembly
KR20010008823A (en) * 1999-07-05 2001-02-05 이중구 BLP package
CN100464412C (en) * 2003-07-28 2009-02-25 旺宏电子股份有限公司 Chip packaging structure
JP2010245106A (en) * 2009-04-01 2010-10-28 Renesas Electronics Corp Magnetic storage device

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