KR0136825Y1 - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR0136825Y1 KR0136825Y1 KR2019930006154U KR930006154U KR0136825Y1 KR 0136825 Y1 KR0136825 Y1 KR 0136825Y1 KR 2019930006154 U KR2019930006154 U KR 2019930006154U KR 930006154 U KR930006154 U KR 930006154U KR 0136825 Y1 KR0136825 Y1 KR 0136825Y1
- Authority
- KR
- South Korea
- Prior art keywords
- lead
- package
- thin film
- semiconductor device
- bonding pad
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
Abstract
본 고안은 반도체 장치의 팩케지에 관한 것으로서, 특히 로드 온 칩(Lead On : LOC)타입의 팩케지에서 본딩 패드와 리드간에 금속박막으로 연결하여 접촉 저항의 감소 및 노이즈 마진을 개선토록 한 반도체 장치의 팩케지에 관한 것이다.The present invention relates to a package of a semiconductor device. In particular, in a package of a load on chip (LOC) type, the semiconductor device is designed to reduce contact resistance and improve noise margin by connecting a thin film between a bonding pad and a lead. It's about packages.
이를 위하여 칩위에 형성된 다수의 본딩 패드와, 지지대위에 안착된 리드를 연결하여서 된 반도체 장치의 팩케지에 있어서, 상기 리드 프레임의 하부에 금속박막을 부착하고, 상기 금속박막과 본딩 패드를 서로 접속하여 접촉저항을 감소시키도록 한 것이다.To this end, in a package of a semiconductor device formed by connecting a plurality of bonding pads formed on a chip and a lead seated on a support, a metal thin film is attached to a lower portion of the lead frame, and the metal thin film and the bonding pad are connected to each other. It is to reduce the resistance.
Description
제1도는 종래 반도체 장치의 팩케지 구조도.1 is a package structure diagram of a conventional semiconductor device.
제2도는 본 고안에 따른 리드 프레임의 제조 공정도.2 is a manufacturing process of the lead frame according to the present invention.
제3도는 본 고안에 따른 리드 프레임의 구조도로서,3 is a structural diagram of a lead frame according to the present invention,
(a)도는 리드 프레임의 단면도.(a) is sectional drawing of a lead frame.
(b)도는 리드 프레임의 평면도.(b) Top view of the lead frame.
제4도는 본 고안에 따른 반도체 장치의 팩케지 구조도.4 is a package structure diagram of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 41 : 칩(chip) 2, 32, 42 : 리드1, 41: chip 2, 32, 42: lead
12 : 금속판 3, 33, 43 : 지지대12: metal plate 3, 33, 43: support
4, 44 : 본딩 패드 5 : 와이어4, 44: bonding pad 5: wire
16, 46 : 금속박막16, 46: metal thin film
본 고안은 반도체 장치의 팩케지에 관한 것으로서, 특히 리드 온 칩(Lead on Chip : LOC)타입의 팩케지에서 본딩 패드와 리드 간에 금속박막으로 연결하여 접촉 저항의 감소 및 노이즈 마진을 개선토록 한 반도체 장치의 팩케지에 관한 것이다.The present invention relates to a package of a semiconductor device. In particular, in a lead on chip (LOC) type package, a semiconductor device is connected to a bonding pad and a lead by a metal thin film to reduce contact resistance and improve noise margin. It's about the package.
일반적으로 반도체 장치에서 리드 온 칩(LOC) 팩케지는 듀얼 인 라인(Dual in Line : DIP), 에스. 오. 피(SOP), 에스. 오. 지(SOG) 타입의 팩케지 보다 크기를 감소시킨 형태의 팩케지로서 칩위에 리드의 한쪽 끝을 위치시키고, 본딩 패드와 와이어로서 연결하기 때문에 팩케지에서 리드가 차지하는 공간을 감소시킨 형태이며, 또한 패들(Paddle)이 없는 관계로 DIP,SOP,SOJ 등의 팩케지 보다 박형으로 제작이 용이하게 된다.In general, the lead-on-chip (LOC) package in a semiconductor device is Dual in Line (DIP), S. Five. SOP, S. Five. It is a package that is smaller in size than a SOG-type package, and is located in one end of the lead on the chip and connected as a bonding pad and wire, thereby reducing the space occupied by the lead in the package. Since there is no paddle, it is easier to manufacture thinner than package of DIP, SOP, SOJ.
즉, 종래 반도체 장치의 리드 온 칩 팩케지는 제1도에 도시된 바와 같이, 칩(1)위의 소정부분에 일정간격을 두고 다수의 본딩 패드(4)가 형성되고, 상기 본딩 패드(4)의 일측에 설치된 지지대(3)위에 다수의 리드(2)가 놓이며, 상기 리드(2)와 본딩 패드(4)는 와이어(5)를 이용하여 레이저 용접으로 연결한다.That is, the lead-on chip package of the conventional semiconductor device, as shown in FIG. 1, a plurality of bonding pads 4 are formed at a predetermined interval on the chip 1, the bonding pads 4 A plurality of leads 2 is placed on the support 3 installed on one side of the leads 2 and the bonding pads 4 are connected by laser welding using a wire 5.
상기와 같은 구조로 이루어지는 종래 리드 온 팩케지는 리드(2)와 본딩 패드(4)를 와이어(5)로서 연결함에 따라 멀티 비트 메모리(multi-bit memory) 등과 같이 순간적으로 높은 피크 전류가 흐르는 제품에서 와이어(5)의 저항에 의해 전압 강하를 유발하거나 또는 노이즈의 영향을 많이 받게될 뿐만 아니라 와이어(5)의 접촉 불량이나 절단되는 현상 및 몰딩 컴파운드(Moulding Compound)의 두께를 증가 시키는 요인이 됨으로써 신뢰도가 저하되는 문제점이 발생하게 되는 것이다.The conventional lead-on package having the above-described structure is connected to the lead 2 and the bonding pad 4 as the wire 5 in a product in which a high peak current flows momentarily, such as a multi-bit memory. The resistance of the wire 5 not only causes a voltage drop or is affected by noise, but also causes a poor contact or breakage of the wire 5 and an increase in the thickness of the molding compound. The problem is that the deterioration occurs.
본 고안은 상기와 같은 문제점을 해소하기 위해 리드에 금속박막을 부착하고, 상기 금속박막과 본딩 패드가 서로 연결 되도록 하여 본딩 패드간의 접촉 저항을 감소 시킴은 물론 제품의 노이즈 마진을 증대시켜 고신뢰도의 반도체 장치를 제작할 수 있는 반도체 장치의 팩케지를 제공하는데 본 고안의 목적이 있다.In order to solve the above problems, the present invention attaches a metal thin film to the lead, and the metal thin film and the bonding pad are connected to each other to reduce the contact resistance between the bonding pads, as well as to increase the noise margin of the product to ensure high reliability. An object of the present invention is to provide a package of a semiconductor device that can produce a semiconductor device.
상기 목적을 달성하기 위한 본 고안에 따른 반도체 장치의 팩케지는 소정 부분에 다수 개의 본딩 패드가 배열된 칩과, 상기 본딩 패드 외측의 칩상에 위치하는 지지대, 상기 지지대 위에 소정의 간격으로 이격되어 안착된 다수 개의 리드, 상기 본딩 패드와 일측이 접촉되고 타측이 상기 리드와 접촉되어 상기 본딩 패드와 리드를 전기적으로 연결하는 금속박막을 포함하여 이루어지는 것이다.The package of the semiconductor device according to the present invention for achieving the above object is a chip having a plurality of bonding pads arranged in a predetermined portion, a support positioned on the chip outside the bonding pad, spaced apart at predetermined intervals on the support It includes a plurality of leads, a metal thin film that one side is in contact with the bonding pad and the other side is in contact with the lead to electrically connect the bonding pad and the lead.
이하 첨부된 도면에 의해 본 고안을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 고안에 따른 리드 프레임의 제조 공정도로서, 먼저 (a)도와 같이 알루미늄 또는 구리(Copper) 등의 금속판(12)의 중앙 부위를 소정 폭으로 절단한 다음 (b)도에서와 같이 금(Au) 또는 알루미늄(Al)과 같은 연성을 가지며 전도성이 우수한 재질의 금속박막(16)을 금속판(12)의 중앙부에 절단된 폭 보다 조금 넓게 형성한 후 상기 금속판(12)과 금속박막(16)을 초고주파 용접 또는 레이저 용접 등으로 부착시킨다.FIG. 2 is a manufacturing process diagram of a lead frame according to the present invention. First, a center portion of a metal plate 12 such as aluminum or copper is cut to a predetermined width as shown in FIG. The metal plate 12 and the metal thin film 16 are formed by forming a metal thin film 16 of ductility such as (Au) or aluminum (Al) and having excellent conductivity, a little wider than the width cut at the center portion of the metal plate 12. ) Is attached by microwave welding or laser welding.
이후 (c)도와 같이 용접이 끝난 금속판(12)을 사용하고자 하는 형태로 절단하여 리드를 만들고, 지지대 위에 소정 간격으로 배열하여 리드 프레임을 만든다.Thereafter, as shown in (c), the welded metal plate 12 is cut into a shape to be used, and a lead is made by arranging at a predetermined interval on the support.
제3도의 (a)는 지지대(33)와 결합된 리드(32)의 단면도이며, (b)도는 평면도를 도시한 것이다.FIG. 3A is a cross-sectional view of the lid 32 coupled to the support 33, and FIG.
상기와 같이 제작된 리드(42)는 제4도에서와 같이 칩(41) 위의 소정 부분에 일정 간격을 두고 다수의 본딩 패드(44)와, 상기 본딩 패드(44)의 일측에 설치된 지지대(43) 위에 설치되고 금속박막(46)이 부착되어 있는 다수의 리드(42)를 안착시킨 후 상기 금속박막(46)과 본딩 패드(44)를 레이저 용접으로 연결한다.The lead 42 manufactured as described above has a plurality of bonding pads 44 and a support provided on one side of the bonding pads 44 at predetermined intervals on a predetermined portion on the chip 41 as shown in FIG. 43) After mounting a plurality of leads 42, which are installed on the metal thin film 46, the metal thin film 46 and the bonding pads 44 are connected by laser welding.
따라서 금속박막(46)과 본딩 패드(44)가 서로 연결되면 접촉 면적의 증가로 인한 접촉저항이 감소되는 것이다.Therefore, when the metal thin film 46 and the bonding pad 44 are connected to each other, the contact resistance due to the increase in the contact area is reduced.
이상에서 상술한 바와 같이 본 고안은 리드에 금속박막을 부착하고, 상기 금속박막과 본딩 패드가 서로 연결 되도록하여 본딩 패드간의 접촉 저항을 감소시킴은 물론 제품의 노이즈 마진을 증대시킬 뿐만 아니라 몰딩 파운드의 높이를 감소시킬 수 있는 것이다.As described above, the present invention attaches a metal thin film to a lead and connects the metal thin film and the bonding pad to each other to reduce the contact resistance between the bonding pads, as well as to increase the noise margin of the product, It can reduce the height.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019930006154U KR0136825Y1 (en) | 1993-04-19 | 1993-04-19 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019930006154U KR0136825Y1 (en) | 1993-04-19 | 1993-04-19 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940025562U KR940025562U (en) | 1994-11-18 |
| KR0136825Y1 true KR0136825Y1 (en) | 1999-02-18 |
Family
ID=19353854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019930006154U KR0136825Y1 (en) | 1993-04-19 | 1993-04-19 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0136825Y1 (en) |
-
1993
- 1993-04-19 KR KR2019930006154U patent/KR0136825Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940025562U (en) | 1994-11-18 |
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