KR19980020498A - Semiconductor chip package having center bonding pad and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package and a method of manufacturing the same, and more particularly, to a semiconductor chip package and a method of manufacturing the same, in which a semiconductor chip having a center bonding pad is applied to a lead frame provided with a die pad. A lead frame having two inner leads, a semiconductor chip attached to an upper surface of the die pad, and having a bonding pad at a central portion thereof, a conductive wire electrically connecting the bonding pad and the inner lead of the lead frame; In the method of manufacturing a semiconductor chip package comprising a molding resin for molding, attaching a semiconductor chip having a plurality of bonding pads in the center portion on the die pad upper surface of the lead frame, the inner lead and the bonding pad of the lead frame Electrical connection using a conductive wire, and the entire molding resin It characterized in that it comprises the step of molding.

Description

Semiconductor chip package having center bonding pad and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package and a method of manufacturing the same, and more particularly, to a semiconductor chip package and a method of manufacturing the same, in which a semiconductor chip having a center bonding pad is applied to a lead frame provided with a die pad.

In general, a semiconductor chip package attaches a semiconductor chip 1 having a plurality of bonding pads 5 to an upper surface of a die pad 8 of a lead frame using an adhesive 4, as shown in FIG. After the inner lead 2 of the lead frame and the bonding pad 5 of the semiconductor chip 1 are electrically connected with each other using a conductive wire 3, the semiconductor chip 1 and the inner lead 2 are fixed. After the part is molded with the molding resin 6, it is produced through a conventional trimming / forming process and a plating process.

Here, reference numeral 7 denotes a tie bar that physically supports the die pad 8 on which the semiconductor chip is mounted.

Since the inner lead and the die pad of the lead frame applied to the semiconductor chip package manufactured as described above are separated from each other by a predetermined distance, the integration degree of the semiconductor chip 1 is improved and the chip size is increased, so that the die pad and the inner lead are increased. There is a problem that can not secure a constant distance with the reverse of the trend of miniaturization of the package.

In addition, in order to package an enlarged semiconductor chip, there is a problem in that a lead frame and a package must be redesigned accordingly.

In order to solve the above problems, the lead on chip (LOC) package shown in Figure 2 has been developed and is currently being actively produced. For the convenience of description, the same reference numerals are used for the same names as those shown in FIG. 1.

In the LOC type semiconductor chip package, the inner lead 2 of the lead frame is attached with an insulating tape 4 on the upper surface of the semiconductor chip 1 having the bonding pad 5 at the center thereof, and the inner lead 2 and the semiconductor chip are attached to each other. The bonding pad 5 of (1) is electrically connected using a conductive wire 3, and a portion of the inner lead 2 is molded with the molding resin 6 so that the semiconductor chip 1 is included. It is manufactured through a conventional trimming / forming process and a plating process.

In the LOC type package as described above, since the inner lead 2 of the lead frame is attached to the surface of the semiconductor chip 1 via an insulating tape 4 or the like, the die pad 8 is not required. Larger semiconductor chips than those used in conventional packages can be mounted. In addition, a package manufactured using a large semiconductor chip has an advantage of making it thinner than the size of a semiconductor chip package made using a lead frame having a conventional die pad.

However, the lead frame used in the LOC type package has a problem in that the manufacturing cost of the package is high because an insulating tape is attached to the inner lead and is more expensive than a lead frame having a conventional die pad.

In addition, since the semiconductor chip applied to the LOC type is highly integrated, as the number of wires used as a means for connecting the circuit pattern formed on the semiconductor chip with a predetermined external circuit increases, the spacing between the wires becomes dense, thereby forming a molding resin. In the molding process, there is a problem in that electrical shorting occurs between wires due to a wire sweeping phenomenon.

Accordingly, the present invention is to solve the above problems, a semiconductor chip package that can be a composite of a semiconductor chip having a center bonding pad which is an advantage of the LOC package in a lead frame having a die pad is an advantage of the general package and The object is to provide a method for producing the same.

1 is a plan view showing the internal structure of a conventional semiconductor chip package

2 is a plan view showing the internal structure of a conventional LOC type semiconductor chip package

3 is a plan view showing the internal structure of a semiconductor chip package according to an embodiment of the present invention

4 is a cross-sectional view illustrating the semiconductor chip package of FIG. 3.

5 (A) to (B) is a view showing another embodiment according to the present invention

Explanation of symbols for main parts of the drawings

1 semiconductor chip 2 inner lead 3 wire

4: adhesive 5: bonding pad 6: molding resin

7: tie bar

Hereinafter, a semiconductor chip package having a center bonding pad according to the present invention will be described in detail with reference to the accompanying drawings. For convenience of description, the same reference numerals are used for the same names as the conventional parts.

3 is a plan view showing the internal structure of a semiconductor chip package according to the present invention, Figure 4 is a cross-sectional view showing a semiconductor chip package according to the present invention.

As illustrated, the back surface of the semiconductor chip 1 having the bonding pads 5 at the center thereof is bonded to the upper surface of the die pad 8 of the lead frame with an adhesive 4, and the bonding pads 5 and the inner leads (2) has a structure in which it is electrically connected with the conductive wire 3, and is molded with the molding resin 6 so that a predetermined portion of the semiconductor chip 1 and the inner lead 2 are included.

5A to 5B show another embodiment of the present invention, and FIG. 5A shows the most of the wires of the semiconductor chip in the molding process of the molding resin during the semiconductor manufacturing process. It is a figure which shows that the wire 3 was bent at a predetermined angle in order to prevent contact with the seat portion and to prevent electrical short between the wires. FIG. 5 (B) shows the inner lead 2 and the semiconductor chip of the lead frame. It is a figure which shows that the upper surface of (1) became horizontal.

Here, in order to prevent the neighboring wires from being electrically shorted to each other, the entire surface of the conductive wire 3 electrically connecting the bonding pad 5 and the inner lead 2 may be coated with an insulator.

The method for manufacturing a semiconductor chip package according to the present invention configured as described above is as follows.

First, the semiconductor chip 1 with the bonding pad 5 is attached to the center of the lead frame with the insulating adhesive 4 on the upper surface of the die pad 8. Thereafter, the bonding pad 5 of the semiconductor chip 1 and the inner lead 2 corresponding to the bonding pad 5 are electrically connected to the conductive wire 3.

Here, the conductive wire 3 is coated with an insulating material in advance in order to prevent shorting with neighboring wires in the process of molding with molding resin.

Subsequently, molding is performed with a molding resin so as to include a predetermined portion of the semiconductor chip 1, the entire wire 3, and the inner lead 2 using the transfer molding method.

Subsequently, dambars (not shown) formed between the out leads may be formed to prevent the molding resin 6 from flowing out of the encapsulation line separating the out leads and the inner leads 2 using a trim process. Cut.

Then, the out lead is cut into the desired shape. The out leads are then electroplated to improve the electrical stability of the out leads and to protect them from the external environment. Subsequently, the electroplated out lead is bent into a desired shape for mounting on a printed circuit board using a forming process. In this way, the semiconductor chip package is completed.

The separate design of semiconductor chips and the need for additional semiconductor manufacturing equipment are eliminated, allowing the use of existing designs and equipment in production packages to be applied directly, thereby avoiding additional investment in semiconductor manufacturing.

As described above, according to the structure of the semiconductor chip package according to the present invention, by combining only the advantages of each of the general semiconductor chip package and LOC package, it is possible to obtain a more complete package function, the existing semiconductor chip and production line The economical effect of manufacturing the product can be obtained.

In addition, by electrically insulating a conductive wire that electrically connects the inner lead and the bonding pad and bending it at a predetermined angle, there is an effect of preventing the deterioration of the function of the semiconductor device due to the short circuit between the wires.

Claims (5)

A lead frame having a die pad and a plurality of inner leads, a semiconductor chip attached to an upper surface of the die pad and having a bonding pad at a center thereof, and a conductive wire electrically connecting the bonding pad and the inner lead of the lead frame. And a molding resin for molding the whole. The semiconductor chip package according to claim 1, wherein the conductive wire is coated with an insulating material on its surface. The semiconductor chip package according to claim 1, wherein the conductive wire is bent at a predetermined angle to prevent contact with the edge portion of the semiconductor chip. The semiconductor chip package of claim 1, wherein an inner lead of the lead frame and an upper surface of the semiconductor chip are horizontal. A method of manufacturing a semiconductor chip package, comprising: attaching a semiconductor chip having a plurality of bonding pads formed at a center portion to an upper surface of a die pad of a lead frame, and electrically connecting the inner lead and the bonding pad of the lead frame using conductive wires A method of manufacturing a semiconductor chip package having a center bonding pad, the method comprising the steps of: connecting to a mold;