KR0135890Y1 - Lead on chip package - Google Patents

Lead on chip package Download PDF

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Publication number
KR0135890Y1
KR0135890Y1 KR2019950042877U KR19950042877U KR0135890Y1 KR 0135890 Y1 KR0135890 Y1 KR 0135890Y1 KR 2019950042877 U KR2019950042877 U KR 2019950042877U KR 19950042877 U KR19950042877 U KR 19950042877U KR 0135890 Y1 KR0135890 Y1 KR 0135890Y1
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KR
South Korea
Prior art keywords
lead
inner lead
chip
chip package
bus bar
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KR2019950042877U
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Korean (ko)
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KR970046892U (en
Inventor
고경희
Original Assignee
김주용
현대전자산업주식회사
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Priority to KR2019950042877U priority Critical patent/KR0135890Y1/en
Publication of KR970046892U publication Critical patent/KR970046892U/en
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Publication of KR0135890Y1 publication Critical patent/KR0135890Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본고안은 내부리드와 칩이 테이프로 어태치되는 리드온칩 패키지에서 내부 리드 표면에 보조테이프로 버스바를 어태치시키고, 칩에는 전도패드를 중앙및 모서리부에 형성한것을 특징으로하는 리드온칩 패키지를 제공하려는 것으로, 리드온칩 패키지의 내부리드를 연장하고 내부리드위에 버스바를 위치시키는 구조이므로 내부리드와의 와이어본딩을 용이하게 하며, 버스바의 양단부 대응 칩부위에 전도패드를 형성하여 버스바와의 와이어본딩을 용이하게 하고, 필요시 특정부위에도 전도패드를 구현 가능하여 칩의 전도패드 설계 계약을 없애준다.In this paper, the lead-on chip package is characterized in that the busbar is attached to the inner lead surface by attaching the busbar to the inner lead surface in the lead-on chip package in which the inner lead and the chip are attached to the tape. It is intended to provide a structure that extends the inner lead of the lead-on chip package and locates the bus bar on the inner lead, thereby facilitating wire bonding with the inner lead, and forming conductive pads on the chip portions corresponding to both ends of the bus bar to form a wire with the bus bar. It facilitates bonding and eliminates chip conduction pad design contracts by allowing conduction pads to be placed on specific areas as needed.

Description

리드온칩 패키지Lead-on chip package

제1도는 일반적인 리드온칩 패키지의 와이어본딩된 상태를 보인 부분 평면도.1 is a partial plan view showing a wire bonded state of a typical lead-on chip package.

제2도는 제1도의 A-A선 단면도.2 is a cross-sectional view taken along the line A-A of FIG.

제3도는 본고안의 몰딩수지를 생략한 상태의 요부 평면도.3 is a plan view of the main parts, with the molding resin in this article omitted.

제4도는 제3도의 A-A선 단면상에서의 패키지 단면도.4 is a cross-sectional view of the package taken along the line A-A of FIG.

제5도는 제3도의 B-B선 단면상에서의 패키지 단면도이다.FIG. 5 is a cross-sectional view of the package taken along the line B-B in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 칩 3 : 내부리드1 chip 3 internal lead

5 : 테이프 5' : 패드공5: Tape 5 ': Pad ball

7 : 전도패드 7' : 전도패드7: conductive pad 7 ': conductive pad

8 : 몰드수지 10 : 보조테이프8: mold resin 10: auxiliary tape

20 : 버스바 21 : 단부20: busbar 21: end

본고안은 리드온칩 패키지에 관한것으로, 내부리드위에 보조접착테이프를 사용하여 리드온리드 상태로 별도의 버스바를 어태치시키고, 칩에는 버스바와 와이어본딩되는 전도패드를 칩의 중앙 및 테두리에 설치한 것이다.This article is about the lead-on chip package.A separate bus bar is attached to the lead by using auxiliary adhesive tape on the inner lead, and the bus bar and the wire-bonding conduction pad are installed at the center and the edge of the chip. will be.

일반적으로 리드온칩 반도체 패키지는 리드프레임의 내부리드밑에 테이프를 어태치시키고 테이프로 내부리드와 칩을 어태치시켜 제조한다. 이때의 와이어본딩된 상태는 제1도와 같이 예시할수있는바, 내부리드(3)와 버스바(2) 밑에 테이프(5)를 어태치시키고, 테이프(5)를 매체로 내부리드(3)와 버스바(2)를 칩(1) 표면에 어태치시킨 다음, 와이어(4)로 와이어본딩 시키는것을 예시할수있다.In general, a lead-on chip semiconductor package is manufactured by attaching a tape under an inner lead of a lead frame and attaching an inner lead and a chip by a tape. The wire-bonded state at this time can be illustrated as shown in FIG. 1, by attaching the tape 5 under the inner lead 3 and the bus bar 2, and using the tape 5 as a medium to the inner lead 3 and the bus. The bar 2 may be attached to the surface of the chip 1 and then wire bonded with the wire 4.

제1도의 A-A선 단면상태는 제2도와 같이 예시할수있는바, 내부리드(3)와 버스바(2)를 테이프(5)를 사용하여 칩(1)에 어태치시키고, 내부리드(3)와 버스바(2)는 칩(1)의 전도패드(7)에 와이어(4)로 와이어 본딩시킨다. 이리한 구조의 리드온칩 패키지는 버스바(2)가 칩(1)의 중앙에 위치하고, 내부리드(3)는 전도패드(7)와의 와이어(4)본딩시 버스바(2)를 지나서 와이어본딩 되므로, 몰딩시 와이어 스위프에 의한 패키지 불량 요인이 되고, 전도패드(7)가 중앙에만 위치되어 전도패드(7) 설계에 제약요인이 된다.The cross-sectional state of the AA line of FIG. 1 can be illustrated as shown in FIG. 2 by attaching the inner lead 3 and the bus bar 2 to the chip 1 using the tape 5, and the inner lead 3 and the inner lead 3. The bus bar 2 wire-bonds the conductive pad 7 of the chip 1 with the wire 4. In this structure, the lead-on chip package has a bus bar 2 positioned at the center of the chip 1, and the inner lead 3 is wire-bonded past the bus bar 2 when bonding the wire 4 with the conductive pad 7. Therefore, when molding, it becomes a package failure factor due to the wire sweep, and the conductive pad 7 is located only at the center, which is a limiting factor in the design of the conductive pad 7.

본고안은 이를 해결코자 하는 것으로, 버스바를 내부리드 표면에 어태치시켜 내부리드의 와이어본딩 에러를 줄일수 있도록함을 특징으로 한다.This paper proposes to solve this problem by attaching the busbar to the inner lead surface to reduce the wire bonding error of the inner lead.

즉, 본고안은 내부리드와 칩이 테이프로 어태치되는 리드온칩 패키지에서, 내부리드 표면에 보조테이프로 버스바를 어태치시키고, 칩에는 전도패드를 중앙 및 모서리부에 형성한 리드온칩 패키지를 제공하려는 것이다.In other words, this paper provides a lead-on chip package in which the lead and chip are attached to the inner lead and the chip, and the busbar is attached to the inner lead surface with an auxiliary tape, and the conductive pad is formed at the center and corners of the chip. I will.

이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.

제3도는 본고안의 요부평면도, 제4도는 제3도의 A-A선 단면도, 제5도는 제3도의 B-B선 단면도로, 내부리드와 칩이 테이프로 어태치되는 리드온칩 패키지에서, 내부리드(3) 표면에 보조테이프(10)로 버스바(20)를 어태치시키고, 칩(1)에는 전도패드(7)를 중앙 및 모서리부에 형성한다.FIG. 3 is a plan view of the main part of the present invention, FIG. 4 is a sectional view taken along the line AA of FIG. 3, and FIG. 5 is a sectional view taken along the line BB of FIG. 3, in the lead-on chip package in which the inner lead and the chip are attached with a tape. The busbar 20 is attached to the auxiliary tape 10, and the conductive pad 7 is formed at the center and the corners of the chip 1.

상기 버스바(20)는 내부리드(3)와 직교하며, 버스바(20) 양단부(21)는 다운셋되어 내부리드(3) 어태치용 테이프(5)에 고정되도록 이루어진다.The bus bar 20 is orthogonal to the inner lead 3, and both ends 21 of the bus bar 20 are downset and fixed to the tape 5 for attaching the inner lead 3.

상기 내부리드(3)와 칩(1)을 어태치시키는 테이프(5) 임의개소에는 특정전도패드(7') 노출용 패드공(5')을 형성한다.The pad hole 5 'for exposing the specific conductive pad 7' is formed in an arbitrary position of the tape 5 to which the inner lead 3 and the chip 1 are attached.

상기 버스바(20)는 양단부(21)만 내부리드(3)와 나란한 Ⅱ형상을 예시할수있다.The bus bar 20 may illustrate a II shape in which only both ends 21 are parallel to the inner lead 3.

상기 내부리드(3)는 전도패드(7) 근접위치까지 연장시킴이 바람직하다.The inner lead 3 preferably extends to a position close to the conductive pad 7.

도면에서(8)은 몰드수지를 나타낸다.In the figure, 8 shows a mold resin.

이와같이 구성한 본고안을 제조함에 있어서는, 칩(1)의 전도패드(7)를 중앙 및 측면(내부리드(3)와 나란한 방향)에 형성하고, 필요시 특정 전도패드(7')를 형성하는바, 이러한 전도패드(7, 7')의 형성기술 자체는 공지 기술이기에 여기서는 전도패드(7, 7')의 위치만을 명기한다. 한편 상기 특정 전도패드(7')에 패드공(5')을 형성한 테이프(5)를 내부리드(3)(기존것보다 전도패드(7)에 근접하게(버스바가 있던 부위까지)연장된건)저면에 어태치시킨다. 이어 내부리드(3) 표면에 보조테이프(10)로 버스바(20)를 내부리드(3)와 직교하는 방향으로 어태치시킨다. 이상태에서 상기 특정전도패드(7') 및 전도패드(7)를 가지는 칩(1)을 어태치시켜 다이어태치 공정을 수행한다. 이경우 칩(1)의 특정전도패드(7')는 테이프(5)의 패드공(5')을 통해 내부리드(3) 사이로 노출된다. 따라서 와이어본딩 시키면 제3도 내지 5도 상태를 이루게 되는바, 칩(1)의 전도패드(7)(7')와 버스바(20)는 어느위치에서도 쉽게 와이어본딩 가능하며, 이에따라 전도패드(7)(7') 설계가 용이하고, 버스바(20)와 전도패드(7)(7') 거리가 상대적으로 가까워져 신뢰성을 향상시킨다.In producing the above-described proposal, the conductive pad 7 of the chip 1 is formed at the center and side surfaces (parallel with the inner lead 3), and if necessary, a specific conductive pad 7 'is formed. Since the technology for forming the conductive pads 7 and 7 'itself is a known technique, only the positions of the conductive pads 7 and 7' are specified here. Meanwhile, the tape 5 having the pad hole 5 'formed on the specific conductive pad 7' is extended to the inner lead 3 (closer to the conductive pad 7 than the conventional one) (up to the area where the bus bar was). Attach to the bottom. Subsequently, the busbar 20 is attached to the surface of the inner lead 3 with the auxiliary tape 10 in a direction orthogonal to the inner lead 3. In this state, a die attach process is performed by attaching the chip 1 having the specific conductive pad 7 ′ and the conductive pad 7. In this case, the specific conductive pad 7 'of the chip 1 is exposed between the inner leads 3 through the pad hole 5' of the tape 5. Therefore, wire bonding results in a state of FIGS. 3 to 5 degrees, and the conductive pads 7 and 7 'of the chip 1 and the bus bar 20 can be easily wire-bonded at any position, and thus the conductive pads ( 7) (7 ') is easy to design, and the distance between the busbar 20 and the conduction pads (7) (7') is relatively close, improving reliability.

본고안에서는 내부리드 표면에 버스바가 2열인 것을 예시하였으나 그이상의 열로 구성할수 있다.In this paper, although the busbar has two rows on the inner lead surface, it can be configured with more rows.

이상과 갈이 본고안은 리드온칩 패키지의 내부리드를 연장하고 내부리드위에 버스바를 위치시키는 구조이므로 내부리드와의 와이어본딩을 용이하게 하며, 버스바의 양단부 대응 칩부위에 전도패드를 형성하여 버스바와의 와이어본딩을 용이하게 하고, 필요시 특정부위에도 전도패드를 구현 가능하여 칩의 전도패드 설계 계약을 없애준다.This paper extends the inner lead of the lead-on chip package and locates the bus bar on the inner lead, thus facilitating wire bonding with the inner lead, and forming a conductive pad on the chip corresponding to both ends of the bus bar. It facilitates wirebonding of bars and conduction pads to specific areas as needed, eliminating the chip's conduction pad design contract.

Claims (5)

내부리드와 칩이 테이프로 어태치되는 리드온칩 패키지에서, 내부리드 표면에 보조테이프로 버스바를 어태치시키고, 칩에는 전도패드를 중앙및 모서리부에 형성한 것을 특징으로하는 리드온칩 패키지.In a lead-on chip package in which the inner lead and the chip are attached to the tape, the bus bar is attached to the inner lead surface with an auxiliary tape, and the chip has conductive pads formed at the center and corners thereof. 제1항에 있어서, 버스바는 내부리드와 직교하며, 그 양단은 다운셋되어 내부리드 어태치용 테이프에 고정된것을 특징으로하는 리드온칩 패키지.The lead-on chip package according to claim 1, wherein the bus bars are orthogonal to the inner lead, and both ends thereof are downset and fixed to the inner lead attach tape. 제1항에 있어서, 내부리드와 칩을 어태치시키는 테이프 임의개소에는 특정전도패드 노출용 패드공을 형성한것을 특징으로하는 리드온칩 패키지.The lead-on chip package according to claim 1, wherein a pad hole for exposing a specific conductive pad is formed in any portion of the tape attaching the inner lead and the chip. 제1항에 있어서, 버스바는 상하단만 내부리드와 나란한 Ⅱ형상인것을 특징으로 하는 리드온칩 패키지.The lead-on chip package according to claim 1, wherein the bus bar has a shape of II in parallel with the inner lead only at the upper and lower ends thereof. 제1항에 있어서, 내부리드는 전도패드 근접 위치까지 연장된것을 특징으로 하는 리드온칩 패키지.The lead-on chip package of claim 1, wherein the inner lead extends to a position close to the conductive pad.
KR2019950042877U 1995-12-18 1995-12-18 Lead on chip package KR0135890Y1 (en)

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KR0135890Y1 true KR0135890Y1 (en) 1999-02-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525091B1 (en) * 2001-12-28 2005-11-02 주식회사 하이닉스반도체 semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100525091B1 (en) * 2001-12-28 2005-11-02 주식회사 하이닉스반도체 semiconductor package

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