KR0124547Y1 - Semiconductor device for multi-type lead frame - Google Patents
Semiconductor device for multi-type lead frameInfo
- Publication number
- KR0124547Y1 KR0124547Y1 KR92015611U KR920015611U KR0124547Y1 KR 0124547 Y1 KR0124547 Y1 KR 0124547Y1 KR 92015611 U KR92015611 U KR 92015611U KR 920015611 U KR920015611 U KR 920015611U KR 0124547 Y1 KR0124547 Y1 KR 0124547Y1
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- lead
- semiconductor device
- lead frame
- inner lead
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 고안은 반도체 장치의 리드프레임을 제1내부리드와 제2내부리드로 구성된 멀티형 리드프레임을 이용하여 LOC 방식에 따른 칩과 패키지의 레이아웃 설계상의 한계성을 극복한 것으로, 이는 제1내부리드를 칩위에 부착하고 제2내부리드는 칩외부에 위치시킴으로써 칩과 패키지의 공간부를 활용하고 패드의 배열설계상의 범위를 넓혀 다양한 패키지의 형상을 디자인을 할 수 있게 한다.The present invention overcomes the limitations of the layout design of chips and packages according to the LOC method using a multi-type lead frame composed of a first internal lead and a second internal lead of a semiconductor device. By attaching on the top and the second inner lead outside the chip, the space of the chip and the package can be utilized, and the pad arrangement can be expanded to design various package shapes.
Description
제1도는 반도체 장치의 칩위에 패드의 배열을 나타낸 평면도.1 is a plan view showing an arrangement of pads on a chip of a semiconductor device.
제2도는 본 고안의 멀티형 리드프레임을 이용한 반도체 장치의 측면도.2 is a side view of a semiconductor device using the multi-type lead frame of the present invention.
제3도는 본 고안의 실시예를 나타낸 평면확대도.Figure 3 is an enlarged plan view showing an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
4,4a : 본딩와이어 5 : 접착제4,4a: bonding wire 5: adhesive
10 : 칩 10a : 칩중앙부10: chip 10a: chip central part
10b : 칩양단부 11a : 제1패드10b: both ends of the chip 11a: the first pad
11b : 제2패드 21 : 제1내부리드11b: 2nd pad 21: 1st internal lead
22 : 제2내부리드22: 2nd internal lead
본 고안은 반도체 장치에 관한 것으로, 특히 반도체 조립의 LOC(LEAD ON CHIP) 방식에 따른 칩과 패키지의 레이 아웃(LAY OUT) 설계상의 한계성을 극복한 멀티형 리드프레임을 이용한 반도체 장치에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a semiconductor device using a multi-type lead frame that overcomes limitations in the layout of chips and packages according to the lead on chip (LOC) method of semiconductor assembly.
일반적으로 반도체 제조시에 리드프레임과 칩을 결선시킴에 있어서는, 칩밖에 리드프레임의 내부리드를 위치시켜 와이어본딩하고 패키징하는 일반적인 방식과, 칩과 리드프레임의 내부리드를 접착테이프를 사용하여 접착하고 와이어본딩한 후 패키징하는 LOC(LEAD ON CHIP) 방식이 알려져 있다. 상기 LOC 방식의 경우 칩위에 내부리드를 올려놓을수 있는 공간부가 충분할 경우는 큰 문제가 없겠지만, 제1도와 같이 칩(1)위에 패드(2)의 배열설계상 칩(1)의 양측단부(1a) 가장자리에 패드(2)가 위치되고 패키지(3)의 형상이 길이방향으로 긴 형태를 이루어 공간부(3a)가 큰 반도체 장치에서는, 칩(1) 상에 내부리드(도시하지 않음)가 접착될만한 공간(A)이 상대적으로 부족하므로 LOC 방식을 적용할수 없게된다. 따라서 칩과 패드의 레이아웃(LAY OUT)설정에 많은 노력과 시간이 소요되는등 많은 문제가 발생하였다.Generally, when connecting lead frame and chip in semiconductor manufacturing, general method of wire bonding and packaging by placing inner lead of lead frame outside chip, and bonding chip and lead frame inner lead with adhesive tape Lead-on chip (LOC) method of packaging after wire bonding is known. In the case of the LOC method, if there is enough space for placing an internal lead on the chip, there is no big problem. However, in the arrangement design of the pad 2 on the chip 1 as shown in FIG. 1, both side ends 1a of the chip 1 are arranged. In the semiconductor device where the pad 2 is positioned at the edge and the shape of the package 3 is long in the longitudinal direction, and the space portion 3a is large, the inner lead (not shown) can adhere to the chip 1. Since the space A is relatively insufficient, the LOC method cannot be applied. As a result, many problems have occurred such as a lot of effort and time in setting the layout (LAY OUT) of the chip and the pad.
본 고안은 이를 해결한 것으로, 내부리드중 일부는 칩의 중앙공간부에 위치시키고 상기 내부리드와 연장되고 일체로 형성된 다른 내부리드는 칩 외부에 위치시키도록 구성된 멀티형 리드프레임을 이용하여 칩과 부착하고 와이어 본딩하여 패키징함을 특징으로 한다. 즉, 칩위에 접착제로 리드를 접착하고 패드와 와이어본딩되는 제1내부리드와, 칩외부에서 칩의 가장자리에 위치한 패드와 와이어 본딩한 제2내부리드로 구성되는 멀티형 리드프레임을 포함하여 이루어진 반도체 장치이다.The present invention solves this problem, and a part of the inner lead is attached to the chip using a multi-type lead frame configured to be positioned in the central space of the chip and the other inner lead extending and integrally formed with the inner lead is located outside the chip. And packaging by wire bonding. That is, a semiconductor device including a multi-type lead frame including a first inner lead bonded to a lead with an adhesive on a chip and wire-bonded with a pad, and a second inner lead wire-bonded with a pad located at an edge of the chip outside the chip. to be.
이하 제2도 및 제3도를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to FIGS. 2 and 3 will be described in detail.
본 고안의 멀티형 리드프레임의 구조는 칩(10) 상면에 위치되는 제1내부리드(21)와, 칩(10)외부에 위치되는 제2내부리드(22)로 이루어지며, 각 리드(21),(22)는 외부리드(23)로 연결되도록 형성된다. 상기 제1내부리드(21)는 칩(10)위에서 접착제(5)로 접착되어 칩(10) 중앙부(10a)에 배열된 제1패드(11a)와 와이어(4) 본딩하고, 상기 제2내부리드(22)는 칩(10) 외부에 위치되어 칩(10) 양측단부(10b) 가장자리에 배열된 제2패드(11b)와 와이어(4a) 본딩되는 구조로 된것이다.The structure of the multi-type lead frame according to the present invention includes a first internal lead 21 positioned on an upper surface of the chip 10 and a second internal lead 22 positioned outside the chip 10, and each lead 21. , 22 is formed to be connected to the outer lead (23). The first inner lead 21 is bonded onto the chip 10 with an adhesive 5 to bond the wires 4 to the first pad 11a arranged at the center portion 10a of the chip 10. The lead 22 has a structure in which the wire 4a is bonded to the second pad 11b which is positioned outside the chip 10 and arranged at the edges of both ends 10b of the chip 10.
제3도는 본 고안의 실시예로 칩(10)위에 패드(11)의 배열을 중앙부(10a)와 양측단부(10b)에 형성하였고, 상기 중앙부(10a)의 패드(11a)에는 제1내부리드(21)를 접착제로 접착하였으며, 제2내부리드(22)는 패키지(3)의 공간부(3a)에 위치시킨 상태를 나타낸 것이다. 즉, 내부리드를 제1 및 그 내부리드(21,22)로 구분형성하고, 제2내부리드(22)를 칩(10)의 외부에 위치케 하므로서, 칩(10)의 크기변화나 패키지(3)의 공간부(3a)에 대응하여 레이아웃을 편하게 구상할수 있게된다. 상기 패드(11)의 배열은 중앙부(10a)와 양측단부(10b)에 고정되어 레이아웃되는 것뿐아니라 필요시 변화가능하며 이에 대응하는 제1 및 2 내부리드(21,22)의 레이아웃은 물론 패키지(3)의 레이아웃도 변화가능함은 물론이다. 본 고안에서 리드프레임을 이용하고, 그 후에 패키이징 및 포밍하는 것은 일반적인 기술이므로 생략한다.3 is an embodiment of the present invention, the arrangement of the pads 11 on the chip 10 is formed in the central portion (10a) and both end portions (10b), the first inner lead on the pad (11a) of the central portion (10a) (21) was bonded with an adhesive, and the second inner lead (22) shows a state of being placed in the space (3a) of the package (3). That is, the inner lead is divided into first and inner leads 21 and 22, and the second inner lead 22 is positioned outside the chip 10, thereby changing the size of the chip 10 or the package ( The layout can be easily conceived in correspondence with the space portion 3a of 3). The arrangement of the pads 11 is fixed to the central portion 10a and both end portions 10b and is not only laid out, but also can be changed as necessary, and the layout of the first and second internal leads 21 and 22 corresponding thereto, as well as the package. It goes without saying that the layout of (3) can also be changed. In the present invention, a lead frame is used, and then packaging and forming is omitted since it is a general technique.
이상과 같이 본 고안은 칩위의 패드배열 설계상의 범위를 넓혀 다양한 패키지의 형상은 디자인할수 있게 하였고 또한 리드프레임의 내부리드 및 패키지의 레이아웃의 한계성을 극복한것으로, 칩과 패키지의 공간부를 활용하여 패드가 칩의 양측단부 가장자리에 위치되고 패키지의 형상이 길이방향으로 긴 형태로 공간부가 많은 반도체 장치에 LOC 반도체 조립방식을 적용가능케하여 칩과 패키지의 디자인 설계상의 문제점을 해결한 우수한 고안이다.As described above, the present invention has broadened the range of pad array design on the chip to design various package shapes and also overcomes limitations of the lead of the inner frame of the lead frame and the layout of the package. The LOC semiconductor assembly method can be applied to semiconductor devices having a large amount of space in the shape of the package which is located at the edges of both sides of the chip and the shape of the package is long in the longitudinal direction.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92015611U KR0124547Y1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor device for multi-type lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92015611U KR0124547Y1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor device for multi-type lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940006488U KR940006488U (en) | 1994-03-25 |
| KR0124547Y1 true KR0124547Y1 (en) | 1998-10-01 |
Family
ID=19338675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92015611U KR0124547Y1 (en) | 1992-08-19 | 1992-08-19 | Semiconductor device for multi-type lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0124547Y1 (en) |
-
1992
- 1992-08-19 KR KR92015611U patent/KR0124547Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940006488U (en) | 1994-03-25 |
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