KR200169730Y1 - Lead frame for semiconductor package - Google Patents
Lead frame for semiconductor package Download PDFInfo
- Publication number
- KR200169730Y1 KR200169730Y1 KR2019970025550U KR19970025550U KR200169730Y1 KR 200169730 Y1 KR200169730 Y1 KR 200169730Y1 KR 2019970025550 U KR2019970025550 U KR 2019970025550U KR 19970025550 U KR19970025550 U KR 19970025550U KR 200169730 Y1 KR200169730 Y1 KR 200169730Y1
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- South Korea
- Prior art keywords
- lead frame
- paddle
- semiconductor chip
- wire
- die
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
본 고안은 반도체 패키지의 리드프레임에 관한 것으로, 종래 기술에 의한 반도체 패키지의 리드프레임은 패키지 작업시 반도체 칩의 크기가 다양해지면서 그에 따른 리드프레임의 패들 또한 다양해져야 하는 문제가 발생하며, 상기 패들의 크기가 달라짐에 따라 와이어본딩시 여러 가지 제약이 발생하게 되는 바, 이에 본 고안은 반도체 칩(11)이 탑재되는 다이패들(12)의 평면상에 사방으로 다수개의 와이어 삽입공(16)을 형성하고, 상기 다이패들(12)의 저면에 절연성 접착 테이프를 부착하여 인너리드(13)의 일측 상면에 다이패들(12)을 접착한 것을 특징으로 하는 반도체 패키지의 리드프레임을 제공함으로써, 인너리드 상면으로 다이패들이 소정량 돌출되어 있어 칩의 탑재 기능 및 열방출 기능을 극대화할 수 있고, 다이패들의 사방에는 와이어 삽입공이 관통되어 와이어의 길이를 조절할 수 있으므로 반도체 칩의 크기에 상관없이 한 종류의 리드프레임으로 와이어본딩 작업이 가능하다.The present invention relates to a lead frame of a semiconductor package, the lead frame of the semiconductor package according to the prior art is a problem that the paddle of the lead frame according to the size of the semiconductor chip is diversified at the time of the package operation is also caused, the paddle As the size is changed, various restrictions occur during wire bonding, and the present invention provides a plurality of wire insertion holes 16 on all sides of the die paddle 12 on which the semiconductor chip 11 is mounted. Forming and attaching an insulating adhesive tape to the bottom surface of the die paddle 12 to provide the lead frame of the semiconductor package, wherein the die paddle 12 is adhered to an upper surface of the inner lead 13. The die pads protrude a predetermined amount to the upper surface of the inner lead to maximize the chip mounting and heat dissipation functions, and wire insert holes are provided on all sides of the die paddles. Since the length of the wire can be adjusted to penetrate, wire bonding can be performed with one kind of lead frame regardless of the size of the semiconductor chip.
Description
본 고안은 반도체 패키지의 리드프레임에 관한 것으로, 특히 반도체 칩에서 발생되는 열을 용이하게 방출하고 칩 크기에 구애받지 않으면서 패키지 제조 작업이 가능한 리드프레임에 관한 것이다.The present invention relates to a lead frame of a semiconductor package, and more particularly, to a lead frame capable of easily dissipating heat generated from a semiconductor chip and making a package manufacturing operation regardless of the chip size.
일반적으로 리드프레임은 반도체 칩이 부착 고정되기 위한 패들과, 그 패들에 고정되는 반도체 칩의 패드에 와이어에 의해 연결되어 반도체 칩과 통전되기 위한 것으로 상기 패들의 주변에 대칭형으로 다수개 형성되는 인너리드와, 그 인너리드와 일체로 그 연장선상에 위치하며 외부회로에 연결되어 통전되기 위한 다수개의 아웃리드로 구성되어 있다.In general, a lead frame is a paddle for attaching and fixing a semiconductor chip, and an inner lead which is symmetrically formed in a circumferential manner around the paddle and is electrically connected to a pad of a semiconductor chip fixed to the paddle by a wire. And a plurality of outleads integrally with the inner lead and connected to an external circuit for energizing.
이와 같이 구성된 리드프레임은 반도체 패키지 제조 공정 중의 하나인 와이어본딩 공정을 거치게 되는데, 와이어본딩이란 패들에 부착된 칩의 외부 연결단자인 패드와 인너리드를 금이나 알루미늄으로 이루어진 가는 와이어로 연결하여 전기적 신호가 흐를 수 있도록 하는 공정을 말하는 바, 와이어본딩 공정을 거치기 위한 종래의 리드프레임이 도 1에 도시되어 있다.The lead frame configured as described above undergoes a wire bonding process, which is one of the semiconductor package manufacturing processes. Wire bonding is an electrical signal by connecting an inner lead of a pad and an inner lead of a chip attached to a paddle with a thin wire made of gold or aluminum. Referring to the process for allowing the flow of the bar, a conventional lead frame for the wire bonding process is shown in FIG.
도 1은 종래의 와이어본딩된 리드프레임의 구조를 개략적으로 보인 평면도로서, 일반적인 반도체 패키지의 리드프레임(1)은 반도체 칩(4)을 탑재하여 본딩하기 위한 다이패들(2)과, 그 다이패들(2)의 주변에 대칭형으로 다수개 형성되며 반도체 칩(4)의 전기적인 통전기능을 외부로 연결하기 위한 인너리드(3)와, 그 인너리드(3)와 일체로 연장 형성되는 아웃리드(미도시)로 구성된다.1 is a plan view schematically illustrating a structure of a conventional wire bonded lead frame, in which a lead frame 1 of a general semiconductor package includes a die paddle 2 for mounting and bonding a semiconductor chip 4 and a die thereof. A plurality of symmetrical shapes are formed around the paddle 2, and the inner lead 3 for connecting the electrical conduction function of the semiconductor chip 4 to the outside, and the extension formed integrally with the inner lead 3, It consists of a lead (not shown).
이와 같이 구성된 종래 기술에 의한 반도체 패키지의 리드프레임의 작용에 대해서 설명하면 다음과 같다.Referring to the operation of the lead frame of the semiconductor package according to the prior art configured as described above are as follows.
리드프레임(1)의 다이패들(2) 위에 에폭시 수지를 도포하여 그 위에 반도체 칩(4)을 본딩하고, 상기 반도체 칩(4)의 패드(4a)와 인너리드(3)를 와이어(5)로 연결한 후, 상기 반도체 칩(4)이 부착된 패들(2)과 인너리드(3)를 몰딩컴파운드로 몰딩하여 패키지 몸체(미도시)를 형성한다.An epoxy resin is applied on the die paddle 2 of the lead frame 1 to bond the semiconductor chip 4 thereon, and the pad 4a and the inner lead 3 of the semiconductor chip 4 are wired 5. After the connection, the paddle 2 and the inner lead 3 to which the semiconductor chip 4 is attached are molded with a molding compound to form a package body (not shown).
그러나, 상술한 바와 같은 종래 기술에 의한 반도체 패키지의 리드프레임은, 패키지 작업시 반도체 칩(4)의 크기가 다양해지면서 그에 따른 리드프레임(1)의 패들(2) 또한 다양해져야 하는 문제가 발생하며, 상기 패들(2)의 크기가 달라짐에 따라 와이어본딩시 여러 가지 제약이 발생하게 되는 문제점이 있었다.However, in the lead frame of the semiconductor package according to the related art as described above, the size of the semiconductor chip 4 is diversified during package operation, and thus the paddle 2 of the lead frame 1 also needs to be diversified. As the paddle 2 is changed in size, various limitations occur in wire bonding.
본 고안은 상기 문제점을 감안하여 안출된 것으로서, 반도체 칩의 크기나 특성에 상관없이 한 종류의 리드프레임으로 와이어본딩 공정 진행이 가능한 리드프레임을 제공하는데 그 목적이 있다.The present invention has been made in view of the above problems, and an object of the present invention is to provide a lead frame capable of performing a wire bonding process with one type of lead frame regardless of the size or characteristics of a semiconductor chip.
또한, 리드프레임의 패들이 반도체 칩의 탑재 기능 및 열방출 기능을 극대화할 수 있는 리드프레임을 제공하는데 목적이 있다.In addition, the purpose of the paddle of the lead frame is to provide a lead frame that can maximize the mounting function and heat dissipation function of the semiconductor chip.
도 1은 패키지 제조 공정시 종래 리드프레임의 구조를 개략적으로 보인 구성도로서,1 is a schematic view showing the structure of a conventional lead frame during a package manufacturing process,
(a)는 측면도,(a) is a side view,
(b)는 평면도,(b) is a plan view,
도 2는 본 고안에 의한 리드프레임을 개략적으로 보인 평면도,Figure 2 is a plan view schematically showing a lead frame according to the present invention,
도 3 및 도 4는 각각 반도체 칩의 크기가 작은 경우와 큰 경우의 패키지 제조 공정시 본 고안에 의한 리드프레임의 구조를 개략적으로 보인 구성도로서,3 and 4 are schematic diagrams showing the structure of a lead frame according to the present invention during a package manufacturing process in a case where the size of the semiconductor chip is small and large, respectively.
(a)는 측면도,(a) is a side view,
(b)는 평면도,(b) is a plan view,
** 도면의 주요부분에 대한 부호의 설명 **** Explanation of symbols for main parts of drawings **
10 ; 리드프레임 11 ; 반도체 칩10; Leadframe 11; Semiconductor chip
12 ; 다이패들 13 ; 인너리드12; Die paddle 13; Inner lead
14 ; 절연성 접착 테이프 15 ; 와이어14; Insulating adhesive tape 15; wire
16 ; 와이어 삽입공16; Wire inserter
상기 목적을 달성하기 위한 본 고안은, 반도체 칩이 탑재되는 다이패들의 평면상에 사방으로 다수개의 와이어 삽입공을 형성하고, 상기 다이패들의 저면에 절연성 접착 테이프를 부착하여 인너리드의 일측 상면에 다이패들을 접착한 것을 특징으로 하는 반도체 패키지의 리드프레임이 제공된다.The present invention for achieving the above object, to form a plurality of wire insertion holes in all directions on the plane of the die pads on which the semiconductor chip is mounted, and attaching an insulating adhesive tape to the bottom of the die pads on the upper surface of one side of the inner lead There is provided a lead frame of a semiconductor package, characterized in that the die pads are bonded.
이하, 첨부된 도면을 참고하여 본 고안에 의한 반도체 패키지의 리드프레임의 실시예에 대해서 설명하면 다음과 같다.Hereinafter, an embodiment of a lead frame of a semiconductor package according to the present invention will be described with reference to the accompanying drawings.
도 2는 본 고안의 리드프레임의 구조를 개략적으로 보인 평면도로서, 도시된 바와 같이, 본 고안에 의한 반도체 패키지의 리드프레임(10)은 리드프레임(10)으로부터 분리가 가능하며 다수개의 패드(11a)가 형성된 반도체 칩(11)을 탑재하여 본딩하기 위한 장방형의 다이패들(12)과, 그 다이패들(12)의 저면에 접착 형성되며 상기 반도체 칩(11)의 패드(11a)에 부착된 와이어(15)와 연결되는 인너리드(13)와, 그 인너리드(13)와 일체로 연장 형성되는 아웃리드(미도시)로 구성된다.2 is a plan view schematically showing the structure of the lead frame of the present invention, as shown, the lead frame 10 of the semiconductor package according to the present invention can be separated from the lead frame 10 and a plurality of pads (11a) ) And a rectangular die paddle 12 for mounting and bonding the semiconductor chip 11 formed thereon and attached to the pad 11a of the semiconductor chip 11. It consists of an inner lead 13 connected to the wire 15 and an out lead (not shown) extending integrally with the inner lead 13.
그리고 상기 리드프레임(10)에 있어서 다이패들(12)은 평면상에 사방으로 다수개의 와이어 삽입공(16)이 장방형으로 통공되어 있다.In the lead frame 10, the die paddle 12 has a plurality of wire insertion holes 16 rectangular in all directions on a plane.
한편, 상기 다이패들(12)의 저면과 인너리드(13)의 상면에는 절연성 접착 테이프(미도시)가 접착되어 상기 인너리드(13)와 다이패들(12)을 접착 고정시켜 준다.Meanwhile, an insulating adhesive tape (not shown) is attached to the bottom of the die paddle 12 and the top of the inner lead 13 to fix and fix the inner lead 13 and the die paddle 12.
상기와 같이 구성된 본 고안에 의한 반도체 패키지의 리드프레임의 작용에 대해서 설명하면 다음과 같다.Referring to the operation of the lead frame of the semiconductor package according to the present invention configured as described above are as follows.
도 3 및 도 4는 각각 반도체 칩의 크기가 작은 경우와 큰 경우의 패키지 제조 공정시 본 고안에 의한 리드프레임을 보인 도면으로 (a)는 측면도 (b)는 평면도이다.3 and 4 are a view showing a lead frame according to the present invention during the package manufacturing process when the size of the semiconductor chip is small and large, respectively, (a) is a side view (b) is a plan view.
리드프레임(10)에 있어서 별도로 분리된 다이패들(12)의 저면에 절연성 접착 테이프를 부착하여 인너리드(13)의 일측 상면에 접착 고정시킨다.In the lead frame 10, an insulating adhesive tape is attached to a bottom surface of the die paddle 12 separated from the lead frame 10 and fixed to an upper surface of one side of the inner lead 13.
인너리드(13)의 상방향으로 소정량 돌출되어 접착된 패들(12)에 반도체 칩(11)을 탑재하여 본딩하고, 그 반도체 칩(11)의 패드(11a) 상면에 부착된 와이어(15)를 상기 다이패들(12)의 사방으로 형성된 와이어 삽입공(16)에 삽입한 후 와이어본딩 공정을 실시한다.The semiconductor chip 11 is mounted and bonded to the paddle 12, which protrudes a predetermined amount in the upward direction of the inner lead 13, and is attached to the upper surface of the pad 11a of the semiconductor chip 11. Is inserted into the wire insertion hole 16 formed in all directions of the die paddle 12, and then performs a wire bonding process.
이때, 반도체 칩(11)의 크기가 작은 경우에는 다이패들(12)에 형성된 와이어 삽입공(16) 중에서 반도체 칩(11)과 가까운 쪽의 와이어 삽입공(16)에 와이어(15)를 삽입하여 본딩하고, 반도체 칩(11)의 크기가 큰 경우에는 먼 쪽의 와이어 삽입공(16)에 와이어(15)를 삽입하여 본딩함으로써 와이어(15)가 너무 쳐지거나 팽팽해지는 것을 조절할 수 있다.At this time, when the size of the semiconductor chip 11 is small, the wire 15 is inserted into the wire insertion hole 16 near the semiconductor chip 11 among the wire insertion holes 16 formed in the die paddle 12. And bonding, and when the size of the semiconductor chip 11 is large, by inserting and bonding the wire 15 into the far wire insertion hole 16, it is possible to control that the wire 15 is too sagging or taut.
이상에서와 같이 본 고안에 의한 반도체 패키지의 리드프레임은, 인너리드 상면으로 다이패들이 소정량 돌출되어 있어 칩의 탑재 기능 및 열방출 기능을 극대화할 수 있고, 다이패들의 사방에는 와이어 삽입공이 관통되어 와이어의 길이를 조절할 수 있으므로 반도체 칩의 크기에 상관없이 한 종류의 리드프레임으로 와이어본딩 작업이 가능하다.As described above, the lead frame of the semiconductor package according to the present invention has a large amount of die pads protruding from the inner lead surface to maximize chip mounting and heat dissipation functions, and wire insertion holes penetrate the die pads in all directions. Since the length of the wire can be adjusted, wire bonding is possible with one kind of lead frame regardless of the size of the semiconductor chip.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970025550U KR200169730Y1 (en) | 1997-09-09 | 1997-09-09 | Lead frame for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970025550U KR200169730Y1 (en) | 1997-09-09 | 1997-09-09 | Lead frame for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990012450U KR19990012450U (en) | 1999-04-06 |
| KR200169730Y1 true KR200169730Y1 (en) | 2000-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970025550U KR200169730Y1 (en) | 1997-09-09 | 1997-09-09 | Lead frame for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200169730Y1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100426330B1 (en) * | 2001-07-16 | 2004-04-08 | 삼성전자주식회사 | Ultra-Thin Semiconductor Package Device Using a Support Tape |
-
1997
- 1997-09-09 KR KR2019970025550U patent/KR200169730Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990012450U (en) | 1999-04-06 |
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