JPH0795580B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0795580B2 JPH0795580B2 JP59250034A JP25003484A JPH0795580B2 JP H0795580 B2 JPH0795580 B2 JP H0795580B2 JP 59250034 A JP59250034 A JP 59250034A JP 25003484 A JP25003484 A JP 25003484A JP H0795580 B2 JPH0795580 B2 JP H0795580B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead
- package
- comb
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、ホール素子やFETの素子のパッケージの小型
化・薄型化を可能とし、インサートマシンによる自動装
置が容易であり、かつ熱拡散がすぐれている半導体装置
に関するものである。TECHNICAL FIELD The present invention enables miniaturization and thinning of a package of a Hall element or a FET element, an automatic machine by an insert machine is easy, and heat diffusion is excellent. Related semiconductor devices.
従来の技術 従来のいわゆるフェースボンディングによりリードへ取
付けられた半導体装置は第５図に示すように、セラミッ
ク基板上にリードを接着したものに素子を取り付け、こ
れを樹脂により封止している。2. Description of the Related Art As shown in FIG. 5, a conventional semiconductor device attached to a lead by so-called face bonding has an element attached to a ceramic substrate with leads attached thereto, which is sealed with a resin.
発明が解決しようとする問題点 このような従来の構成ではパッケージの厚みがセラミッ
ク基板のために厚くなるばかりか、リードはパッケージ
の横方向へのみ出る構造となり、又、熱拡散に対しても
問題を有していた。Problems to be Solved by the Invention In such a conventional configuration, not only is the thickness of the package increased due to the ceramic substrate, but the leads are only exposed in the lateral direction of the package, and there is also a problem with heat diffusion. Had.
本発明は上記問題点に鑑み、パッケージの厚みが薄く、
パッケージ底面にもリードを有し、又、熱拡散に対して
も有利な構成である半導体装置を提供することを目的と
する。In view of the above problems, the present invention has a thin package,
It is an object of the present invention to provide a semiconductor device having leads also on the bottom surface of a package and having an advantageous structure for heat diffusion.
問題点を解決するための手段 本発明は、両面の平坦なコムリードの一面に半導体素子
のチップを対面接続して、前記コムリードの他面の全域
を封止樹脂外囲体の外面とほぼ同等面内に露出させた構
造になしたものである。Means for Solving the Problems The present invention is directed to face-to-face connection of a chip of a semiconductor element to one surface of a flat comb lead on both surfaces, and the entire area of the other surface of the comb lead is almost the same as the outer surface of a sealing resin envelope. The structure is exposed in the same plane.
作用 上記の構成により、パッケージの薄型化ができ、またコ
ムリードが上面より見たときパッケージより外にはみ合
さなくとも、セットへ実装することができ、インサート
マシンによる自動装着も容易になる。又、素子からの熱
は露出したコムリードにより、効果的に拡散される。Operation With the above configuration, the package can be made thinner, and it can be mounted on a set even if the comb lead does not fit outside the package when viewed from the top, facilitating automatic mounting by an insert machine. . Also, the heat from the device is effectively diffused by the exposed comb leads.
実施例 第１図は、本発明の一実施例による半導体装置の断面構
造図であり、第１図において１はアップサイドダウンに
対面接続して組み込まれたチップ、２はエポキシ等の樹
脂、３はコムリードでCuやFe等の導体を用い、その表面
にNiメッキが被着され、チップボンディングを容易にす
る加工を施している。４は、そのコム上に組立後メッキ
やディップにて形成した半田層で、この部分をプリント
基板上の配線面に密着接続し易くしたものである。５は
チップに形成されたオーミック電極や配線電極である。
６はチップの電極とコム面とを接触，固定し結線させる
ためのAgペースト等のろう材で、７はチップ内の半絶縁
性の部分を示しており、８はチップ内のインオン注入や
エピタキシャル等において形成された活性領域部分を示
している。９はチップ上に形成された保護膜を示してい
る。Embodiment 1 FIG. 1 is a sectional structural view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 1 is a chip incorporated by face-to-face connection in upside down, 2 is a resin such as epoxy, and 3 is a resin. Uses a conductor such as Cu or Fe in the comb lead, and the surface of the conductor is coated with Ni plating, which is processed to facilitate chip bonding. A solder layer 4 is formed on the comb by assembling after plating or dipping, and this portion facilitates close contact with the wiring surface on the printed circuit board. Reference numeral 5 is an ohmic electrode or a wiring electrode formed on the chip.
6 is a brazing material such as Ag paste for contacting, fixing and connecting the chip electrode and comb surface, 7 is a semi-insulating part in the chip, and 8 is in-on injection or epitaxial in the chip. The active region portion formed in FIG. Reference numeral 9 indicates a protective film formed on the chip.
第２図は第１図に示したものの上から見た外観図であ
り、第３図は、同じものを下から見た外観図である。FIG. 2 is an external view of the same thing as shown in FIG. 1 seen from above, and FIG. 3 is an external view of the same thing seen from below.
第４図は、本発明の一実施例で、リード線を必要とする
場合の半導体装置の断面構造図である。コムがパッケー
ジ側面より出ている所が第１図と異なる点で他は同じ構
造である。FIG. 4 is a sectional structural view of a semiconductor device in the case where a lead wire is required according to an embodiment of the present invention. The structure is the same except that the comb is out of the side of the package as shown in FIG.
発明の効果 以上のように本発明によれば、コムリードの一面に半導
体素子を対面接続して、このコムリードの他面の全域を
露出させて樹脂封入することにより、パッケージの薄型
化がはかれ、かつ熱拡散に対しても有効な半導体装置と
なり、又、パッケージ下部の外面とほぼ同等面内に電極
リードを有するため、インサートマシンによる自動装着
も容易になる等、実用上すぐれた効果がある。As described above, according to the present invention, the semiconductor element is face-to-face connected to one surface of the comb lead, and the entire area of the other surface of the comb lead is exposed and resin-encapsulated, thereby reducing the thickness of the package. In addition, it is a semiconductor device that is also effective against heat diffusion, and because it has an electrode lead in the same plane as the outer surface of the lower part of the package, automatic mounting by an insert machine is easy, and other practical advantages. is there.
第１図は本発明の一実施例による半導体装置を示す断面
構造図、第２図は第１図を斜上部より見たところの外観
図、第３図は斜下部より見たところの外観図、第４図
は、本発明の別の実施例による半導体装置の断面構造
図、第５図は従来の実施例による半導体装置を示す断面
構造図である。 １……素子、２……樹脂、３……コム、４……半田層、
５……電極、６……ろう材、10……セラミック基板。FIG. 1 is a cross-sectional structural view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is an external view of FIG. 1 as seen from an obliquely upper portion, and FIG. 3 is an external view as seen from an obliquely lower portion. 4 is a sectional structural view of a semiconductor device according to another embodiment of the present invention, and FIG. 5 is a sectional structural view showing a semiconductor device according to a conventional embodiment. 1 ... element, 2 ... resin, 3 ... com, 4 ... solder layer,
5 ... Electrode, 6 ... Brazing material, 10 ... Ceramic substrate.
Claims (2)
対面接続して、前記リードの他面の全域を封止樹脂外囲
体の外面とほぼ同等面内に露出し、前記半導体素子の表
面下部に少なくとも平坦な封止樹脂外囲体面を設けたこ
とを特徴とする半導体装置。1. A semiconductor element is face-to-face connected to one surface of a flat lead on both surfaces, and the entire area of the other surface of the lead is exposed in a plane substantially equal to the outer surface of the encapsulating resin envelope, and A semiconductor device, wherein at least a flat surface of a sealing resin envelope is provided below the surface.
許請求の範囲第項高記載の半導体装置。2. The semiconductor device according to claim 1, wherein a solder layer is attached to the exposed surface of the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59250034A JPH0795580B2 (en) | 1984-11-27 | 1984-11-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59250034A JPH0795580B2 (en) | 1984-11-27 | 1984-11-27 | Semiconductor device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6158410A Division JP2532821B2 (en) | 1994-07-11 | 1994-07-11 | Semiconductor device |
| JP6286588A Division JP2725719B2 (en) | 1994-11-21 | 1994-11-21 | Electronic component and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61128548A JPS61128548A (en) | 1986-06-16 |
| JPH0795580B2 true JPH0795580B2 (en) | 1995-10-11 |
Family
ID=17201842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59250034A Expired - Lifetime JPH0795580B2 (en) | 1984-11-27 | 1984-11-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0795580B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977613A (en) * | 1996-03-07 | 1999-11-02 | Matsushita Electronics Corporation | Electronic component, method for making the same, and lead frame and mold assembly for use therein |
| JP4303699B2 (en) * | 2002-04-01 | 2009-07-29 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
| JP2005057067A (en) * | 2003-08-05 | 2005-03-03 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50105365U (en) * | 1974-02-05 | 1975-08-29 | ||
| JPS54106776U (en) * | 1978-01-12 | 1979-07-27 | ||
| JPS58204547A (en) * | 1982-05-25 | 1983-11-29 | Citizen Watch Co Ltd | Sealing method for ic |
| JPS596839U (en) * | 1982-07-07 | 1984-01-17 | 日本電気株式会社 | semiconductor equipment |
| JPS59193039A (en) * | 1983-04-15 | 1984-11-01 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS59227143A (en) * | 1983-06-07 | 1984-12-20 | Dainippon Printing Co Ltd | Package of integrated circuit |
-
1984
- 1984-11-27 JP JP59250034A patent/JPH0795580B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61128548A (en) | 1986-06-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |