JPS62195Y2 - - Google Patents
Info
- Publication number
- JPS62195Y2 JPS62195Y2 JP4782380U JP4782380U JPS62195Y2 JP S62195 Y2 JPS62195 Y2 JP S62195Y2 JP 4782380 U JP4782380 U JP 4782380U JP 4782380 U JP4782380 U JP 4782380U JP S62195 Y2 JPS62195 Y2 JP S62195Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solid
- recess
- package
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 24
- 238000003384 imaging method Methods 0.000 claims description 9
- 238000004806 packaging method and process Methods 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910015365 Au—Si Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Description
【考案の詳細な説明】
本考案は、固体撮像装置に使用するパツケージ
に関するものである。[Detailed Description of the Invention] The present invention relates to a package used in a solid-state imaging device.
MOS−IC（絶縁ゲート型電界効果トランジス
タの集積回路）、CCD（電荷結合素子）等を使用
した固体撮像装置は、一般にセラミツク・パツケ
ージの所要位置にデバイス即ち撮像素子を貼り合
せ、且つ撮像素子の電極とパツケージの導電端子
間をワイヤーボンドして構成される。カラー固体
撮像装置の場合はさらに撮像素子上に色分解フイ
ルタが配される。特にカラー固体撮像装置に於て
は、撮像素子と色分解フイルター間の合せ精度が
通常数μと厳しく、そのために撮像素子と色分解
フイルターの相対位置の組合せを正確に行う必要
がある。先に本出願人はこの点を考慮して撮像素
子をパツケージに対してダイボンドする際にある
程度正確に撮像素子の位置決めができるようにし
た、パツケージを提案したが、本考案はこれをさ
らに改良したものである。 Solid-state imaging devices using MOS-ICs (insulated gate field-effect transistor integrated circuits), CCDs (charge-coupled devices), etc. generally have devices, that is, imaging elements, bonded to desired positions on a ceramic package, and It is constructed by wire bonding between the electrode and the conductive terminal of the package. In the case of a color solid-state imaging device, a color separation filter is further arranged on the imaging element. Particularly in color solid-state imaging devices, the accuracy of alignment between the image sensor and the color separation filter is usually as severe as several microns, and therefore it is necessary to accurately combine the relative positions of the image sensor and the color separation filter. Taking this point into consideration, the applicant previously proposed a package that allows for a certain degree of accurate positioning of the image sensor when die-bonding the image sensor to the package, but the present invention further improves this. It is something.
先づ、本考案の理解を容易にするために、第１
図及び第２図を用いて先に提案したパツケージを
説明する。同図において、１は積層セラミツク基
板２〔２ａ，２ｂ，２ｃ及び２ｄ〕からなるパツ
ケージを示し、第１層の基板２ａの上面には開口
部３が設けられ、この開口部３に臨んで第２層及
び第３層の基板２ｂ及び２ｃによつて固体撮像素
子４を配置する凹所５が設けられる。第２層の基
板２ｂの凹所５に臨む２辺の内側には夫々素子４
の位置決用の突起６が設けられ、さらに第２層の
基板２ｂの面にはリード配線パターンが被着さ
れ、その一方の導電端子７が開口部３に臨む凹所
５の周辺にまで延長され、他端が外部リード１０
に接続される。素子４は凹所５内において突起６
によつて略所要位置に位置決めされて接着剤８
（半田、Agペースト、Au−Si等）を介してダイ
ボンドされ、次に素子４と端子７間が例えばAu
線９を介してワイヤボンドされる。１Ａはパツケ
ージ１の位置決め用凹部である。なお、この場合
第２層の基板２ｂの厚さt1は素子４の厚さt2より
大（t1＞t2）に形成される。 First, in order to facilitate understanding of the present invention, the first
The previously proposed package will be explained using FIG. In the figure, reference numeral 1 indicates a package consisting of laminated ceramic substrates 2 [2a, 2b, 2c, and 2d], and an opening 3 is provided on the upper surface of the first layer substrate 2a. A recess 5 in which the solid-state image sensor 4 is placed is provided by the second and third layer substrates 2b and 2c. On the inside of the two sides facing the recess 5 of the second layer substrate 2b are elements 4, respectively.
Further, a lead wiring pattern is adhered to the surface of the second layer substrate 2b, and one of the conductive terminals 7 extends to the periphery of the recess 5 facing the opening 3. and the other end is the external lead 10
connected to. The element 4 has a protrusion 6 in the recess 5.
The adhesive 8 is positioned approximately at the desired position by
(solder, Ag paste, Au-Si, etc.), and then between the element 4 and the terminal 7, for example, Au
Wire bonding is performed via line 9. 1A is a recess for positioning the package 1. In this case, the thickness t 1 of the second layer substrate 2b is larger than the thickness t 2 of the element 4 (t 1 >t 2 ).
しかるに、かかるパツケージ１においては、素
子４をダイボンドしたときに、素子４の下面の接
着剤８が素子４の側面に寄り、突起６と素子４間
を通して這い上り、素子表面でシヨートし、又は
導電端子７とシヨートし、さらには又突起６に這
い上つた接着剤８とAu線９がシヨートする等の
懼れがあつた。 However, in such a package 1, when the element 4 is die-bonded, the adhesive 8 on the lower surface of the element 4 approaches the side surface of the element 4, creeps up through between the protrusion 6 and the element 4, shoots on the element surface, or becomes conductive. There was a fear that the adhesive 8 and the Au wire 9 that had climbed up onto the protrusion 6 would also shoot out.
本考案は、この点を改良し歩留りの向上を図つ
たものである。以下第３図及び第４図を用いて本
考案による固体撮像素子のパツケージを説明しよ
う。 The present invention aims to improve this point and improve the yield. The package of the solid-state image sensing device according to the present invention will be explained below with reference to FIGS. 3 and 4.
第３図及び第４図において、１１は積層セラミ
ツク基板２〔２ａ，２ｂ，２ｃ及び２ｄ〕からな
る本考案のパツケージを全体として示す。第１層
の基板２ａの上面には所定の大きさの開口部３が
形成され、この開口部３に臨んで第２層及び第３
層の基板２ｂ及び２ｃによる凹所５が形成され
る。この凹所５はデバイス即ち固体撮像素子４が
配置されるものであり、開口部３より小面積に形
成される。第２層の基板２ｂの凹所５に臨む隣り
合う２辺に対応する内側には夫々素子４の位置決
め用の突起６が形成される。この突起６は凹所５
を構成する第２層の基板２ｂに一体に形成され
る。１１Ａはパツケージ１１の位置決め用凹部で
ある。 In FIGS. 3 and 4, reference numeral 11 generally indicates a package according to the present invention consisting of laminated ceramic substrates 2 [2a, 2b, 2c and 2d]. An opening 3 of a predetermined size is formed in the upper surface of the first layer substrate 2a, and the second and third layers face this opening 3.
A recess 5 is formed by the substrates 2b and 2c of the layers. The recess 5 is where a device, that is, the solid-state image sensor 4 is placed, and is formed to have a smaller area than the opening 3. Protrusions 6 for positioning the elements 4 are formed on the inside corresponding to two adjacent sides facing the recess 5 of the second layer substrate 2b, respectively. This protrusion 6 is the recess 5
It is formed integrally with the second layer substrate 2b that constitutes the. 11A is a recess for positioning the package 11.
しかして、本考案においては、第２層の基板２
ｂの面にリード配線パターンを印刷形成し、その
一端の各導電端子７を開口部３に臨む凹所周辺の
段部上面に導出するものであるが、このとき導電
端子７は突起６より延長する部分１２（斜視図
示）を除いて夫々所定間隔を保つて形成するよう
になす。配線パターンの各他端は基板外側に延長
し外部リード１０に接続する。又、第２層の基板
２ｂの厚さt1を素子４の厚さt2より薄く（t1＜t2）
形成する。例えば素子の厚さt2を0.3mmとする
と、基板２ｂの厚さt1は0.25mm程度とするを可と
する。このパツケージ１１に対して素子４を接着
剤８（半田、Agペイント、Au−Si等）を介して
ダイボンドし、次で素子４と端子７間をAu線９
を介してワイヤボンドする。 However, in the present invention, the second layer substrate 2
A lead wiring pattern is printed on the surface b, and each conductive terminal 7 at one end thereof is led out to the upper surface of the stepped portion around the recess facing the opening 3. At this time, the conductive terminal 7 extends from the protrusion 6. They are formed at predetermined intervals apart from each other, except for a portion 12 (shown in a perspective view). The other ends of each wiring pattern are extended to the outside of the board and connected to external leads 10. Also, the thickness t 1 of the second layer substrate 2b is made thinner than the thickness t 2 of the element 4 (t 1 <t 2 ).
Form. For example, if the thickness t 2 of the element is 0.3 mm, the thickness t 1 of the substrate 2b may be about 0.25 mm. The element 4 is die-bonded to this package 11 via an adhesive 8 (solder, Ag paint, Au-Si, etc.), and then the Au wire 9 is connected between the element 4 and the terminal 7.
Wire bond through.
上述せる構成によれば、第２層の基板２ｂの厚
さt1が素子４の厚みt2より薄く（t1＜t2）形成され
ているので、素子４を突起６により位置決めして
ダイボンドしたときに仮りに余分な接着剤８が素
子４と突起６間より這い上り導電端子７の面側に
流れ出すことになつたとしても、素子４の面上に
這い上ることはなく、接着剤８による素子４での
Alパツド部間のシヨート、或はAlパツドと素子
４のサブストレート間のシヨートは起らない。し
かも、接着剤８がパツケージ側の導電端子７側に
流れ出しても、突起６に対応した位置には導電端
子７が形成されていないので、導電端子７間のシ
ヨート事故は発生しない。尚、突起６の突出し寸
法を適当に選ぶことにより導電端子７と接着剤８
とのシヨートは回避できる。 According to the above-mentioned structure, since the thickness t 1 of the second layer substrate 2b is formed to be thinner than the thickness t 2 of the element 4 (t 1 <t 2 ), the element 4 is positioned by the protrusion 6 and die bonded. Even if excess adhesive 8 were to creep up from between the element 4 and the protrusion 6 and flow out onto the surface of the conductive terminal 7, it would not creep onto the surface of the element 4 and the adhesive 8 would In element 4 due to
No shortening occurs between the Al pads or between the Al pad and the substrate of the element 4. Furthermore, even if the adhesive 8 flows out toward the conductive terminals 7 on the package side, since the conductive terminals 7 are not formed at the positions corresponding to the protrusions 6, no shoot accident between the conductive terminals 7 will occur. In addition, by appropriately selecting the protrusion dimension of the protrusion 6, the conductive terminal 7 and the adhesive 8
This can be avoided.
従つて、このようなパツケージを用いることに
より歩留りが向上し、且つ信頼性の高い固体撮像
装置が得られるものである。 Therefore, by using such a package, the yield can be improved and a highly reliable solid-state imaging device can be obtained.
第１図は本考案の説明に供する固体撮像素子の
パツケージの例を示す断面図、第２図はその平面
図、第３図は本考案による固体撮像素子のパツケ
ージの例を示す断面図、第４図はその平面図であ
る。
２は積層基板、３は開口部、４は撮像素子、５
は凹部、６は突起、７は導電端子である。
FIG. 1 is a cross-sectional view showing an example of a package of a solid-state image sensor according to the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a cross-sectional view showing an example of a package of a solid-state image sensor according to the present invention. Figure 4 is a plan view thereof. 2 is a laminated substrate, 3 is an opening, 4 is an image sensor, 5
6 is a concave portion, 6 is a protrusion, and 7 is a conductive terminal.
Claims (1)
素子を配置する凹所が設けられ、上記積層基板に
おける１の基板の該凹所に臨む内側に上記固体撮
像素子の位置決め用突起が形成されると共に、上
記１の基板の凹所周辺の上面に上記突起の延長部
分を除いて導電端子が形成され、上記１の基板の
厚さが上記固体撮像素子の厚さより薄く形成され
て成る固体撮像素子のパツケージ。 The substrate is made of a laminated substrate, and a recess is provided facing the top surface of the substrate in which the solid-state imaging device is disposed, and a protrusion for positioning the solid-state imaging device is formed on the inside facing the recess of one substrate in the laminated substrate. , a solid-state image pickup device, wherein a conductive terminal is formed on the upper surface of the substrate 1 above around the recess, excluding the extended portion of the protrusion, and the thickness of the substrate 1 is formed to be thinner than the thickness of the solid-state image pickup device. Packaging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4782380U JPS62195Y2 (en) | 1980-04-08 | 1980-04-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4782380U JPS62195Y2 (en) | 1980-04-08 | 1980-04-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56149475U JPS56149475U (en) | 1981-11-10 |
| JPS62195Y2 true JPS62195Y2 (en) | 1987-01-07 |
Family
ID=29642820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4782380U Expired JPS62195Y2 (en) | 1980-04-08 | 1980-04-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62195Y2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2771807B2 (en) * | 1986-10-21 | 1998-07-02 | ソニー株式会社 | Solid-state imaging device |
| JPH073874B2 (en) * | 1987-07-22 | 1995-01-18 | 工業技術院長 | Semiconductor device |
| CN100397127C (en) * | 1998-08-05 | 2008-06-25 | 精工爱普生株式会社 | Optical module and method of manufacture thereof |
-
1980
- 1980-04-08 JP JP4782380U patent/JPS62195Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56149475U (en) | 1981-11-10 |
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