JPH10247701A - Semiconductor device and lead frame for manufacturing the same - Google Patents
Semiconductor device and lead frame for manufacturing the sameInfo
- Publication number
- JPH10247701A JPH10247701A JP9050677A JP5067797A JPH10247701A JP H10247701 A JPH10247701 A JP H10247701A JP 9050677 A JP9050677 A JP 9050677A JP 5067797 A JP5067797 A JP 5067797A JP H10247701 A JPH10247701 A JP H10247701A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- support plate
- wire connection
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置およびそ
の製造に用いるリードフレームに関し、特に支持板の主
面に固定された半導体チップの電極と、前記支持板を導
電性のワイヤで接続する構造の半導体装置の製造技術に
適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a lead frame used for manufacturing the same, and more particularly to a semiconductor device having a structure in which electrodes of a semiconductor chip fixed to a main surface of a support plate are connected to the support plate by conductive wires. The present invention relates to a technology effective when applied to a semiconductor device manufacturing technology.
【０００２】[0002]
【従来の技術】ＩＣ（集積回路装置）等の半導体装置に
おいて、半導体チップ等を封止する封止（パッケージ）
構造として樹脂（レジン）による封止構造が知られてい
る。2. Description of the Related Art In semiconductor devices such as ICs (integrated circuit devices), encapsulation (package) for encapsulating semiconductor chips and the like.
As a structure, a sealing structure using a resin (resin) is known.
【０００３】樹脂封止（レジンパッケージ）型半導体装
置は、リードフレームを使用して製造される。リードフ
レームは、薄い金属板をエッチングや精密プレスによっ
てパターニングすることによって形成される。[0003] A resin-sealed (resin package) type semiconductor device is manufactured using a lead frame. The lead frame is formed by patterning a thin metal plate by etching or precision press.
【０００４】リードフレームを使用して製造される半導
体装置は、その製造において、タブ等と呼称される支持
板の主面に接合材を介して半導体チップを固定するとと
もに、前記半導体チップの電極とリードを導電性のワイ
ヤで接続する。In the manufacture of a semiconductor device using a lead frame, a semiconductor chip is fixed to a main surface of a support plate called a tab or the like via a bonding material, and an electrode of the semiconductor chip is connected to the semiconductor device. Connect the leads with conductive wires.
【０００５】特開平5-144561号公報には、タブを支持す
るインナーリードと、半導体チップの電極をワイヤで接
続した半導体装置が開示されている。この文献には、半
導体ペレットをＡｕ膜,Ａｕ−Ｓｎ合金膜，Ｐｂ−Ｓｎ
合金膜等からなる接着層を用いてタブに固定することが
記載されている。[0005] Japanese Patent Application Laid-Open No. Hei 5-144561 discloses a semiconductor device in which inner leads for supporting tabs and electrodes of a semiconductor chip are connected by wires. In this document, semiconductor pellets are made of Au film, Au-Sn alloy film, Pb-Sn.
It is described that the sheet is fixed to a tab using an adhesive layer made of an alloy film or the like.
【０００６】[0006]
【発明が解決しようとする課題】ガリウム砒素（ＧａＡ
ｓ）基板を使用した半導体装置としてＭＥＳＦＥＴ（Me
tal Semiconductor Field Effect Transistor)が知られ
ている。SUMMARY OF THE INVENTION Gallium arsenide (GaAs)
s) As a semiconductor device using a substrate, MESFET (Me
tal Semiconductor Field Effect Transistor) is known.
【０００７】本出願人においては、ＧａＡｓ−ＭＥＳＦ
ＥＴチップ（半導体チップ）を支持板の主面にＡｕ−Ｓ
ｎ半田を介して固定するとともに、半導体チップのソー
ス電極に一端を接続するワイヤの他端を前記支持板の半
導体チップ固定領域から外れた領域面に固定する構造を
採用している。In the present applicant, GaAs-MESF
An ET chip (semiconductor chip) is Au-S on the main surface of the support plate.
In addition to the n-solder, a structure is employed in which the other end of the wire connecting one end to the source electrode of the semiconductor chip is fixed to the surface of the support plate outside the semiconductor chip fixing region.
【０００８】しかし、この構造では、接合材が半導体チ
ップ固定領域から外に流出し、ワイヤ接続領域面にまで
到達することがあり、半導体チップ固定後のワイヤボン
ディングにおいて、前記接合材上にワイヤが接続される
ため、ワイヤの接続強度が低下したり接続の信頼性が低
くなることが本発明者によってあきらかにされた。However, in this structure, the bonding material may flow out of the semiconductor chip fixing region and reach the surface of the wire connection region, and in the wire bonding after fixing the semiconductor chip, the wire is formed on the bonding material. It has been clarified by the present inventor that the connection reduces the connection strength of the wire and lowers the reliability of the connection.
【０００９】本発明の目的は、支持板に接続されるワイ
ヤの接続強度向上および接続の信頼性向上を図ることに
ある。An object of the present invention is to improve the connection strength of a wire connected to a support plate and to improve the reliability of connection.
【００１０】本発明の前記ならびにそのほかの目的と新
規な特徴は、本明細書の記述および添付図面からあきら
かになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。The following is a brief description of an outline of typical inventions disclosed in the present application.
【００１２】（１）支持板と、前記支持板の主面に接合
材を介して固定される半導体チップと、前記半導体チッ
プを被うように少なくとも前記支持板の主面側に設けら
れる封止体と、前記封止体の内外に亘って延在する複数
のリードと、前記封止体内で前記リードおよび前記支持
板と前記半導体チップの電極とを電気的に接続する導電
性のワイヤとを有する半導体装置であって、前記支持板
の半導体チップを固定する半導体チップ固定領域と、ワ
イヤを接続するワイヤ接続領域との間に前記接合材が流
出して前記ワイヤ接続領域に浸入するのを停止させる浸
入停止手段が設けられている。前記支持板の主面には部
分的に窪みが設けられ、前記窪み底面が前記半導体チッ
プ固定領域を構成する。これによって前記ワイヤ接続領
域面が前記半導体チップ固定領域面よりも高くなってい
る。前記支持板から突出し先端が前記封止体の外に突出
する支持リードが設けられている。前記封止体は前記支
持板の主面側を被っている。(1) A support plate, a semiconductor chip fixed to the main surface of the support plate via a bonding material, and a seal provided at least on the main surface side of the support plate so as to cover the semiconductor chip. A body, a plurality of leads extending over the inside and outside of the sealing body, and a conductive wire electrically connecting the lead and the support plate and the electrode of the semiconductor chip inside the sealing body. The bonding material flows out between a semiconductor chip fixing region for fixing a semiconductor chip of the support plate and a wire connection region for connecting a wire, and stops entering the wire connection region. There is provided an intrusion stop means for causing the intrusion. A depression is partially provided on the main surface of the support plate, and the bottom surface of the depression constitutes the semiconductor chip fixing region. Thereby, the surface of the wire connection region is higher than the surface of the semiconductor chip fixing region. A support lead is provided which protrudes from the support plate and has a tip protruding outside the sealing body. The sealing body covers the main surface side of the support plate.
【００１３】このような半導体装置の製造には、以下の
構造のリードフレームが使用される。支持板の主面に半
導体チップを固定する半導体チップ固定領域と、一つ以
上のワイヤを接続するワイヤ接続領域を有するリードフ
レームであって、前記半導体チップ固定領域とワイヤ接
続領域との間に前記接合材が流出して前記ワイヤ接続領
域に浸入するのを停止させる浸入停止手段が設けられて
いる。前記支持板の主面には部分的に窪みが設けられ、
前記窪み底面が前記半導体チップ固定領域を構成する。
これによって前記ワイヤ接続領域面が前記半導体チップ
固定領域面よりも高くなっている。For manufacturing such a semiconductor device, a lead frame having the following structure is used. A semiconductor chip fixing region for fixing a semiconductor chip to a main surface of a support plate, and a lead frame having a wire connection region for connecting one or more wires, wherein the semiconductor chip fixing region and the wire connection region are provided between the semiconductor chip fixing region and the wire connection region. There is provided an intrusion stop means for stopping the outflow of the bonding material into the wire connection area. A depression is provided partially on the main surface of the support plate,
The recess bottom forms the semiconductor chip fixing region.
Thereby, the surface of the wire connection region is higher than the surface of the semiconductor chip fixing region.
【００１４】（２）前記（１）の構成において、前記支
持板の主面には１以上の凸面が設けられ、前記凸面が前
記ワイヤ接続領域を構成している。すなわち、前記凸面
はワイヤ毎に対応して形成されている。(2) In the configuration of (1), one or more convex surfaces are provided on the main surface of the support plate, and the convex surfaces constitute the wire connection region. That is, the convex surface is formed corresponding to each wire.
【００１５】（３）前記（１）の構成において、前記半
導体チップ固定領域と前記ワイヤ接続領域との間の前記
支持板の主面には連続または不連続な凸条が設けられて
いる。(3) In the configuration of (1), a continuous or discontinuous ridge is provided on a main surface of the support plate between the semiconductor chip fixing region and the wire connection region.
【００１６】（４）前記（１）の構成において、前記半
導体チップ固定領域と前記ワイヤ接続領域との間の前記
支持板の主面には連続または不連続な溝が設けられてい
る。前記不連続な溝は支持板を貫通している。(4) In the configuration of (1), a continuous or discontinuous groove is provided on the main surface of the support plate between the semiconductor chip fixing region and the wire connection region. The discontinuous groove extends through the support plate.
【００１７】（５）前記（１）の構成において、前記半
導体チップが固定される支持板は相互に電気的に独立す
る複数の支持分断片によって構成され、かつ前記各支持
分断片に前記ワイヤが接続されている。(5) In the configuration of the above (1), the support plate to which the semiconductor chip is fixed is constituted by a plurality of support segments which are electrically independent from each other, and the wire is attached to each of the support segments. It is connected.
【００１８】前記（１）の手段によれば、半導体装置の
製造に用いるリードフレームにおいて、支持板には半導
体チップを固定する半導体チップ固定領域と、ワイヤを
接続するワイヤ接続領域との間に前記接合材が流出して
前記ワイヤ接続領域に浸入するのを停止させる浸入停止
手段が設けられていることから、半導体チップの固定
時、接合材が半導体チップ固定領域から外に向かって流
出しても、前記浸入停止手段によって遮られてワイヤ接
続領域に到達しないため、その後にワイヤ接続領域にワ
イヤを接続した場合、接合材上にワイヤが接続されるこ
となく直接支持板に接続される。したがって、ワイヤの
接続強度向上が図れるとともに、ワイヤの接続の信頼性
の向上が図れる。According to the means of (1), in the lead frame used for manufacturing the semiconductor device, the support plate is provided between the semiconductor chip fixing region for fixing the semiconductor chip and the wire connection region for connecting the wires. Since the intrusion stopping means for stopping the outflow of the bonding material and intrusion into the wire connection region is provided, even when the bonding material flows out of the semiconductor chip fixing region when the semiconductor chip is fixed, Since the wire does not reach the wire connection area because of being blocked by the intrusion stop means, when a wire is subsequently connected to the wire connection area, the wire is directly connected to the support plate without being connected to the bonding material. Therefore, the connection strength of the wire can be improved, and the reliability of the connection of the wire can be improved.
【００１９】前記（２）の手段によれば、前記ワイヤ接
続領域は各ワイヤに対応する凸面によってそれぞれ形成
されていることから、前記凸面よりも低い半導体チップ
固定領域面から流出してきた接合材は前記凸面上に到達
することがなく、凸面の側部を流れるため、前記手段
（１）の場合と同様に直接凸面にワイヤ接続が行え、ワ
イヤの接続強度向上が図れるとともに、ワイヤ接続の信
頼性の向上が図れる。According to the means (2), since the wire connection regions are formed by the convex surfaces corresponding to the respective wires, the bonding material flowing out from the semiconductor chip fixing region surface lower than the convex surface is reduced. Since the wire does not reach the convex surface and flows on the side of the convex surface, the wire can be directly connected to the convex surface as in the case of the means (1), thereby improving the connection strength of the wire and improving the reliability of the wire connection. Can be improved.
【００２０】前記（３）の手段によれば、前記半導体チ
ップ固定領域と前記ワイヤ接続領域との間の前記支持板
の主面には、前記半導体チップ固定領域面から流出して
きた接合材の流出を阻止する連続または不連続な凸条が
設けられているため、ワイヤ接続領域面に接合材が付着
しない。したがって、前記手段（１）の場合と同様に直
接凸面にワイヤ接続が行え、ワイヤの接続強度向上が図
れるとともに、ワイヤ接続の信頼性の向上が図れる。According to the above-mentioned means (3), the outflow of the bonding material flowing out from the semiconductor chip fixing area surface is provided on the main surface of the support plate between the semiconductor chip fixing area and the wire connection area. Since the continuous or discontinuous ridges are provided to prevent the bonding, the bonding material does not adhere to the surface of the wire connection region. Therefore, as in the case of the above-mentioned means (1), wire connection can be directly performed on the convex surface, and the connection strength of the wire can be improved, and the reliability of the wire connection can be improved.
【００２１】前記（４）の手段によれば、前記半導体チ
ップ固定領域と前記ワイヤ接続領域との間の前記支持板
の主面には、前記半導体チップ固定領域面から流出して
きた接合材を溜めてその流れを停止させる連続または不
連続な溝が設けられているため、ワイヤ接続領域面に接
合材が付着しない。したがって、前記手段（１）の場合
と同様に直接凸面にワイヤ接続が行え、ワイヤの接続強
度向上が図れるとともに、ワイヤ接続の信頼性の向上が
図れる。According to the means (4), the bonding material flowing out from the semiconductor chip fixing area surface is stored on the main surface of the support plate between the semiconductor chip fixing area and the wire connection area. Since the continuous or discontinuous groove for stopping the flow is provided, the bonding material does not adhere to the surface of the wire connection area. Therefore, as in the case of the above-mentioned means (1), wire connection can be directly performed on the convex surface, and the connection strength of the wire can be improved, and the reliability of the wire connection can be improved.
【００２２】前記（５）の手段によれば、前記手段
（１）による効果に加えて、前記支持板は相互に電気的
に独立する複数の支持分断片によって構成されているこ
とから、複数箇所にグランドや電源電位を配置する半導
体チップを含む半導体装置の製造にも適する。According to the means (5), in addition to the effect of the means (1), since the support plate is constituted by a plurality of support segments which are electrically independent from each other, It is also suitable for manufacturing a semiconductor device including a semiconductor chip in which a ground and a power supply potential are arranged.
【００２３】[0023]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。なお、発明の実施の形態を
説明するための全図において、同一機能を有するものは
同一符号を付け、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
【００２４】（実施形態１）図１乃至図５は本発明の一
実施形態（実施形態１）である半導体装置およびその製
造方法を示す図であり、図１は一部を除去した半導体装
置の斜視図、図２は半導体装置の断面図、図３は半導体
装置の製造に使用するリードフレームの平面図、図４は
リードフレームの支持板部分を示す斜視図、図５は半導
体チップを固定し、ワイヤボンディングを行ったリード
フレームを示す平面図である。(Embodiment 1) FIGS. 1 to 5 are views showing a semiconductor device according to an embodiment (Embodiment 1) of the present invention and a method of manufacturing the same. FIG. FIG. 2 is a cross-sectional view of the semiconductor device, FIG. 3 is a plan view of a lead frame used for manufacturing the semiconductor device, FIG. 4 is a perspective view showing a support plate portion of the lead frame, and FIG. FIG. 3 is a plan view showing a lead frame on which wire bonding has been performed.
【００２５】本実施形態１では、ＧａＡｓ−ＭＥＳＦＥ
Ｔに本発明を適用した例について説明する。本実施形態
１の半導体装置１は、図１および図２に示すように、外
観的には偏平な樹脂（レジン）からなる封止体（パッケ
ージ）２と、このパッケージ２の周面、４辺から突出す
るリード３とからなっている。パッケージ２の左側に突
出するリード３はドレイン（Ｄ）リード、パッケージ２
の右側に突出するリード３はゲート（Ｇ）リード、パッ
ケージ２の前面及び背面に突出するリード３はソース
（Ｓ）リードである。In the first embodiment, the GaAs-MESFE
An example in which the present invention is applied to T will be described. As shown in FIGS. 1 and 2, a semiconductor device 1 according to the first embodiment includes a sealing body (package) 2 made of a resin (resin) that is flat in appearance, and a peripheral surface and four sides of the package 2. And a lead 3 protruding therefrom. Lead 3 projecting to the left side of package 2 is a drain (D) lead, package 2
Are the gate (G) leads, and the leads 3 projecting from the front and back surfaces of the package 2 are the source (S) leads.
【００２６】前記パッケージ２の内部には支持板４が位
置している。この支持板４はタブとも称され、一対の対
面する２辺の中央部分をそれぞれ支持リード（タブ吊り
リード）に支持されている。本実施形態１では、支持リ
ードは前記パッケージ２の外に突出してソースリードを
構成している。A support plate 4 is located inside the package 2. The support plate 4 is also referred to as a tab, and the central portions of a pair of facing two sides are supported by support leads (tab suspension leads). In the first embodiment, the support leads protrude out of the package 2 to form source leads.
【００２７】前記支持板４は、その主面（上面）に部分
的に窪み１０が設けられている。この窪み１０の底面に
は、図２にも示すように半導体チップ６が接合材５を介
して固定されている。前記接合材５は、たとえばＡｕ−
Ｓｎ半田となっている。前記窪み１０の底面の広さは、
図１の二点鎖線で示すように、半導体チップ６を固定す
る半導体チップ固定領域１１よりも広くなっている。The support plate 4 is partially provided with a depression 10 on its main surface (upper surface). A semiconductor chip 6 is fixed to the bottom surface of the recess 10 via a bonding material 5 as shown in FIG. The bonding material 5 is, for example, Au-
It is Sn solder. The width of the bottom surface of the depression 10 is
As shown by the two-dot chain line in FIG. 1, the area is wider than the semiconductor chip fixing area 11 for fixing the semiconductor chip 6.
【００２８】また、前記窪み１０は前記ドレインリード
側に片寄って形成されている。前記窪み１０の縁となる
ゲートリード寄りの支持板４の主面部分は幅が広くな
り、ワイヤ接続部１２を構成している。また、ワイヤ接
続部１２の一部は二点鎖線で示すようにワイヤ接続領域
１３を形成する。The recess 10 is formed so as to be offset toward the drain lead. The main surface portion of the support plate 4 near the gate lead, which is the edge of the recess 10, has a large width and forms a wire connection portion 12. Further, a part of the wire connection portion 12 forms a wire connection region 13 as shown by a two-dot chain line.
【００２９】したがって、前記ワイヤ接続領域１３の面
は、前記半導体チップ固定領域１１の面よりも高くな
り、半導体チップ６を支持板４に固定する接合材５がワ
イヤ接続領域１３の面にはい上がることはない（図２参
照）。Therefore, the surface of the wire connection region 13 is higher than the surface of the semiconductor chip fixing region 11, and the bonding material 5 for fixing the semiconductor chip 6 to the support plate 4 rises to the surface of the wire connection region 13. (See FIG. 2).
【００３０】一方、前記ドレインリードおよびゲートリ
ードの先端部分は、前記支持板４の辺に沿うように幅が
広くなり、ワイヤ接続部７を形成している。On the other hand, the tip portions of the drain lead and the gate lead are widened along the sides of the support plate 4 to form the wire connection portions 7.
【００３１】また、半導体チップ６の上面の図示しない
電極と、前記パッケージ２内に延在するリード３の先端
および前記ワイヤ接続部１２は、導電性のワイヤ１４に
よって電気的に接続されている。An electrode (not shown) on the upper surface of the semiconductor chip 6 is electrically connected to a tip end of the lead 3 extending into the package 2 and the wire connection portion 12 by a conductive wire 14.
【００３２】つぎに、本実施形態１の半導体装置の製造
方法について説明する。半導体装置１の製造において
は、図３に示すようなリードフレーム１５が用意され
る。Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. In manufacturing the semiconductor device 1, a lead frame 15 as shown in FIG. 3 is prepared.
【００３３】リードフレーム１５は、０．４ｍｍ程度の
厚さの鉄−ニッケル系合金板，銅板，銅合金板等をエッ
チングまたは精密プレスによってパターニングすること
によって形成される。リードフレーム１５は、平行に延
在する一対の外枠１６と、前記一対の外枠１６に直交し
かつ前記一対の外枠１６を一定間隔位置で連結する内枠
１７とからなっている。The lead frame 15 is formed by etching or patterning an iron-nickel alloy plate, copper plate, copper alloy plate or the like having a thickness of about 0.4 mm by etching or precision press. The lead frame 15 includes a pair of outer frames 16 extending in parallel, and an inner frame 17 orthogonal to the pair of outer frames 16 and connecting the pair of outer frames 16 at fixed intervals.
【００３４】また、前記一対の外枠１６と隣接する２本
の内枠１７とによって形成される枠の中央には、矩形の
支持板（タブ）４が位置している。この支持板４は、前
記外枠１６の略中間部分から延在する支持リード（タブ
リード）２０に支持されている。前記支持板４の主面に
は、図４に示すように、前述のように左側に片寄って窪
み１０が設けられている。この窪み１０は、半導体チッ
プ６を固定する半導体チップ固定領域１１よりも大きく
なっている。前記窪み１０の右寄りの主面部分はワイヤ
を接続するためのワイヤ接続部１２を形成している。こ
のワイヤ接続部１２には、二点鎖線で示すようにワイヤ
接続領域１３が位置するようになっている。前記支持リ
ード２０は、ソースリードとなる。A rectangular support plate (tab) 4 is located at the center of the frame formed by the pair of outer frames 16 and two adjacent inner frames 17. The support plate 4 is supported by support leads (tab leads) 20 extending from a substantially intermediate portion of the outer frame 16. As shown in FIG. 4, the main surface of the support plate 4 is provided with a recess 10 which is offset to the left as described above. The recess 10 is larger than the semiconductor chip fixing area 11 for fixing the semiconductor chip 6. The right main surface portion of the recess 10 forms a wire connection portion 12 for connecting a wire. The wire connection area 13 is located at the wire connection portion 12 as shown by a two-dot chain line. The support lead 20 becomes a source lead.
【００３５】前記窪み１０は、コイニングによって形成
され、たとえば、０．０２ｍｍの深さに形成される。The depression 10 is formed by coining, for example, to a depth of 0.02 mm.
【００３６】前記窪み１０、厳密には窪みの縁は、窪み
底の半導体チップ固定領域１１から接合材５がワイヤ接
続領域１３に流出するのを停止させる浸入停止手段を構
成する。The recess 10, more precisely, the edge of the recess, constitutes an intrusion stopping means for stopping the flow of the bonding material 5 from the semiconductor chip fixing region 11 at the bottom of the recess to the wire connection region 13.
【００３７】また、前記内枠１７の内側中央部分からそ
れぞれリード３が延在している。このリード３の先端は
前記支持板４の周辺に近接するとともに、幅広となり、
ワイヤを接続するためのワイヤ接続部７を形成してい
る。The leads 3 extend from the inner central portion of the inner frame 17, respectively. The leading end of the lead 3 approaches the periphery of the support plate 4 and becomes wider,
A wire connecting portion 7 for connecting a wire is formed.
【００３８】リードフレーム１５の外枠１６には、ガイ
ド孔２８ａ，２８ｂが設けられている。このガイド孔２
８，２９は、リードフレーム１５の移送や位置決め等の
ガイドとして利用される。なお、前記リードフレーム１
５は必要に応じて所望個所にメッキが施される。The outer frame 16 of the lead frame 15 is provided with guide holes 28a and 28b. This guide hole 2
Reference numerals 8 and 29 are used as guides for transferring and positioning the lead frame 15. The lead frame 1
5 is plated at a desired place as needed.
【００３９】つぎに、図５に示すように、前記リードフ
レーム１５の支持板４の窪み１０底上に接合材５を介し
て半導体チップ６を固定する。たとえば、支持板４の窪
み１０底に接合材５として、０．０２ｍｍ程度の厚さの
Ａｕ−Ｓｎ半田からなる箔を取り付けるとともに、Ａｕ
−Ｓｎ半田箔上に半導体チップ６を載置し、前記Ａｕ−
Ｓｎ半田を一時的に溶かして半導体チップ６を支持板４
に固定する。Ａｕ−Ｓｎ半田箔の厚さは、０．０２ｍｍ
であることから、前記窪み１０の深さを０．０２ｍｍ程
度としておけば、溶けたＡｕ−Ｓｎ半田が窪み１０の縁
をはい上がってワイヤ接続部１２の表面に浸入すること
はない。Next, as shown in FIG. 5, the semiconductor chip 6 is fixed on the bottom of the recess 10 of the support plate 4 of the lead frame 15 via the bonding material 5. For example, a foil made of Au-Sn solder having a thickness of about 0.02 mm is attached to the bottom of the depression 10 of the support
-The semiconductor chip 6 is placed on the Sn solder foil, and the Au-
The semiconductor chip 6 is temporarily melted by the Sn solder to support the semiconductor chip 6.
Fixed to The thickness of the Au-Sn solder foil is 0.02 mm
Therefore, if the depth of the dent 10 is set to about 0.02 mm, the melted Au-Sn solder does not go up the edge of the dent 10 and enter the surface of the wire connection portion 12.
【００４０】半導体チップ６は、たとえば、ＧａＡｓ−
ＭＥＳＦＥＴからなり、図示しないが、ソース電極，ド
レイン電極，ゲート電極の各ワイヤボンディング用の電
極（パッド）は、ドレイン電極，ゲート電極がそれぞれ
３個、ソース電極が２個となっている。ドレイン電極の
パッド列とゲート電極のパッド列は平行になる。また、
ソース電極のパッドはゲート電極のバッド間にそれぞれ
位置している。The semiconductor chip 6 is made of, for example, GaAs-
Although not shown, each electrode (pad) for wire bonding of a source electrode, a drain electrode, and a gate electrode has three drain electrodes and three gate electrodes, and two source electrodes (not shown). The pad row of the drain electrode and the pad row of the gate electrode are parallel. Also,
The source electrode pads are located between the gate electrode pads.
【００４１】つぎに、図５に示すように、半導体チップ
６の図示しない電極と、リード３の先端のワイヤ接続部
７および支持板４のワイヤ接続部１２を導電性のワイヤ
１４で接続する。１例として、図５に示すように、ドレ
インリードおよびゲートリードは、それぞれ３本のワイ
ヤ１４が接続され、ソースリードに繋がる支持板４には
２本のワイヤ１４が接続される。Next, as shown in FIG. 5, the electrodes (not shown) of the semiconductor chip 6 are connected to the wire connection portions 7 at the tips of the leads 3 and the wire connection portions 12 of the support plate 4 with conductive wires 14. As an example, as shown in FIG. 5, three wires 14 are connected to the drain lead and the gate lead, respectively, and two wires 14 are connected to the support plate 4 connected to the source lead.
【００４２】つぎに、図５の二点鎖線で示すように、ト
ランスファモールドによってパッケージ２が支持板４の
主面側を被うように形成される。したがって、支持板
４，リード３，支持リード２０の下面はパッケージ２か
ら露出するようになる。Next, as shown by a two-dot chain line in FIG. 5, the package 2 is formed so as to cover the main surface of the support plate 4 by transfer molding. Therefore, the lower surfaces of the support plate 4, the lead 3, and the support lead 20 are exposed from the package 2.
【００４３】ついで、不要リードフレーム部分は切断除
去される。すなわち、リード３および支持リード２０は
パッケージ２から所望距離隔てた位置で切断除去され、
図１および図２に示す半導体装置１が製造される。Next, the unnecessary lead frame portion is cut and removed. That is, the lead 3 and the support lead 20 are cut and removed at a desired distance from the package 2,
The semiconductor device 1 shown in FIGS. 1 and 2 is manufactured.
【００４４】本実施形態１の半導体装置１は、窪み１０
からなる浸入停止手段によって、支持板４の主面の半導
体チップ固定領域１１からワイヤ接続領域１３への接合
材５の流出を停止させることができるため、前記ワイヤ
接続領域１３に接続されたワイヤ１４の接続面に接合材
５が介在しなくなり、ワイヤの接続強度が向上する。ま
た、ワイヤの接続部分に接合材が介在しないことから、
ワイヤの剥離も起き難くなり信頼性が向上する。The semiconductor device 1 of the first embodiment has a recess 10
Can be stopped from flowing out of the bonding material 5 from the semiconductor chip fixing area 11 on the main surface of the support plate 4 to the wire connection area 13 by the intrusion stop means composed of the wire 14 connected to the wire connection area 13 The bonding material 5 does not intervene in the connection surface of the wire, and the connection strength of the wire improves. Also, since there is no bonding material at the wire connection,
The peeling of the wire hardly occurs, and the reliability is improved.
【００４５】本実施形態１のリードフレームは、半導体
チップ６を固定する支持板４の主面に窪み１０を設け、
半導体チップ固定領域１１とワイヤ接続領域１３との間
に、接合材５が半導体チップ固定領域１１からワイヤ接
続領域１３に流出しないように段差が設けられている。
したがって、このリードフレームを使用して半導体装置
を製造した場合、前記半導体チップ固定領域１１に接合
材５を介して半導体チップ６を固定した場合、溶けた接
合材５がワイヤ接続領域１３面に流出しなくなり、ワイ
ヤ接続領域１３に接続するワイヤ１４の接続強度が向上
する。この結果、製造された半導体装置の信頼性も高く
なる。In the lead frame of the first embodiment, a depression 10 is provided on the main surface of the support plate 4 for fixing the semiconductor chip 6,
A step is provided between the semiconductor chip fixing region 11 and the wire connection region 13 so that the bonding material 5 does not flow from the semiconductor chip fixing region 11 to the wire connection region 13.
Therefore, when a semiconductor device is manufactured using this lead frame, and when the semiconductor chip 6 is fixed to the semiconductor chip fixing region 11 via the bonding material 5, the melted bonding material 5 flows out to the surface of the wire connection region 13. The connection strength of the wire 14 connected to the wire connection region 13 is improved. As a result, the reliability of the manufactured semiconductor device is improved.
【００４６】なお、半導体チップ６の両側の支持板４部
分にワイヤ１４を接続する場合は、前記窪み１０を支持
板４の中央に設け、窪み１０の両側の縁部分をワイヤ接
続部１２とすればよい。When the wires 14 are connected to the support plate 4 on both sides of the semiconductor chip 6, the recess 10 is provided at the center of the support plate 4, and the edge portions on both sides of the recess 10 are connected to the wire connection portions 12. I just need.
【００４７】（実施形態２）図６は本発明の他の実施形
態（実施形態２）のリードフレームの支持板部分を示す
斜視図である。本実施形態２では、浸入停止手段として
段差２４を支持板４に設けるものである。すなわち、コ
イニングによって段差２４を設け、支持板４の主面を高
い面２５と低い面２６とし、前記低い面２６に半導体チ
ップ固定領域１１を設け、前記高い面２５にワイヤ接続
領域１３を設ける構成になっている。前記段差２４は、
半導体チップ固定領域１１に半導体チップ６を接合材５
によって固定する際、溶けた接合材５が乗り越えない高
さが必要である。たとえば、接合材５として厚さ０．０
２ｍｍのＡｕ−Ｓｎ半田箔を使用する場合には、前記段
差２４は０．０２ｍｍ程度の高さとすれば、接合材５の
ワイヤ接続領域１３面への浸入を防止することができ
る。(Embodiment 2) FIG. 6 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 2) of the present invention. In the second embodiment, a step 24 is provided on the support plate 4 as an intrusion stop unit. That is, the step 24 is provided by coining, the main surface of the support plate 4 is made into a high surface 25 and a low surface 26, the semiconductor chip fixing region 11 is provided on the low surface 26, and the wire connection region 13 is provided on the high surface 25. It has become. The step 24 is
The semiconductor chip 6 is bonded to the semiconductor chip fixing region 11 with the bonding material 5.
When fixing by the method, a height that the melted joining material 5 cannot climb over is required. For example, as the joining material 5, a thickness of 0.0
When a 2 mm Au-Sn solder foil is used, if the step 24 has a height of about 0.02 mm, it is possible to prevent the bonding material 5 from entering the surface of the wire connection region 13.
【００４８】この結果、ワイヤ接続領域１３の面は、前
記半導体チップ固定領域１１の面よりも高くなっている
ことから、半導体チップ固定領域１１に接合材５によっ
て半導体チップ６を固定した場合、接合材５がワイヤ接
続領域１３に流出しなくなり、ワイヤ接続領域１３に確
実にワイヤ１４を接続することができる。As a result, since the surface of the wire connection region 13 is higher than the surface of the semiconductor chip fixing region 11, when the semiconductor chip 6 is fixed to the semiconductor chip fixing region 11 by the bonding material 5, The material 5 does not flow out to the wire connection region 13, and the wire 14 can be securely connected to the wire connection region 13.
【００４９】なお、ワイヤ接続部１２を支持板４の両側
に設けてもよい。The wire connection portions 12 may be provided on both sides of the support plate 4.
【００５０】（実施形態３）図７は本発明の他の実施形
態（実施形態３）のリードフレームの支持板部分を示す
斜視図である。本実施形態３では、浸入停止手段は、前
記実施形態１・２と同様に、ワイヤ接続領域１３面を半
導体チップ固定領域１１面よりも高くする構成である
が、各ワイヤ接続領域１３を各凸面２７にそれぞれ１つ
設ける構成になっている。この凸面２７もコイニングに
よって形成できる。(Embodiment 3) FIG. 7 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 3) of the present invention. In the third embodiment, the intrusion stopping means is configured such that the surface of the wire connection region 13 is higher than the surface of the semiconductor chip fixing region 11 as in the first and second embodiments. 27 is provided. The convex surface 27 can also be formed by coining.
【００５１】本実施形態３では、各ワイヤ接続領域１３
の面は凸面２７に設けられ、前記半導体チップ固定領域
１１の面よりも高くなっていることから、半導体チップ
固定領域１１に接合材５によって半導体チップ６を固定
した場合、接合材５がワイヤ接続領域１３に流出しなく
なり、ワイヤ接続領域１３に確実にワイヤ１４を接続す
ることができる。本実施形態３では、ワイヤ接続領域１
３に向かって流出する接合材５は、凸面２７の両側の低
い面上を流れすぎることになり、接合材５が盛り上がっ
て凸面２７上にはい上がるのを確実に防止できる。In the third embodiment, each wire connection region 13
Is provided on the convex surface 27 and is higher than the surface of the semiconductor chip fixing region 11, so that when the semiconductor chip 6 is fixed to the semiconductor chip fixing region 11 by the bonding material 5, the bonding material 5 It does not flow out to the region 13 and the wire 14 can be reliably connected to the wire connection region 13. In the third embodiment, the wire connection region 1
The bonding material 5 flowing out toward 3 will flow too much on the low surface on both sides of the convex surface 27, and it is possible to reliably prevent the bonding material 5 from rising and rising onto the convex surface 27.
【００５２】なお、凸面２７を支持板４の両側に設けて
もよい。The convex surfaces 27 may be provided on both sides of the support plate 4.
【００５３】（実施形態４）図８は本発明の他の実施形
態（実施形態４）のリードフレームの支持板部分を示す
斜視図である。本実施形態４は浸入停止手段として、支
持板４の主面に突条３０を設けた例である。本実施形態
４では、半導体チップ固定領域１１の面と、ワイヤ接続
領域１３の面は同一高さとなるが、半導体チップ固定領
域１１とワイヤ接続領域１３との間には１本の突条３０
（連続な突条）を設けた構成になっている。この突条３
０もコイニングによって形成できる。前記突条３０は、
半導体チップ固定領域１１に半導体チップ６を接合材５
によって固定する際、溶けた接合材５が乗り越えない高
さが必要である。たとえば、接合材５として厚さ０．０
２ｍｍのＡｕ−Ｓｎ半田箔を使用する場合には、前記突
条３０は０．０２ｍｍ程度の高さとすれば、接合材５の
ワイヤ接続領域１３面への浸入を防止することができ
る。(Embodiment 4) FIG. 8 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 4) of the present invention. The fourth embodiment is an example in which a ridge 30 is provided on the main surface of the support plate 4 as an intrusion stop unit. In the fourth embodiment, the surface of the semiconductor chip fixing region 11 and the surface of the wire connection region 13 have the same height, but one ridge 30 is provided between the semiconductor chip fixing region 11 and the wire connection region 13.
(Continuous ridges) are provided. This ridge 3
0 can also be formed by coining. The ridge 30
The semiconductor chip 6 is bonded to the semiconductor chip fixing region 11 with the bonding material 5.
When fixing by the method, a height that the melted joining material 5 cannot climb over is required. For example, as the joining material 5, a thickness of 0.0
When a 2 mm Au-Sn solder foil is used, if the protrusions 30 have a height of about 0.02 mm, it is possible to prevent the bonding material 5 from entering the surface of the wire connection region 13.
【００５４】したがって、ワイヤ接続領域１３は接合材
５によって汚染されなくなり、ワイヤ接続領域１３に接
続されるワイヤ１４の接続強度が向上するとともに、ワ
イヤの接続の信頼性が高くなる。Therefore, the wire connection region 13 is not contaminated by the bonding material 5, the connection strength of the wire 14 connected to the wire connection region 13 is improved, and the reliability of the wire connection is increased.
【００５５】なお、突条３０を支持板４の両側に設け、
支持板４の両側にそれぞれワイヤ接続領域１３を設ける
ようにしてもよい。The ridges 30 are provided on both sides of the support plate 4,
The wire connection regions 13 may be provided on both sides of the support plate 4.
【００５６】また、前記突条３０を、断続的（不連続）
に設けてもよい。この場合、不連続な突条３０は、各ワ
イヤ接続領域１３の一辺に沿って設け、各突条３０によ
って対応するワイヤ接続領域１３への接合材５の流出を
停止させる。Further, the ridges 30 may be intermittent (discontinuous).
May be provided. In this case, the discontinuous protrusions 30 are provided along one side of each wire connection region 13, and each protrusion 30 stops the flow of the bonding material 5 to the corresponding wire connection region 13.
【００５７】また、半導体チップ固定領域１１とワイヤ
接続領域１３とを突条３０で区分けして接合材５のワイ
ヤ接続領域１３への流出を防止するために、前記突条３
０で半導体チップ固定領域１１を囲むようにしてもよ
い。The semiconductor chip fixing region 11 and the wire connection region 13 are separated by a ridge 30 to prevent the joining material 5 from flowing out to the wire connection region 13.
0 may surround the semiconductor chip fixing region 11.
【００５８】（実施形態５）図９は本発明の他の実施形
態（実施形態５）のリードフレームの支持板部分を示す
斜視図である。本実施形態５では、平坦な支持板４の主
面に浸入停止手段として連続な溝３５を形成したもので
あり、半導体チップ固定領域１１から流出してきた接合
材５を前記溝３５内に落とし込み、ワイヤ接続領域１３
への流れを停止させる構成である。(Embodiment 5) FIG. 9 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 5) of the present invention. In the fifth embodiment, a continuous groove 35 is formed on the main surface of the flat support plate 4 as an intrusion stopping means, and the bonding material 5 flowing out of the semiconductor chip fixing region 11 is dropped into the groove 35, Wire connection area 13
To stop the flow to
【００５９】図９の場合は、支持板４の主面の半導体チ
ップ固定領域１１とワイヤ接続領域１３との間に１本の
溝３５（連続溝）を配置した構成になっている。前記溝
３５の容量は半導体チップ固定領域１１から流出してき
た接合材５を溜め込み、ワイヤ接続領域１３側への流出
が起きない程度とする。これによって、半導体チップ固
定領域１１に半導体チップ６を接合材５を介して固定し
た場合、ワイヤ接続領域１３は接合材５によって汚染さ
れないため、ワイヤ接続領域１３に接続されたワイヤ１
４は支持板４に確実に固定される。この結果、ワイヤの
接続強度向上が図れるとともに、ワイヤ接続の信頼性の
向上が図れる。In the case of FIG. 9, one groove 35 (continuous groove) is arranged between the semiconductor chip fixing region 11 and the wire connection region 13 on the main surface of the support plate 4. The capacity of the groove 35 is such that the bonding material 5 flowing out of the semiconductor chip fixing region 11 is stored and does not flow out to the wire connection region 13 side. Thus, when the semiconductor chip 6 is fixed to the semiconductor chip fixing region 11 via the bonding material 5, the wire connection region 13 is not contaminated by the bonding material 5.
4 is securely fixed to the support plate 4. As a result, the connection strength of the wire can be improved, and the reliability of the wire connection can be improved.
【００６０】（実施形態６）図１０は本発明の他の実施
形態（実施形態６）のリードフレームの支持板部分を示
す斜視図である。本実施形態５では、平坦な支持板４の
主面に浸入停止手段として不連続な溝３６を形成したも
のであり、前記実施形態５と同様に、半導体チップ固定
領域１１から流出してきた接合材５を前記不連続な溝３
６内に落とし込み、ワイヤ接続領域１３への流れを停止
させる構成である。(Embodiment 6) FIG. 10 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 6) of the present invention. In the fifth embodiment, a discontinuous groove 36 is formed on the main surface of the flat support plate 4 as an intrusion stop means, and the bonding material flowing out of the semiconductor chip fixing region 11 is similar to the fifth embodiment. 5 is the discontinuous groove 3
6 to stop the flow to the wire connection area 13.
【００６１】図１０の場合は、支持板４の主面の半導体
チップ固定領域１１とワイヤ接続領域１３との間に不連
続な溝３６を配置した構成になっている。本実施形態６
の場合は、ワイヤ接続部１２に接合材５が進出しても、
ワイヤ接続領域１３が接合材５で汚染されなければよい
という思想であり、半導体チップ固定領域１１からワイ
ヤ接続領域１３に流出する接合材５部分を前記不連続な
溝３６内に落とし込ませ、ワイヤ接続領域１３を接合材
５で汚染させなくする。In the case of FIG. 10, a discontinuous groove 36 is arranged between the semiconductor chip fixing region 11 and the wire connection region 13 on the main surface of the support plate 4. Embodiment 6
In the case of, even if the bonding material 5 advances to the wire connection portion 12,
The idea is that the wire connection region 13 should not be contaminated with the bonding material 5. The bonding material 5 that flows out of the semiconductor chip fixing region 11 to the wire connection region 13 is dropped into the discontinuous groove 36, and the wire The connection region 13 is prevented from being contaminated with the bonding material 5.
【００６２】これによって、半導体チップ固定領域１１
に半導体チップ６を接合材５を介して固定した場合、ワ
イヤ接続領域１３は接合材５によって汚染されないた
め、ワイヤ接続領域１３に接続されたワイヤ１４は支持
板４に確実に固定される。この結果、ワイヤの接続強度
向上が図れるとともに、ワイヤ接続の信頼性の向上が図
れる。Thus, the semiconductor chip fixing region 11
When the semiconductor chip 6 is fixed via the bonding material 5, the wire connection region 13 is not contaminated by the bonding material 5, so that the wires 14 connected to the wire connection region 13 are securely fixed to the support plate 4. As a result, the connection strength of the wire can be improved, and the reliability of the wire connection can be improved.
【００６３】なお、不連続な溝３６を支持板４に設ける
場合、前記不連続な溝３６を貫通穴としてもよい。この
場合、パッケージ２を形成するレジンが深い不連続な溝
３６に入り込むことから、パッケージ２と支持板４との
密着性が高くなり、耐湿性が向上する。When the discontinuous groove 36 is provided on the support plate 4, the discontinuous groove 36 may be a through hole. In this case, since the resin forming the package 2 enters the deep discontinuous groove 36, the adhesion between the package 2 and the support plate 4 is increased, and the moisture resistance is improved.
【００６４】（実施形態７）図１１は本発明の他の実施
形態（実施形態７）である半導体装置を示す一部を除去
した平面図、図１２は本実施形態７の半導体装置を示す
断面図である。(Embodiment 7) FIG. 11 is a plan view of a semiconductor device according to another embodiment (Embodiment 7) of the present invention, with a part thereof removed, and FIG. 12 is a cross section showing the semiconductor device of Embodiment 7 of the present invention. FIG.
【００６５】本実施形態７はガルウィング型のＱＦＰ
（Quad Flat Package)構造の半導体装置に本発明を適用
した例である。すなわち、本実施形態７の半導体装置１
は、パッケージ２の４辺からそれぞれリード３を突出さ
せた構造となっている。そして、特徴的なことは、半導
体チップ６を支持する支持板４が分割構造となっている
ことである。すなわち、前記支持板４は、相互に電気的
に独立する複数の支持分断片４０によって構成されてい
る。各支持分断片４０は支持リード２０によって支持さ
れている。また、前記支持分断片４０には半導体チップ
固定領域１１とワイヤ接続領域１３との間に、浸入停止
手段が設けられている。The seventh embodiment is a gull-wing type QFP.
This is an example in which the present invention is applied to a semiconductor device having a (Quad Flat Package) structure. That is, the semiconductor device 1 of the seventh embodiment
Has a structure in which the leads 3 protrude from the four sides of the package 2, respectively. What is characteristic is that the support plate 4 that supports the semiconductor chip 6 has a divided structure. That is, the support plate 4 is constituted by a plurality of support segments 40 which are electrically independent from each other. Each support segment 40 is supported by a support lead 20. Further, the support segment 40 is provided with an intrusion stopping means between the semiconductor chip fixing region 11 and the wire connection region 13.
【００６６】本実施形態７の場合は、浸入停止手段は図
１２に示すように、前記実施形態２と同様に高い面２５
と低い面２６とによる段差２４で構成され、低い面２６
に接合材５を介して半導体チップ６を固定する際の接合
材５のワイヤ接続領域１３への流出を停止させるように
なっている。In the case of the seventh embodiment, as shown in FIG.
And the lower surface 26, the lower surface 26.
When the semiconductor chip 6 is fixed via the bonding material 5, the outflow of the bonding material 5 to the wire connection region 13 is stopped.
【００６７】本実施形態７の場合、図１２に示すよう
に、接合材５は絶縁性のものを使用しているが、半導体
チップ６の裏面が電気的に独立し、表層部分の各回路部
分と絶縁的であるならば、前記各実施形態の場合と同様
にＡｕ−Ｓｎ半田等の導電性接合材を使用してもよい。In the case of the seventh embodiment, as shown in FIG. 12, the bonding material 5 is made of an insulating material. However, the back surface of the semiconductor chip 6 is electrically independent, and each of the circuit portions on the surface layer is separated. If it is insulative, a conductive bonding material such as Au-Sn solder may be used as in the above-described embodiments.
【００６８】本実施形態７の半導体装置１、すなわちＩ
Ｃ（集積回路装置）においても、支持板４にワイヤ１４
を接続した場合、支持板４（支持分断片４０）のワイヤ
接続領域１３は接合材５で汚染されていないことから、
ワイヤ１４は確実に支持板４（支持分断片４０）に確実
に接続されることになり、ＩＣにおけるワイヤ接続の信
頼性が向上する。The semiconductor device 1 of the seventh embodiment, that is, I
C (integrated circuit device), the wire 14
Are connected, since the wire connection region 13 of the support plate 4 (the support segment 40) is not contaminated with the bonding material 5,
The wire 14 is securely connected to the support plate 4 (supporting piece 40), and the reliability of the wire connection in the IC is improved.
【００６９】図１１および図１２に示す半導体装置１
は、たとえば、各支持分断片４０は、２つのグランド
と、２電源電位を有する半導体装置である。Semiconductor device 1 shown in FIGS. 11 and 12
For example, each supporting segment 40 is a semiconductor device having two grounds and two power supply potentials.
【００７０】本実施形態７においても、前記実施形態３
〜実施形態６の浸入停止手段を適用することができる。In the seventh embodiment, the third embodiment is also used.
The intrusion stopping means of the sixth embodiment can be applied.
【００７１】なお、前記段差，突条，溝等は、パッケー
ジ２内に浸入した水分の半導体チップ６に至る距離をい
ずれも長くさせることになり、半導体装置１の耐湿性が
向上する。The steps, the ridges, the grooves, and the like increase the distance of the water penetrating into the package 2 to the semiconductor chip 6, thereby improving the moisture resistance of the semiconductor device 1.
【００７２】以上本発明者によってなされた発明を実施
形態に基づき具体的に説明したが、本発明は上記実施形
態に限定されるものではなく、その要旨を逸脱しない範
囲で種々変更可能であることはいうまでもない。Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
【００７３】[0073]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００７４】（１）主面に半導体チップ固定領域とワイ
ヤ接続領域を有する支持板において、前記半導体チップ
固定領域とワイヤ接続領域との間に浸入停止手段が設け
られていることから、前記半導体チップ固定領域に接合
材を介して半導体チップを固定する際、溶けた接合材は
前記浸入停止手段によって遮られるため、ワイヤ接続領
域に到達しなくなり、ワイヤ接続領域は接合材によって
汚染されなくなる。この結果、ワイヤ接続領域にワイヤ
を接続した場合、ワイヤ接続領域の表面は接合材が付着
していないことから、強固に接続され、ワイヤの接続強
度向上およびワイヤの接続信頼性が高くなる。(1) In a support plate having a semiconductor chip fixing region and a wire connection region on a main surface, an intrusion stop means is provided between the semiconductor chip fixing region and the wire connection region. When the semiconductor chip is fixed to the fixing region via the bonding material, the melted bonding material is blocked by the intrusion stopping means, so that it does not reach the wire connection region, and the wire connection region is not contaminated by the bonding material. As a result, when a wire is connected to the wire connection region, since the surface of the wire connection region has no bonding material attached thereto, it is firmly connected, and the connection strength of the wire is improved and the connection reliability of the wire is increased.
【図１】本発明の一実施形態（実施形態１）である半導
体装置を示す一部を除去した斜視図である。FIG. 1 is a perspective view of a semiconductor device according to an embodiment (Embodiment 1) of the present invention, with a part thereof removed.
【図２】本実施形態１の半導体装置を示す断面図であ
る。FIG. 2 is a cross-sectional view illustrating the semiconductor device of the first embodiment.
【図３】本実施形態１の半導体装置の製造に使用するリ
ードフレームを示す平面図である。FIG. 3 is a plan view showing a lead frame used for manufacturing the semiconductor device of the first embodiment.
【図４】本実施形態１の半導体装置の製造に使用するリ
ードフレームの支持板部分を示す斜視図である。FIG. 4 is a perspective view showing a support plate portion of a lead frame used for manufacturing the semiconductor device of the first embodiment.
【図５】本実施形態１の半導体装置の製造において、半
導体チップを固定し、ワイヤボンディングを行ったリー
ドフレームを示す平面図である。FIG. 5 is a plan view showing a lead frame to which a semiconductor chip is fixed and wire bonding has been performed in the manufacture of the semiconductor device of the first embodiment.
【図６】本発明の他の実施形態（実施形態２）のリード
フレームの支持板部分を示す斜視図である。FIG. 6 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 2) of the present invention.
【図７】本発明の他の実施形態（実施形態３）のリード
フレームの支持板部分を示す斜視図である。FIG. 7 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 3) of the present invention.
【図８】本発明の他の実施形態（実施形態４）のリード
フレームの支持板部分を示す斜視図である。FIG. 8 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 4) of the present invention.
【図９】本発明の他の実施形態（実施形態５）のリード
フレームの支持板部分を示す斜視図である。FIG. 9 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 5) of the present invention.
【図１０】本発明の他の実施形態（実施形態６）のリー
ドフレームの支持板部分を示す斜視図である。FIG. 10 is a perspective view showing a support plate portion of a lead frame according to another embodiment (Embodiment 6) of the present invention.
【図１１】本発明の他の実施形態（実施形態７）である
半導体装置を示す一部を除去した平面図である。FIG. 11 is a plan view of a semiconductor device according to another embodiment (Embodiment 7) of the present invention, with a part thereof removed.
【図１２】本実施形態７の半導体装置を示す断面図であ
る。FIG. 12 is a cross-sectional view illustrating a semiconductor device according to a seventh embodiment.
１…半導体装置、２…パッケージ、３…リード、４…支
持板、５…接合材、６…半導体チップ、７…ワイヤ接続
部、１０…窪み、１１…半導体チップ固定領域、１２…
ワイヤ接続部、１３…ワイヤ接続領域、１４…ワイヤ、
１５…リードフレーム、１６…外枠、１７…内枠、２０
…支持リード、２５…高い面、２６…低い面、２７…凸
面、３０…突条、３５…溝、３６…不連続な溝、４０…
支持分断片。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Package, 3 ... Lead, 4 ... Support plate, 5 ... Bonding material, 6 ... Semiconductor chip, 7 ... Wire connection part, 10 ... Depression, 11 ... Semiconductor chip fixing area, 12 ...
Wire connection portion, 13: wire connection area, 14: wire,
15 ... lead frame, 16 ... outer frame, 17 ... inner frame, 20
... support lead, 25 ... high surface, 26 ... low surface, 27 ... convex surface, 30 ... projection, 35 ... groove, 36 ... discontinuous groove, 40 ...
Supporting fragments.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大岡 幹治 埼玉県戸田市新曽南３−17−35 株式会社 ジャパンエナジー内 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mikiharu Ooka 3-17-35 Niisonanami, Toda City, Saitama Prefecture Japan Energy Co., Ltd.
Claims (14)
介して固定される半導体チップと、前記半導体チップを
被うように少なくとも前記支持板の主面側に設けられる
封止体と、前記封止体の内外に亘って延在する複数のリ
ードと、前記封止体内で前記リードおよび前記支持板と
前記半導体チップの電極とを電気的に接続する導電性の
ワイヤとを有する半導体装置であって、前記支持板の半
導体チップを固定する半導体チップ固定領域と、ワイヤ
を接続するワイヤ接続領域との間に前記接合材が流出し
て前記ワイヤ接続領域に浸入するのを停止させる浸入停
止手段が設けられていることを特徴とする半導体装置。1. A support plate, a semiconductor chip fixed to a main surface of the support plate via a bonding material, and a sealing body provided at least on a main surface side of the support plate so as to cover the semiconductor chip. And a plurality of leads extending inside and outside the sealing body, and a conductive wire for electrically connecting the leads, the support plate, and the electrode of the semiconductor chip inside the sealing body. A semiconductor device, wherein the bonding material stops flowing between a semiconductor chip fixing region for fixing a semiconductor chip of the support plate and a wire connection region for connecting a wire to enter the wire connection region. A semiconductor device comprising an intrusion stop means.
プ固定領域面よりも高くなっていることを特徴とする請
求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein said wire connection region surface is higher than said semiconductor chip fixing region surface.
けられ、前記窪み底面が前記半導体チップ固定領域を構
成することを特徴とする請求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein a depression is partially provided on a main surface of the support plate, and the bottom surface of the depression forms the semiconductor chip fixing region.
けられ、前記凸面が前記ワイヤ接続領域を構成すること
を特徴とする請求項２記載の半導体装置。4. The semiconductor device according to claim 2, wherein at least one convex surface is provided on a main surface of said support plate, and said convex surface forms said wire connection region.
接続領域との間の前記支持板の主面には連続または不連
続な凸条が設けられていることを特徴とする請求項１記
載の半導体装置。5. The semiconductor according to claim 1, wherein a continuous or discontinuous ridge is provided on a main surface of the support plate between the semiconductor chip fixing region and the wire connection region. apparatus.
接続領域との間の前記支持板の主面には連続または不連
続な溝が設けられていることを特徴とする請求項１記載
の半導体装置。6. The semiconductor device according to claim 1, wherein a continuous or discontinuous groove is provided on a main surface of said support plate between said semiconductor chip fixing region and said wire connection region. .
徴とする請求項６記載の半導体装置。7. The semiconductor device according to claim 6, wherein said groove penetrates a support plate.
の外に突出する支持リードが設けられていることを特徴
とする請求項１乃至請求項７のいずれか１項記載の半導
体装置。8. The semiconductor device according to claim 1, further comprising a support lead projecting from said support plate and having a tip projecting outside said sealing body.
裏面側を被っていることを特徴とする請求項１乃至請求
項８のいずれか１項記載の半導体装置。9. The semiconductor device according to claim 1, wherein the sealing body covers a main surface side and a back surface side of the support plate.
は相互に電気的に独立する複数の支持分断片によって構
成され、かつ前記各支持分断片に前記ワイヤが接続され
ていることを特徴とする請求項１乃至請求項９のいずれ
か１項記載の半導体装置。10. A support plate to which said semiconductor chip is fixed is constituted by a plurality of support segments which are electrically independent from each other, and said wires are connected to said support segments. The semiconductor device according to claim 1.
る半導体チップ固定領域と、一つ以上のワイヤを接続す
るワイヤ接続領域を有するリードフレームであって、前
記半導体チップ固定領域とワイヤ接続領域との間に前記
接合材が流出して前記ワイヤ接続領域に浸入するのを停
止させる浸入停止手段が設けられていることを特徴とす
るリードフレーム。11. A lead frame having a semiconductor chip fixing region for fixing a semiconductor chip on a main surface of a support plate and a wire connection region for connecting one or more wires, wherein the semiconductor chip fixing region and the wire connection region are provided. A lead-in stop means for stopping the joining material from flowing out and entering the wire connection region.
ップ固定領域面よりも高くなっていることを特徴とする
請求項１１記載のリードフレーム。12. The lead frame according to claim 11, wherein said wire connection region surface is higher than said semiconductor chip fixing region surface.
ヤ接続領域との間の支持板の主面には連続または不連続
な凸条が設けられていることを特徴とする請求項１１記
載のリードフレーム。13. The lead frame according to claim 11, wherein a continuous or discontinuous ridge is provided on a main surface of the support plate between the semiconductor chip fixing region and the wire connection region. .
ヤ接続領域との間の前記支持板の主面には連続または不
連続な溝が設けられていることを特徴とする請求項１１
記載のリードフレーム。14. A continuous or discontinuous groove is provided on a main surface of the support plate between the semiconductor chip fixing region and the wire connection region.
Lead frame as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9050677A JPH10247701A (en) | 1997-03-05 | 1997-03-05 | Semiconductor device and lead frame for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9050677A JPH10247701A (en) | 1997-03-05 | 1997-03-05 | Semiconductor device and lead frame for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10247701A true JPH10247701A (en) | 1998-09-14 |
Family
ID=12865577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9050677A Pending JPH10247701A (en) | 1997-03-05 | 1997-03-05 | Semiconductor device and lead frame for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10247701A (en) |
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| WO2006112332A1 (en) * | 2005-04-13 | 2006-10-26 | Rohm Co., Ltd. | Semiconductor device and lead frame |
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| JP2012104709A (en) * | 2010-11-11 | 2012-05-31 | Shindengen Electric Mfg Co Ltd | Lead frame and semiconductor device |
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| JP2006503427A (en) * | 2002-10-09 | 2006-01-26 | ミクロナス ゲーエムベーハー | Support device for monolithic integrated circuits |
| JP2006524904A (en) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ，インコーポレイテッド | Semiconductor die package with reduced inductance and reduced die adhesive flow |
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