JP2002164496A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same

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Publication number
JP2002164496A
JP2002164496A JP2000358826A JP2000358826A JP2002164496A JP 2002164496 A JP2002164496 A JP 2002164496A JP 2000358826 A JP2000358826 A JP 2000358826A JP 2000358826 A JP2000358826 A JP 2000358826A JP 2002164496 A JP2002164496 A JP 2002164496A
Authority
JP
Japan
Prior art keywords
die pad
mounting surface
semiconductor chip
sealing
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000358826A
Other languages
Japanese (ja)
Inventor
Hajime Hasebe
一 長谷部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP2000358826A priority Critical patent/JP2002164496A/en
Publication of JP2002164496A publication Critical patent/JP2002164496A/en
Pending legal-status Critical Current

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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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Abstract

PROBLEM TO BE SOLVED: To increase bonding reliability of a die pad down binding by preventing delamination between a die pad and a molding resin, and bleeding. SOLUTION: A die pad 2 formed in a QFN semiconductor device 1 has a rectangle pad portion 2a where a semiconductor chip is mounted and down bonding portions 2b, 2c formed having four sides of the die pad 2a extending outside. Folded portions K are formed between the die pad portion 2a and the down bonding portions 2b, 2c, and the down bonding portions 2b, 2c are placed upward relative to the die pad portion 2a. The down bonding portions 2b, 2c are connected to arbitrary electrodes for a reference voltage VSS in the semiconductor chip 5 via bonding wires 7a to increase electrical performance, so called down bond is performed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置におけ
る接続信頼性の向上技術に関し、特に、ＱＦＮ（Ｑｕａ
ｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ ｐａｃｋａｇ
ｅ）形半導体装置におけるダイパッドダウンボンドの接
続信頼性の向上に適用して有効な技術に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for improving connection reliability in a semiconductor device, and more particularly, to a QFN (Qua).
d Flat Non-leaded packag
The present invention relates to a technique which is effective when applied to improve the connection reliability of a die pad down bond in an e) type semiconductor device.

【０００２】[0002]

【従来の技術】本発明者が検討したところによれば、表
面実装形パッケージの１つとして、ＱＦＮ形の半導体装
置がある。ＱＦＮ形の半導体装置は、パッケージの４つ
の側面に複数の電極パッドをそれぞれ備えた構成が一般
的に知られている。2. Description of the Related Art According to studies made by the present inventor, a QFN type semiconductor device is one of surface mount packages. It is generally known that a QFN type semiconductor device has a configuration in which a plurality of electrode pads are provided on four side surfaces of a package.

【０００３】この半導体装置においては、パッケージの
薄型化、および放熱性の向上を図るためにダイパッドの
裏面が露出したダイパッド露出構造のパッケージがあ
る。このような構造の半導体装置では電気的特性を向上
させるために、たとえば、半導体チップに設けられた基
準電位ＶSS用のチップ電極、あるいは電源電圧ＶCC用の
チップ電極部とダイパッドとをボンディングワイヤによ
ってボンディングする、いわゆるダイパッドダウンボン
ドが行われている。In this semiconductor device, there is a package having an exposed die pad structure in which the back surface of the die pad is exposed in order to reduce the thickness of the package and improve heat dissipation. In a semiconductor device having such a structure, in order to improve electrical characteristics, for example, a chip electrode for a reference potential V SS provided on a semiconductor chip, or a chip electrode portion for a power supply voltage V CC and a die pad are bonded with a bonding wire. A so-called die pad down bond is performed.

【０００４】なお、この種の半導体装置について詳しく
述べてある例としては、特開平８−８３８７０号公報が
あり、この文献には、ダイパッド露出構造のＱＦＮ形半
導体装置について記載されている。Japanese Patent Application Laid-Open No. 8-83870 discloses an example of this type of semiconductor device in detail, which describes a QFN type semiconductor device having an exposed die pad structure.

【０００５】[0005]

【発明が解決しようとする課題】ところが、上記のよう
なダイパッド露出構造の半導体装置では、次のような問
題点があることが本発明者により見い出された。However, the present inventors have found that the semiconductor device having the above-described die pad exposed structure has the following problems.

【０００６】すなわち、ダイパッドとパッケージを形成
するモールド樹脂との熱膨張係数の違いなどから、ダイ
パッドとモールド樹脂との界面が剥離してしまい、その
隙間から水分などが侵入し、ボンディングワイヤの腐食
による接続不良や断線などが発生してしまう恐れがあ
る。That is, due to the difference in the coefficient of thermal expansion between the die pad and the mold resin forming the package, the interface between the die pad and the mold resin is peeled off, moisture and the like enter through the gap, and the bonding wire is corroded. There is a possibility that poor connection or disconnection may occur.

【０００７】また、ダウンボンド対応のダイパッドに
は、ボンディングワイヤとの接続性を高めるために銀め
っきなどの処理が施されており、このめっきによってダ
イパッドとモールド樹脂との密着性がより阻害され、剥
離が発生しやすいという問題が生じている。Further, the die pad for down bonding is subjected to a treatment such as silver plating in order to enhance the connectivity with the bonding wire, and this plating further hinders the adhesion between the die pad and the mold resin. There is a problem that peeling is likely to occur.

【０００８】さらに、ダイパッドは、半導体チップが搭
載されるダイボンド部分とダイパッドダウンボンドが行
われるダウンボンド部分とが同じ高さであるので、ダイ
ボンド時に、ダイパッドのチップ搭載面に銀ペーストな
どの接着材を塗布した際に該ダイパッドのチップ搭載面
に接着材が流れる、いわゆるブリード現象が発生し、こ
の現象によって該ダイパッドのボンディング面が汚染さ
れてしまい、ボンディングワイヤの接続不良などが生じ
てしまう恐れもある。Further, since the die pad has the same height as the die bond portion where the semiconductor chip is mounted and the down bond portion where the die pad down bond is performed, an adhesive such as silver paste is attached to the die mounting surface of the die pad during die bonding. When the adhesive is applied, an adhesive flows on the chip mounting surface of the die pad, that is, a so-called bleed phenomenon occurs, and this phenomenon may contaminate the bonding surface of the die pad and cause a connection failure of a bonding wire. is there.

【０００９】本発明の目的は、ダイパッドとモールド樹
脂との剥離を防止し、かつブリード現象を防止すること
によって、ダイパッドダウンボンディングの接続信頼性
を大幅に向上することのできる半導体装置およびその製
造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can significantly improve the connection reliability of die pad down bonding by preventing separation of a die pad from a mold resin and preventing bleeding. Is to provide.

【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１１】[0011]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【００１２】すなわち、本発明の半導体装置は、搭載面
に半導体チップが搭載され、その搭載面の反対面が封止
部の実装面から露出する四角形状のダイパッド部と、該
ダイパッドの外周辺が外方に延在し、かつ外周辺近傍が
屈折した屈折部が設けられて封止部により封止されたダ
ウンボンディング部とからなるダイパッドを備えたもの
である。That is, in the semiconductor device of the present invention, a semiconductor chip is mounted on a mounting surface, and a rectangular die pad portion having a surface opposite to the mounting surface exposed from a mounting surface of a sealing portion, and an outer periphery of the die pad. A die pad is provided which includes a refraction portion extending outward and having a refraction in the vicinity of the outer periphery, and a down bonding portion sealed by a sealing portion.

【００１３】また、本発明の半導体装置は、搭載面に半
導体チップが搭載され、その搭載面の反対面が封止部の
実装面から露出する四角形状のダイパッド部と、該ダイ
パッドの外周辺が外方に延在し、かつ外周辺近傍が屈折
した屈折部が設けられて封止部により封止され、屈折部
の両側に切り込みが形成されたダウンボンディング部と
からなるダイパッドを備えたものである。Further, in the semiconductor device of the present invention, a semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of a sealing portion. A die pad including a down bonding portion extending outward and having a bent portion whose outer periphery and vicinity is bent is provided and sealed by a sealing portion, and cuts are formed on both sides of the bent portion. is there.

【００１４】さらに、本発明の半導体装置は、搭載面に
半導体チップが搭載され、その搭載面の反対面が封止部
の実装面から露出する四角形状のダイパッド部と、該ダ
イパッドの外周辺が外方に延在し、かつ外周辺近傍が屈
折した屈折部が設けられて封止部により封止され、屈折
部にスリットが形成されたダウンボンディング部とから
なるダイパッドを備えたものである。Further, in the semiconductor device according to the present invention, a semiconductor chip is mounted on a mounting surface, and a rectangular die pad portion in which a surface opposite to the mounting surface is exposed from a mounting surface of a sealing portion. There is provided a die pad including a refraction portion extending outward and having a refraction in the vicinity of the outer periphery, which is sealed by a sealing portion, and a down bonding portion in which a slit is formed in the refraction portion.

【００１５】また、本発明の半導体装置の製造方法は、
半導体チップが搭載される搭載面の反対面が封止部の実
装面から露出する四角形状のダイパッド部と該ダイパッ
ドの外周辺が外方に延在し、かつ外周辺近傍が屈折した
屈折部が設けられて封止部により封止されたダウンボン
ディング部とからなるダイパッドが設けられ、該ダイパ
ッドの周辺部に配置され、半導体チップの表面電極に対
応する複数の電極部が形成されたリードフレームを準備
する工程と、半導体チップとダイパッド部とを接合する
工程と、半導体チップの表面電極とこれに対応する電極
部、ならびに該半導体チップの表面電極とこれに対応す
るダイパッド部とを接続部材により接続する工程と、半
導体チップを封止樹脂によって覆うとともに、半導体装
置の実装面側に電極部とダイパッド部とを露出して樹脂
モールドし、封止部を形成する工程と、電極部の露出
面、ならびにダイパッド部の露出面にはんだ皮膜を積層
して形成する工程と、電極部をリードフレームの枠部か
ら分離し、外部電極部を形成する工程とを有するもので
ある。Further, a method of manufacturing a semiconductor device according to the present invention
A square die pad portion in which the opposite surface of the mounting surface on which the semiconductor chip is mounted is exposed from the mounting surface of the sealing portion, and an outer periphery of the die pad extends outward, and a refraction portion in which the outer periphery is bent is formed. A die pad comprising a down bonding portion provided and sealed by a sealing portion is provided, and a lead frame is provided around the die pad and formed with a plurality of electrode portions corresponding to surface electrodes of a semiconductor chip. A preparing step, a step of joining the semiconductor chip and the die pad portion, and a connection member connecting the surface electrode of the semiconductor chip and the corresponding electrode portion, and the surface electrode of the semiconductor chip and the corresponding die pad portion with a connecting member And covering the semiconductor chip with a sealing resin, exposing the electrode portion and the die pad portion on the mounting surface side of the semiconductor device and performing resin molding, and sealing. Forming a solder film on the exposed surface of the electrode portion, and the exposed surface of the die pad portion, and separating the electrode portion from the frame of the lead frame to form an external electrode portion. It has.

【００１６】さらに、本発明の半導体装置の製造方法
は、搭載面に半導体チップが搭載され、その搭載面の反
対面が封止部の実装面から露出する四角形状のダイパッ
ド部とダイパッドの外周辺が外方に延在し、かつ外周辺
近傍が屈折した屈折部が設けられて封止部により封止さ
れ、該屈折部の両側に切り込みが形成されたダウンボン
ディング部とからなるダイパッドが設けられ、該ダイパ
ッドの周辺部に配置され、半導体チップの表面電極に対
応する複数の電極部が形成されたリードフレームを準備
する工程と、半導体チップとダイパッド部とを接合する
工程と、半導体チップの表面電極とこれに対応する電極
部、ならびに該半導体チップの表面電極とこれに対応す
るダイパッド部とを接続部材により接続する工程と、半
導体チップを封止樹脂によって覆うとともに、半導体装
置の実装面側に電極部とダイパッド部とを露出して樹脂
モールドし、封止部を形成する工程と、電極部の露出
面、ならびにダイパッド部の露出面にはんだ皮膜を積層
して形成する工程と、電極部をリードフレームの枠部か
ら分離し、外部電極部を形成する工程とを有するもので
ある。Further, in the method of manufacturing a semiconductor device according to the present invention, a semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of a sealing portion. A die pad is provided which extends outward and is provided with a refraction portion whose outer periphery and vicinity are bent and sealed by a sealing portion, and a down bonding portion formed with cuts on both sides of the refraction portion. Preparing a lead frame disposed around the die pad and having a plurality of electrode portions corresponding to surface electrodes of the semiconductor chip; bonding the semiconductor chip to the die pad portion; Connecting the electrode and the corresponding electrode portion, the surface electrode of the semiconductor chip and the corresponding die pad portion by a connecting member, and sealing the semiconductor chip with a sealing resin. A process of exposing the electrode portion and the die pad portion on the mounting surface side of the semiconductor device and performing resin molding to form a sealing portion, and applying a solder film to the exposed surface of the electrode portion and the exposed surface of the die pad portion. The method includes a step of forming by lamination and a step of separating an electrode portion from a frame portion of a lead frame to form an external electrode portion.

【００１７】[0017]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.

【００１８】図１は、本発明の一実施の形態による半導
体装置の説明図、図２は、図１の半導体装置におけるダ
イパッドの断面図、図３〜図５は、図１の半導体装置に
おける製造工程の説明図、図６は、図１の半導体装置に
おける製造工程のフローチャートである。FIG. 1 is an explanatory view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of a die pad in the semiconductor device of FIG. 1, and FIGS. FIG. 6 is a flowchart of a manufacturing process in the semiconductor device of FIG.

【００１９】本実施の形態１において、半導体装置１
は、ノンリード表面実装パッケージの１つであるＱＦＮ
からなる。半導体装置１は、図１、および図２に示すよ
うに、中央部にダイパッド２が位置している。In the first embodiment, the semiconductor device 1
Is one of the non-lead surface mount packages, QFN
Consists of As shown in FIGS. 1 and 2, the semiconductor device 1 has a die pad 2 located at the center.

【００２０】このダイパッド２は、４本のタブ吊りリー
ド３によって支持されており、該ダイパッド２上には、
銀ペースト接着材などの接着材４を介して半導体チップ
５が接着固定されている。The die pad 2 is supported by four tab suspension leads 3, and on the die pad 2,
The semiconductor chip 5 is bonded and fixed via an adhesive 4 such as a silver paste adhesive.

【００２１】ダイパッド２は、半導体チップ５が搭載さ
れる四角形のダイパッド部２ａと、ダイパッド部２ａの
４辺が、該ダイパッド部２ａの平面方向に外方に向けて
それぞれ延在したダウンボンディング部２ｂ〜２ｅとか
らなり、十字状に構成されている。The die pad 2 includes a square die pad portion 2a on which the semiconductor chip 5 is mounted, and a down bonding portion 2b in which four sides of the die pad portion 2a extend outward in the plane direction of the die pad portion 2a. To 2e, and is formed in a cross shape.

【００２２】また、ダイパッド部２ａとダウンボンディ
ング部２ｂ〜２ｅとの間には、たとえばプレス機などに
よって折り曲げ加工が施されて屈折部Ｋがそれぞれ形成
されており、ダウンボンディング部２ｂ〜２ｅは、ダイ
パッド部２ａよりも上方に位置している。A bending portion K is formed between the die pad portion 2a and the down bonding portions 2b to 2e by, for example, a press machine to form bending portions K. The down bonding portions 2b to 2e It is located above the die pad portion 2a.

【００２３】この屈折部Ｋは、たとえば、図７に示すよ
うに、ハーフエッチングを施して薄板化することによ
り、曲げ加工を容易に行うことができる。折れ曲がり部
分の薄板化の例としては、ハーフィエッチングの他に、
Ｖ溝加工、あるいはつぶし加工などを上げることができ
る。As shown in FIG. 7, for example, as shown in FIG. 7, the bending portion K can be easily bent by performing half etching to make it thinner. As an example of thinning the bent part, besides Hafi etching,
V-groove processing or crushing processing can be performed.

【００２４】これらダウンボンディング部２ｂ〜２ｅ
は、該ダウンボンディング部２ｂ〜２ｅのボンディング
面の反対面に封止樹脂が充分に回り込む程度で、かつ該
ダウンボンディング部２ｂ〜２ｅのボンディング面が半
導体チップ５よりも低くなるような高さとなっている。These down bonding portions 2b to 2e
Is such a height that the sealing resin sufficiently wraps around the bonding surface of the down bonding portions 2b to 2e and that the bonding surface of the down bonding portions 2b to 2e is lower than the semiconductor chip 5. ing.

【００２５】このダウンボンディング部２ｂ〜２ｅにお
ける４辺の周辺部近傍には、複数のインナリード６がそ
れぞれ位置しており、これらインナリード６の先端部と
半導体チップ５に形成された電極（表面電極）とが、金
線などからなるボンディングワイヤ（接続部材）７によ
って電気的にそれぞれ接続されている。A plurality of inner leads 6 are located near the periphery of the four sides of the down bonding portions 2b to 2e, respectively. The tips of the inner leads 6 and the electrodes (surfaces) formed on the semiconductor chip 5 are formed. The electrodes are electrically connected to each other by bonding wires (connection members) 7 made of a gold wire or the like.

【００２６】さらに、半導体チップ５における任意の電
極、たとえば、基準電位ＶSS用の電極などには、電気的
特性を向上させるためにダウンボンディング部２ｂ〜２
ｅがボンディングワイヤ（接続部材）７ａを介して接続
される、いわゆるダウンボンドが行われている。これら
ダウンボンディング部２ｂ〜２ｅの表面には、ボンディ
ングワイヤ７ａとの接続を確実にするために銀（Ａｇ）
めっきなどが施されている。Further, any electrodes in the semiconductor chip 5, for example, electrodes for the reference potential V SS , are provided with down bonding portions 2b to 2b to improve electrical characteristics.
The so-called down bonding in which e is connected via a bonding wire (connection member) 7a is performed. Silver (Ag) is formed on the surfaces of these down bonding portions 2b to 2e in order to secure the connection with the bonding wire 7a.
Plating is applied.

【００２７】また、半導体チップ５、インナリード６、
ならびにボンディングワイヤ７，７ａは、熱硬化性の封
止樹脂によって封止され、矩形状のパッケージ（封止
部）８が形成されている。The semiconductor chip 5, the inner leads 6,
In addition, the bonding wires 7 and 7a are sealed with a thermosetting sealing resin to form a rectangular package (sealing portion) 8.

【００２８】このパッケージ８における４辺には、複数
の外部電極９が形成されており、ダイパッド部２ａにお
ける半導体チップ５が搭載されない面、ならびに外部電
極９は、パッケージ８における実装面、側面から露出し
て形成されている。A plurality of external electrodes 9 are formed on four sides of the package 8, and the surface of the die pad 2a on which the semiconductor chip 5 is not mounted and the external electrodes 9 are exposed from the mounting surface and side surfaces of the package 8. It is formed.

【００２９】また、ダウンボンディング部２ｂ〜２ｅ
は、前述したように折り曲げ加工によってダイパッド部
２ａよりも上方に位置しているので封止樹脂によって封
止され、パッケージ７からは露出しないことになる。The down bonding portions 2b to 2e
Is located above the die pad portion 2a by the bending process as described above, and thus is sealed by the sealing resin, and is not exposed from the package 7.

【００３０】そして、半導体装置１の実装時には、外部
電極９が、該半導体装置１の実装時に電子部品などを実
装するプリント配線基板に形成された接続電極となるラ
ンドと重合し、それぞれ電気的に接続される。When the semiconductor device 1 is mounted, the external electrodes 9 overlap with lands serving as connection electrodes formed on a printed wiring board on which electronic components and the like are mounted when the semiconductor device 1 is mounted, and are electrically connected to each other. Connected.

【００３１】また、ダウンボンディング部２ｂ〜２ｅ
に、ボンディングワイヤ７ａを介して半導体チップ５の
基準電位ＶSS用の電極が接続されている場合、パッケー
ジ８から露出したダイパッド部２ａの露出面（半導体チ
ップ５の搭載面の反対面）にはプリント配線基板に形成
された基準電位ＶSS用のランドが接続される。The down bonding portions 2b to 2e
When the electrode for the reference potential V SS of the semiconductor chip 5 is connected to the semiconductor chip 5 via the bonding wire 7a, the exposed surface of the die pad portion 2a exposed from the package 8 (the surface opposite to the mounting surface of the semiconductor chip 5) A land for the reference potential V SS formed on the printed wiring board is connected.

【００３２】さらに、ボンディングワイヤ７ａを介して
ダウンボンディング部２ｂ〜２ｅと半導体チップ５の電
源電圧ＶCC用の電極が接続されている場合には、パッケ
ージ８から露出したダイパッド部２ａの露出面（半導体
チップ５の搭載面の反対面）にはプリント配線基板に形
成された電源電圧ＶCC用のランドが接続される。Further, when the down bonding portions 2b to 2e and the electrode for the power supply voltage V CC of the semiconductor chip 5 are connected via the bonding wires 7a, the exposed surface of the die pad portion 2a exposed from the package 8 ( A land for the power supply voltage V CC formed on the printed wiring board is connected to the surface opposite to the mounting surface of the semiconductor chip 5).

【００３３】次に、本実施の形態における半導体装置の
製造方法について、図３〜図５の工程説明図、および図
６のフローチャートを用いて説明する。Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to the process explanatory diagrams of FIGS. 3 to 5 and the flowchart of FIG.

【００３４】まず、リードフレームを準備する（ステッ
プＳ１０１）。このリードフレームは、たとえば、鉄系
や銅系などからなる金属板をエッチング、あるいはプレ
ス加工してパターンニングすることによって形成され
る。First, a lead frame is prepared (step S101). The lead frame is formed by, for example, etching or pressing a metal plate made of iron or copper and patterning it.

【００３５】リードフレームには、前述した折り曲げ加
工が施されたダイパッド２、インナリード６、ならびに
電極部９ａとなるアウタリード１０が成形され、それら
のパターンが数個以上連結された金属製のリボン構造よ
りなる。The lead frame is formed with the die pad 2, the inner lead 6, and the outer lead 10 serving as the electrode portion 9a which have been subjected to the above-mentioned bending process, and a metal ribbon structure in which several or more of those patterns are connected. Consisting of

【００３６】そして、ダイパッド部２ａに銀ペースト接
着材などの接着材４を塗布し、半導体チップ５を搭載し
て接着固定する（ステップＳ１０２）。このとき、接着
材４がダイパッド部２ａのチップ搭載面に流れ出す、い
わゆるブリード現象が発生しても、折れ曲げ加工が施さ
れたダウンボンディング部２ｂ〜２ｅは、ダイパッド部
２ａよりも高い位置にあるので、接着材４による汚染を
防止することができる。Then, an adhesive 4 such as a silver paste adhesive is applied to the die pad portion 2a, and the semiconductor chip 5 is mounted and fixed (step S102). At this time, even if a so-called bleed phenomenon occurs in which the adhesive 4 flows out to the chip mounting surface of the die pad portion 2a, the bent down bonding portions 2b to 2e are located at a position higher than the die pad portion 2a. Therefore, contamination by the adhesive 4 can be prevented.

【００３７】その後、図３に示すように、半導体チップ
５の電極とリードフレームのインナリード６、ならびに
半導体チップ５における特定の電極とダウンボンディン
グ部２ｂ〜２ｅとをボンディングワイヤ７，７ａによっ
てそれぞれ接合し、電気的に接続する（ステップＳ１０
３）。Thereafter, as shown in FIG. 3, the electrodes of the semiconductor chip 5 and the inner leads 6 of the lead frame, and the specific electrodes of the semiconductor chip 5 and the down bonding portions 2b to 2e are bonded by bonding wires 7, 7a. And make an electrical connection (step S10).
3).

【００３８】また、ステップＳ１０３の処理において、
ダウンボンディング部２ｂ〜２ｅが上方に位置している
ことにより、半導体チップ５の電極とダウンボンディン
グ部２ｂ〜２ｅとの高低差が小さくなるのでワイヤルー
プの形成が比較的容易となり、安定したワイヤボンディ
ングを行うことができる。In the process of step S103,
Since the down bonding portions 2b to 2e are located above, the height difference between the electrode of the semiconductor chip 5 and the down bonding portions 2b to 2e is reduced, so that the wire loop is relatively easily formed, and the stable wire bonding is performed. It can be performed.

【００３９】ワイヤボンディングされたリードフレーム
は、図４に示すように、モールド装置による半導体モー
ルド形成によって樹脂封止され、図５に示すように、パ
ッケージ８が形成される（ステップＳ１０４）。The wire-bonded lead frame is resin-sealed by forming a semiconductor mold using a molding device as shown in FIG. 4, and a package 8 is formed as shown in FIG. 5 (step S104).

【００４０】モールド装置は、モールド金型Ｋ１，Ｋ２
によってリードフレームのアウタリード１０を該リード
フレームの厚さ方向に挟み込み、ダイパッド２を支持す
るリード近傍に設けられたモールド金型のゲートからキ
ャビティに封止樹脂を注入してパッケージ８を形成す
る。よって、パッケージ８の実装面には、アウタリード
１０、ならびにダイパッド部２ａの裏面が露出すること
になる。The molding apparatus includes molding dies K1 and K2.
Thus, the outer lead 10 of the lead frame is sandwiched in the thickness direction of the lead frame, and a sealing resin is injected into the cavity from the gate of the mold provided near the lead supporting the die pad 2 to form the package 8. Therefore, the outer leads 10 and the back surface of the die pad portion 2a are exposed on the mounting surface of the package 8.

【００４１】その後、パッケージ８から露出したリード
フレームのアウタリード１０、およびダイパッド部２ａ
の裏面に、たとえば、電解めっき法などによってはんだ
めっき（はんだ皮膜）を施す（ステップＳ１０５）。Thereafter, the outer lead 10 of the lead frame exposed from the package 8 and the die pad portion 2a
Is subjected to solder plating (solder film) by, for example, an electrolytic plating method (Step S105).

【００４２】はんだめっき処理の後、パッケージ８の側
面から突出したアウタリード１０は、該パッケージ８の
側面と段差なく平面状態になるように切断されて（ステ
ップＳ１０６）、外部引き出し線となる外部電極９が形
成され、図１、図２に示す半導体装置１が完成する（ス
テップＳ１０７）。After the solder plating process, the outer leads 10 protruding from the side surfaces of the package 8 are cut so as to be flat without any level difference from the side surfaces of the package 8 (step S106), and the external electrodes 9 serving as external lead lines are cut. Is formed, and the semiconductor device 1 shown in FIGS. 1 and 2 is completed (Step S107).

【００４３】製品となった半導体装置１は、外部電極
９、ならびにダイパッド部２ａが実装基板であるプリン
ト配線基板に形成されたランドと重合し、リフローはん
だ付けなどによってそれぞれ電気的に接続され、プリン
ト配線基板に実装される。In the semiconductor device 1 as a product, the external electrode 9 and the die pad portion 2a are overlapped with lands formed on a printed wiring board, which is a mounting board, and are electrically connected to each other by reflow soldering or the like. It is mounted on a wiring board.

【００４４】それにより、本実施の形態によれば、ダウ
ンボンディング部２ｂ〜２ｅをダイパッド部２ａよりも
上方に設けたことにより、ダウンボンディング部２ｂ〜
２ｅの全面が樹脂封止されるので密着性が向上し、該ダ
ウンボンディング部２ｂ〜２ｅとパッケージ７との剥離
などを防止することができ、半導体装置１の接続信頼性
を向上することができる。Thus, according to the present embodiment, since the down bonding portions 2b to 2e are provided above the die pad portion 2a, the down bonding portions 2b to 2e are provided.
Since the entire surface of 2e is resin-sealed, adhesion is improved, separation of the down bonding portions 2b to 2e from the package 7 and the like can be prevented, and connection reliability of the semiconductor device 1 can be improved. .

【００４５】また、ダウンボンディング部２ｂ〜２ｅを
ダイパッド部２ａよりも上方に設けることにより、接着
材４が該ダウンボンディング部２ｂ〜２ｅに流れて汚染
することを防止できるので、ダウンボンドの信頼性を向
上することができる。Further, by providing the down bonding portions 2b to 2e above the die pad portion 2a, it is possible to prevent the adhesive 4 from flowing to the down bonding portions 2b to 2e and to contaminate the down bonding portions. Can be improved.

【００４６】さらに、本実施の形態では、ダウンボンデ
ィング部２ｂ〜２ｅが四角形のダイパッド部２ａの４辺
が、該ダイパッド部２ａの平面方向にそれぞれ延在した
構成としたが、これらダウンボンディング部２ｂ〜２ｅ
は、ダイパッド部２ａと電気的に接続され、かつ該ダイ
パッド部２ａよりも高い位置に設けられていればどのよ
うな形状であってもよい。Further, in the present embodiment, the down bonding portions 2b to 2e are configured such that the four sides of the square die pad portion 2a extend in the plane direction of the die pad portion 2a, respectively. ~ 2e
May have any shape as long as it is electrically connected to the die pad portion 2a and provided at a position higher than the die pad portion 2a.

【００４７】たとえば、ダウンボンディング部２ｂ1 〜
２ｅ1 における屈折部Ｋを両側からそれぞれ切り込み、
図８に示すように、該ダウンボンディング部２ｂ1 〜２
ｅ1をＴ字状にしたり、あるいはダウンボンディング部
２ｂ2 〜２ｅ2 、ならびに屈折部Ｋにスリットを形成
し、図９に示すように、該ダウンボンディング部２ｂ2
〜２ｅ2 をＭ字状にしてもよい。For example, the down bonding portions 2b 1 to
Cut each bent portion K in 2e 1 from both sides,
As shown in FIG. 8, the down bonding portions 2b 1 to 2b 2
or a e 1 in a T-shape, or a slit down the bonding portion 2b 2 ~2e 2, and bent portions K, as shown in FIG. 9, the down bonded portion 2b 2
２2e 2 may be M-shaped.

【００４８】また、ダイパッド部２ａの平面方向に延在
させるのではなく、図１０に示すように、タブ吊りリー
ド３から延出して、半導体チップ５の外周辺と平行に位
置するように、ダウンボンディング部２ｂ3 〜２ｅ3 を
形成するようにてもよい。Further, instead of extending in the plane direction of the die pad portion 2a, the die pad portion 2a extends from the tab suspension lead 3 as shown in FIG. or at to form a bonding portion 2b 3 ~2e 3.

【００４９】この場合、タブ吊りリード３から延出した
部分に折り曲げ加工によって屈折部Ｋを設け、、ダウン
ボンディング部２ｂ3 〜２ｅ3 をダイパッド部２ａより
も上方に位置するように加工する。In this case, a bent portion K is provided by bending at a portion extending from the tab suspension lead 3, and the down bonding portions 2b 3 to 2e 3 are processed so as to be located above the die pad portion 2a.

【００５０】これらによって、ダウンボンディング部２
ｂ1 〜２ｂ3 ，２ｃ1 〜２ｃ3 ，２ｄ1 〜２ｄ3 ，２ｅ
1 〜２ｅ3 の表面積をより大きくできるので封止樹脂の
密着性を高くすることができ、これらダウンボンディン
グ部とパッケージ７との剥離などをより確実に防止する
ことができる。With these, the down bonding portion 2
b 1 ~2b 3, 2c 1 ~2c 3, 2d 1 ~2d 3, 2e
1 because the surface area of ～2E 3 can be further increased it is possible to increase the adhesion of the sealing resin, it is possible to prevent the peeling of these down bonding portion and the package 7 more reliably.

【００５１】さらに、前記実施の形態においては、ダウ
ンボンディング部２ｂ〜２ｂ3 ，２ｃ〜２ｃ3 ，２ｄ〜
２ｄ3 ，２ｅ〜２ｅ3 全面に銀めっきを施した場合につ
いて記載したが、たとえば、ポイントめっきなどにより
ボンディングワイヤ７ａがボンディングされる領域だけ
をめっきするようにしてもよい。[0051] Further, in the above embodiment, the down bonding portion 2b~2b 3, 2c~2c 3, 2d~
Although the case where silver plating is applied to the entire surface of 2d 3 , 2e to 2e 3 has been described, for example, only the region where the bonding wire 7a is bonded may be plated by point plating or the like.

【００５２】これによって、より封止樹脂の密着性を高
くすることができ、半導体装置１の接続信頼性を大幅に
向上することができる。As a result, the adhesion of the sealing resin can be further increased, and the connection reliability of the semiconductor device 1 can be greatly improved.

【００５３】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

【００５４】[0054]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【００５５】（１）本発明によれば、ダウンボンディン
グ部がすべて樹脂封止されるので封止部との密着性が向
上し、該ダウンボンディング部と封止部との剥離などを
防止することができる。(1) According to the present invention, since the down bonding portion is entirely sealed with resin, the adhesion to the sealing portion is improved, and peeling of the down bonding portion from the sealing portion is prevented. Can be.

【００５６】（２）また、本発明では、ダウンボンディ
ング部を屈折させることにより、該ダウンボンディング
部がダイボンドに用いられる接着材によって汚染される
ことを防止することができる。(2) In the present invention, by bending the down bonding portion, it is possible to prevent the down bonding portion from being contaminated by the adhesive used for die bonding.

【００５７】（３）さらに、本発明においては、上記
（１）、（２）により、半導体装置の接続信頼性を向上
することができる。(3) Further, in the present invention, the connection reliability of the semiconductor device can be improved by the above (1) and (2).

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態による半導体装置の説明
図である。FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention.

【図２】図１の半導体装置におけるダイパッドの断面図
である。FIG. 2 is a sectional view of a die pad in the semiconductor device of FIG. 1;

【図３】図１の半導体装置における製造工程の説明図で
ある。FIG. 3 is an explanatory diagram of a manufacturing process in the semiconductor device of FIG. 1;

【図４】図３に続く半導体装置の製造工程の説明図であ
る。FIG. 4 is an explanatory view of the semiconductor device manufacturing process following FIG. 3;

【図５】図４に続く半導体装置の製造工程の説明図であ
る。FIG. 5 is an explanatory view of the semiconductor device manufacturing process following FIG. 4;

【図６】図１の半導体装置における製造工程のフローチ
ャートである。FIG. 6 is a flowchart of a manufacturing process in the semiconductor device of FIG. 1;

【図７】本発明の他の実施の形態による半導体装置にお
けるダイパッドの屈折部、およびその近傍の拡大説明図
である。FIG. 7 is an enlarged explanatory view of a bending portion of a die pad and its vicinity in a semiconductor device according to another embodiment of the present invention.

【図８】本発明の他の実施の形態による半導体装置にお
けるダイパッドの一例を示す説明図である。FIG. 8 is an explanatory diagram showing an example of a die pad in a semiconductor device according to another embodiment of the present invention.

【図９】本発明の他の実施の形態による半導体装置にお
けるダイパッドの他の例を示す説明図である。FIG. 9 is an explanatory diagram showing another example of a die pad in a semiconductor device according to another embodiment of the present invention.

【図１０】本発明の他の実施の形態による半導体装置に
おけるダイパッドの一例を示す説明図である。FIG. 10 is an explanatory diagram showing an example of a die pad in a semiconductor device according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体装置 ２ ダイパッド ２ａ ダイパッド部 ２ｂ〜２ｅ ダウンボンディング部 ２ｂ1 〜２ｅ1 ダウンボンディング部 ２ｂ2 〜２ｅ2 ダウンボンディング部 ２ｂ3 〜２ｅ3 ダウンボンディング部 ３ タブ吊りリード ４ 接着材 ５ 半導体チップ ６ インナリード ７，７ａ ボンディングワイヤ（接続部材） ８ パッケージ（封止部） ９ 外部電極 １０ アウタリード Ｋ 屈折部REFERENCE SIGNS LIST 1 semiconductor device 2 die pad 2 a die pad portion 2 b to 2 e down bonding portion 2 b 1 to 2 e 1 down bonding portion 2 b 2 to 2 e 2 down bonding portion 2 b 3 to 2 e 3 down bonding portion 3 tab suspension lead 4 adhesive 5 semiconductor chip 6 inner Lead 7, 7a Bonding wire (connection member) 8 Package (sealing part) 9 External electrode 10 Outer lead K Refraction part

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 外部信号が入出力される複数の外部電極
が、半導体チップが樹脂封止されて形成された封止部の
実装面、および側面に露出して形成された半導体装置で
あって、 搭載面に前記半導体チップが搭載され、前記搭載面の反
対面が前記封止部の実装面から露出する四角形状のダイ
パッド部と、 前記ダイパッドの外周辺が外方に延在し、かつ前記外周
辺近傍が屈折した屈折部が設けられて前記封止部により
封止されたダウンボンディング部とからなるダイパッド
を備えたことを特徴とする半導体装置。1. A semiconductor device wherein a plurality of external electrodes for inputting and outputting external signals are exposed on a mounting surface and a side surface of a sealing portion formed by resin sealing a semiconductor chip. A square die pad portion on which the semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of the sealing portion; and an outer periphery of the die pad extends outward, and A semiconductor device comprising: a die pad provided with a refraction portion whose outer periphery and vicinity are bent and a down bonding portion sealed by the sealing portion. 【請求項２】 外部信号が入出力される複数の外部電極
が、半導体チップが樹脂封止されて形成された封止部の
実装面、および側面に露出して形成された半導体装置で
あって、 搭載面に前記半導体チップが搭載され、前記搭載面の反
対面が前記封止部の実装面から露出する四角形状のダイ
パッド部と、 前記ダイパッドの外周辺が外方に延在し、かつ前記外周
辺近傍が屈折した屈折部が設けられて前記封止部により
封止され、前記屈折部の両側に切り込みが形成されたダ
ウンボンディング部とからなるダイパッドを備えたこと
を特徴とする半導体装置。2. A semiconductor device wherein a plurality of external electrodes for inputting / outputting external signals are exposed on a mounting surface and a side surface of a sealing portion formed by resin-sealing a semiconductor chip. A square die pad portion on which the semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of the sealing portion; and an outer periphery of the die pad extends outward, and A semiconductor device, comprising: a die pad including a bent portion whose outer periphery is bent and sealed by the sealing portion, and a down bonding portion having cuts formed on both sides of the bent portion. 【請求項３】 外部信号が入出力される複数の外部電極
が、半導体チップが樹脂封止されて形成された封止部の
実装面、および側面に露出して形成された半導体装置で
あって、 搭載面に前記半導体チップが搭載され、前記搭載面の反
対面が前記封止部の実装面から露出する四角形状のダイ
パッド部と、 前記ダイパッドの外周辺が外方に延在し、かつ前記外周
辺近傍が屈折した屈折部が設けられて前記封止部により
封止され、前記屈折部にスリットが形成されたダウンボ
ンディング部とからなるダイパッドを備えたことを特徴
とする半導体装置。3. A semiconductor device in which a plurality of external electrodes for inputting and outputting external signals are exposed on a mounting surface and a side surface of a sealing portion formed by sealing a semiconductor chip with a resin. A square die pad portion on which the semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of the sealing portion; and an outer periphery of the die pad extends outward, and A semiconductor device, comprising: a die pad including a refraction portion whose outer periphery is bent and sealed by the sealing portion, and a down bonding portion having a slit formed in the refraction portion. 【請求項４】 半導体チップが搭載される搭載面の反対
面が封止部の実装面から露出する四角形状のダイパッド
部と前記ダイパッドの外周辺が外方に延在し、かつ前記
外周辺近傍が屈折した屈折部が設けられて前記封止部に
より封止されたダウンボンディング部とからなるダイパ
ッドが設けられ、前記ダイパッドの周辺部に配置され、
前記半導体チップの表面電極に対応する複数の電極部が
形成されたリードフレームを準備する工程と、 前記半導体チップと前記ダイパッド部とを接合する工程
と、 前記半導体チップの表面電極とこれに対応する前記電極
部、ならびに前記半導体チップの表面電極とこれに対応
する前記ダイパッド部とを接続部材により接続する工程
と、 前記半導体チップを封止樹脂によって覆うとともに、半
導体装置の実装面側に前記電極部と前記ダイパッド部と
を露出して樹脂モールドし、封止部を形成する工程と、 前記電極部の露出面、ならびに前記ダイパッド部の露出
面にはんだ皮膜を積層して形成する工程と、 前記電極部を前記リードフレームの枠部から分離し、外
部電極部を形成する工程とを有することを特徴とする半
導体装置の製造方法。4. A quadrangular die pad portion in which a surface opposite to a mounting surface on which a semiconductor chip is mounted is exposed from a mounting surface of a sealing portion, an outer periphery of the die pad extends outward, and a vicinity of the outer periphery. A die pad including a refraction portion in which a refraction portion is provided and a down bonding portion sealed by the sealing portion is provided, and a die pad is disposed around the die pad,
A step of preparing a lead frame having a plurality of electrode portions corresponding to the surface electrodes of the semiconductor chip; a step of bonding the semiconductor chip to the die pad portion; A step of connecting the electrode portion and a surface electrode of the semiconductor chip to the corresponding die pad portion by a connecting member; and covering the semiconductor chip with a sealing resin and the electrode portion on a mounting surface side of a semiconductor device. Forming a sealing portion by exposing the die pad portion and the die pad portion, forming a sealing portion, laminating a solder film on the exposed surface of the electrode portion, and the exposed surface of the die pad portion, Separating the lead portion from the frame portion of the lead frame to form an external electrode portion. 【請求項５】 搭載面に半導体チップが搭載され、前記
搭載面の反対面が前記封止部の実装面から露出する四角
形状のダイパッド部と前記ダイパッドの外周辺が外方に
延在し、かつ前記外周辺近傍が屈折した屈折部が設けら
れて前記封止部により封止され、前記屈折部の両側に切
り込みが形成されたダウンボンディング部とからなるダ
イパッドが設けられ、前記ダイパッドの周辺部に配置さ
れ、前記半導体チップの表面電極に対応する複数の電極
部が形成されたリードフレームを準備する工程と、 前記半導体チップと前記ダイパッド部とを接合する工程
と、 前記半導体チップの表面電極とこれに対応する前記電極
部、ならびに前記半導体チップの表面電極とこれに対応
する前記ダイパッド部とを接続部材により接続する工程
と、 前記半導体チップを封止樹脂によって覆うとともに、半
導体装置の実装面側に前記電極部と前記ダイパッド部と
を露出して樹脂モールドし、封止部を形成する工程と、 前記電極部の露出面、ならびに前記ダイパッド部の露出
面にはんだ皮膜を積層して形成する工程と、 前記電極部を前記リードフレームの枠部から分離し、外
部電極部を形成する工程とを有することを特徴とする半
導体装置の製造方法。5. A square die pad portion on which a semiconductor chip is mounted on a mounting surface, and a surface opposite to the mounting surface is exposed from a mounting surface of the sealing portion, and an outer periphery of the die pad extends outward. And a die pad including a down bonding portion provided with a bent portion having a bent portion near the outer periphery and sealed by the sealing portion, and cuts formed on both sides of the bent portion, and a peripheral portion of the die pad. Preparing a lead frame on which a plurality of electrode portions corresponding to the surface electrodes of the semiconductor chip are formed; joining the semiconductor chip and the die pad portion; and Connecting the corresponding electrode portion, the surface electrode of the semiconductor chip and the corresponding die pad portion by a connecting member, Covering the chip with a sealing resin, exposing the electrode portion and the die pad portion on the mounting surface side of the semiconductor device and performing resin molding to form a sealing portion, and an exposed surface of the electrode portion; and A step of forming a solder film on the exposed surface of the die pad portion by laminating; and a step of separating the electrode portion from a frame portion of the lead frame to form an external electrode portion. Production method.
JP2000358826A 2000-11-27 2000-11-27 Semiconductor device and method for manufacturing the same Pending JP2002164496A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227278A (en) * 2007-03-14 2008-09-25 Nec Electronics Corp Semiconductor device and its manufacturing method
WO2009013665A2 (en) * 2007-07-23 2009-01-29 Nxp B.V. A leadframe structure for electronic packages
JP2014143433A (en) * 2014-03-31 2014-08-07 Mitsubishi Electric Corp Semiconductor device
WO2015159526A1 (en) * 2014-04-17 2015-10-22 パナソニックＩｐマネジメント株式会社 Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227278A (en) * 2007-03-14 2008-09-25 Nec Electronics Corp Semiconductor device and its manufacturing method
WO2009013665A2 (en) * 2007-07-23 2009-01-29 Nxp B.V. A leadframe structure for electronic packages
WO2009013665A3 (en) * 2007-07-23 2009-03-26 Nxp Bv A leadframe structure for electronic packages
US8258611B2 (en) 2007-07-23 2012-09-04 Nxp B.V. Leadframe structure for electronic packages
JP2014143433A (en) * 2014-03-31 2014-08-07 Mitsubishi Electric Corp Semiconductor device
WO2015159526A1 (en) * 2014-04-17 2015-10-22 パナソニックＩｐマネジメント株式会社 Semiconductor device

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