JP2010165777A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expose a die pad from a sealing body of a die pad exposed type semiconductor device. <P>SOLUTION: The semiconductor device has the die pad 1c, a bus bar 1d disposed around the die pad 1c, a plurality of inner leads 1a disposed around the bus bar 1d, a semiconductor chip 2 mounted on an upper surface 1ca of the die pad 1c, a plurality of wires 4 for electrically connecting a plurality of electrode pads 2c of the semiconductor chip 2 to the plurality of inner leads 1a, the sealing body 3 for sealing the semiconductor chip 2 such that a lower surface 1cb of the die pad 1c is exposed, and a plurality of outer leads 1b exposed from the sealing body 3, wherein the bus bar 1d is located at a height between the inner leads 1a and a mounting surface 3b of the sealing body 3 such that the interval between an inner lead 1a and the bus bar 1d is equal to the interval between the bus bar 1d and the mounting surface 3b of the sealing body 3 or is larger than the interval between the bus bar 1d and the mounting surface 3b of the sealing body 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a die pad exposed semiconductor device.

  As a high heat dissipation type semiconductor package (semiconductor device), a die pad exposed type semiconductor package is known.

  As a die pad exposure type semiconductor package, for example, Japanese Patent Laid-Open No. 2000-91489 (Patent Document 1) describes a structure in which a semiconductor chip mounting plate (die pad) is exposed on the bottom surface of a package.

JP 2000-91489 A

  As semiconductor devices become more sophisticated, power consumption (drive power) of built-in semiconductor chips (hereinafter also simply referred to as chips) tends to increase, and the amount of heat generated from the semiconductor chips also increases. Therefore, various configurations using a heat sink or a thermal ball as a semiconductor package structure for improving heat dissipation have been studied. However, in such a configuration, it is necessary to use a new member, and it is difficult to reduce the manufacturing cost.

  Therefore, as a configuration that can ensure heat dissipation at a low price, for example, as shown in Patent Document 1, there is a QFP (Quad Flat Package) type semiconductor device in which a tab is exposed from the lower surface of a sealing body. Here, in the case of a QFP type semiconductor device, even if the mounting substrate expands and contracts in the horizontal direction due to the influence of heat when mounting the semiconductor device on the mounting substrate, the connection with the mounting substrate is made by the length of the outer lead. Since the stress generated in the part can be absorbed, high mounting reliability can be obtained at a low price.

  However, in the case of a QFP type semiconductor device, a semiconductor chip and a die pad (tab) incorporated in the sealing body are arranged at a substantially central portion in the thickness direction of the sealing body in consideration of a resin balance in the molding process. . Therefore, if the die pad is exposed from the lower surface of the sealing body, the amount of downset of the suspension lead formed integrally with the tab is increased, and the suspension lead is greatly extended, so that the strength of the suspension lead itself is reduced. The location of the die pad becomes unstable due to the resin filling pressure in the molding process.

  Therefore, the inventor of the present application studied a configuration in which the suspension lead that supports the die pad is bent in two stages as shown in Patent Document 1. At this time, not only the suspension lead but also a bridge bar (bus bar, section bar) is applied, and the bending portion is divided into two portions, the suspension lead and the bridge bar, to ensure the strength of the suspension lead against bending, The location of the die pad can be stabilized.

  As a result of the inventor's evaluation using such a lead frame, the following problems were newly discovered.

  First, a molding die used for forming a sealing body includes a cavity part in which a semiconductor chip is arranged, a gate part connected to the cavity part and serving as a path for supplying resin, and the gate part. An air vent part and a flow cavity part for exhausting the air in the cavity are provided in the part which is not present. In such a molding die, when the gate portion is formed only on one side (one of the upper die and the lower die) of the lead frame, a void is generated inside the formed sealing body. I understood it.

  This is due to the increase in the number of terminals (electrode pads) of the semiconductor chip as the functionality of the semiconductor device increases. That is, when the semiconductor chip and the leads are electrically connected via wires, the number of wires and leads increases in accordance with the increasing terminals. Further, when the outer size of the semiconductor device is reduced, the distance between adjacent wires and leads is also reduced, so that the gate (for example, the upper mold) provided on one side of the lead frame is changed to the other side (for example, It becomes difficult to supply resin toward the lower mold.

  Therefore, the inventor of the present application evaluated using a molding die in which gates are arranged on both sides of the lead frame.

  As a result, the die pad moves (lifts in the upper mold direction) due to the resin filling pressure, and the lower surface of the die pad is covered with the sealing body.

  This was found to be caused by the location of the bridge bar. That is, as shown in the patent document 1 or the QFP 30 of the comparative example of FIG. 31, the interval (T1) between the bus bar 1d (bridge bar) and the inner lead 1a is the distance between the bus bar 1d and the mounting surface 3b of the sealing body 3. When the distance is smaller than the interval (T2), it is found that the amount of resin supplied to the lower side of the bus bar 1d increases, and thus the die pad 1c is lifted through the bus bar 1d.

  Further, as shown in Patent Document 1 or the comparative example of FIG. 32, the semiconductor chip 2 is disposed on the die pad 1c so that the main surface of the semiconductor chip 2 is located at substantially the same height as the inner lead 1a. If so, the flow of the resin supplied through the lower gate is blocked by the side surface of the semiconductor chip 2. Thereafter, since the resin flows toward the wire 4, it was found that the die pad 1c on which the semiconductor chip 2 was mounted was lifted via the wire 4 (action F).

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of exposing a die pad from a sealing body in a die pad exposure type semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the heat dissipation of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a die pad having an upper surface and a lower surface opposite to the upper surface, a bus bar disposed around the die pad, a plurality of suspension leads formed with bent portions and connected to the bus bar, A plurality of leads arranged around the bus bar, a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface, are mounted on the upper surface of the die pad. And a semiconductor chip. Further, a plurality of wires that electrically connect the plurality of electrode pads and the plurality of leads of the semiconductor chip, respectively, a surface, a mounting surface opposite to the surface, and the surface and the mounting surface A seal that seals the bus bar, the semiconductor chip, and the plurality of wires such that a part of each of the plurality of leads is exposed from the side surface and the lower surface of the die pad is exposed. And a stationary body. Further, each of the plurality of suspension leads is formed with the bent portion, and in the thickness direction of the sealing body, the bus bar has an interval between the lead and the bus bar and the sealing between the bus bar and the sealing bar. It is arranged between the lead and the mounting surface of the sealing body so that it is the same as the spacing between the mounting surface of the body or larger than the spacing between the bus bar and the mounting surface of the sealing body. is there.

  Moreover, this invention includes the following processes. (A) a die pad having an upper surface and a lower surface opposite to the upper surface, a bus bar disposed around the die pad, a plurality of suspension leads formed with bent portions and connected to the bus bar, and the periphery of the bus bar And (b) a semiconductor chip having a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface. (C) electrically connecting the plurality of electrode pads and the plurality of leads of the semiconductor chip via a plurality of wires, respectively; Each of the plurality of leads is exposed from a side surface of the sealing body, and the lower surface of the die pad is exposed, so that the bus bar, the semiconductor chip, and the plurality of wires are exposed. Step to separate each of the plurality of leads is exposed from the (e) the sealing body, from the lead frame; a step of sealing with resin. Here, in the step (a), in the thickness direction of the lead frame, the interval between the lead and the bus bar is the same as the interval between the bus bar and the die pad, or larger than the interval between the bus bar and the die pad. The lead frame including the bus bar disposed between the lead and the upper surface of the die pad is prepared. The step (d) includes (d1) a first cavity and an upper mold having a first gate connected to the first cavity, a second cavity facing the first cavity, and the first gate. And a step of preparing a molding die provided with a lower die having a second gate connected to the second cavity; (d2) After the step (d1), the lead frame on which the semiconductor chip is mounted, A step of disposing between the first cavity of the upper die and the second cavity of the lower die; (d3) after the step (d2), the first gate and the second gate through the first gate; Supplying the resin into the first cavity and the second cavity.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in the die pad exposure type semiconductor device, the die pad can be reliably exposed from the sealing body.

It is a top view which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a side view showing the structure of the semiconductor device shown in FIG. 1. It is sectional drawing which shows the structure cut | disconnected along the AA line shown in FIG. It is sectional drawing which shows the structure cut | disconnected along the BB line shown in FIG. FIG. 2 is a partial plan view showing an example of a wiring state in the semiconductor device shown in FIG. 1. It is a fragmentary sectional view which shows the structure cut | disconnected along the AA line shown in FIG. FIG. 3 is a cross-sectional view showing a structure cut on a second suspension lead of the semiconductor device shown in FIG. 1. FIG. 2 is a partial cross-sectional view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 1. It is a fragmentary sectional view which shows an example of the structure at the time of die-bonding material application | coating in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure at the time of the pairing in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure at the time of wire bonding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure at the time of the resin molding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure after the resin molding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure after exterior plating in the assembly of the semiconductor device shown in FIG. FIG. 2 is a partial cross-sectional view illustrating an example of a structure after cut molding in the assembly of the semiconductor device illustrated in FIG. 1. FIG. 9 is an enlarged partial plan view showing an example of the structure of the lead frame shown in FIG. 8. FIG. 18 is an enlarged partial plan view showing the structure of a portion A shown in FIG. 17. It is an expanded partial sectional view which shows the structure cut | disconnected along the BB line of FIG. FIG. 2 is a partial plan view showing an example of a structure when die bonding is completed in the assembly of the semiconductor device shown in FIG. 1. It is a fragmentary sectional view which shows an example of the flow state of the resin at the time of the resin molding in the assembly of the semiconductor device shown in FIG. It is sectional drawing which shows the structure of the semiconductor device of the modification in Embodiment 1 of this invention. It is sectional drawing which shows an example of the mounting structure of the semiconductor device shown in FIG. It is a top view which shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. FIG. 25 is a side view showing the structure of the semiconductor device shown in FIG. 24. It is sectional drawing which shows the structure cut | disconnected along the AA line shown in FIG. It is sectional drawing which shows the structure cut | disconnected along the BB line shown in FIG. FIG. 25 is a cross-sectional view showing a structure cut on a second suspension lead of the semiconductor device shown in FIG. 24. FIG. 25 is a cross-sectional view showing an example of a first mounting structure of the semiconductor device shown in FIG. 24. FIG. 25 is a cross-sectional view showing an example of a second mounting structure of the semiconductor device shown in FIG. 24. It is sectional drawing which shows the structure of the semiconductor device of a comparative example. FIG. 32 is a cross-sectional view showing a resin flow state in the assembly of the semiconductor device shown in FIG. 31.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  Further, in the following embodiments, regarding constituent elements and the like, when “consisting of A”, “consisting of A”, “having A”, and “including A” are specifically indicated that only those elements are included. It goes without saying that other elements are not excluded except in the case of such cases. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a plan view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a side view showing the structure of the semiconductor device shown in FIG. 1, and FIG. 3 is taken along line AA shown in FIG. FIG. 4 is a cross-sectional view showing the structure cut along the line BB shown in FIG. 1. 5 is a partial plan view showing an example of a wiring state in the semiconductor device shown in FIG. 1, FIG. 6 is a partial sectional view showing a structure cut along the line AA shown in FIG. 5, and FIG. It is sectional drawing which shows the structure cut | disconnected on the 2nd suspension lead of the semiconductor device shown in FIG.

  The semiconductor device according to the first embodiment shown in FIGS. 1 to 7 is a resin-encapsulated and multi-pin semiconductor package. Here, the semiconductor device is exposed from the side surface 3c of the encapsulant 3 formed of resin. A QFP 5 in which a plurality of outer leads (external connection terminals) 1b are bent and formed in a gull wing shape will be described as an example. Furthermore, the QFP 5 has a structure in which the lower surface 1cb, which is a part of the die pad 1c on which the semiconductor chip 2 is mounted, is exposed from the sealing body 3 to improve heat dissipation. That is, the QFP 5 is a high heat dissipation type semiconductor package.

  The QFP 5 according to the first embodiment has a structure in which the lower surface 1 cb of the die pad 1 c is exposed from the mounting surface 3 b that is the back surface of the sealing body 3.

  A configuration of the QFP (semiconductor device) 5 shown in FIGS. 1 to 7 will be described. The QFP 5 includes a die pad 1c having an upper surface 1ca and a lower surface 1cb opposite to the upper surface 1ca, a bus bar 1d arranged around the die pad 1c, and a first bent portion (folded portion) 1f. A plurality of first suspension leads (suspending leads) 1e connected to the bus bar 1d and a plurality of leads arranged around the bus bar 1d are provided. The plurality of leads include an inner lead (a part of the lead) 1a disposed inside the sealing body 3 and an outer lead (lead lead) that is integrally connected to the inner lead 1a and exposed from the side surface 3c of the sealing body 3. Other part) 1b. That is, each lead includes an inner lead 1a and an outer lead 1b.

  The QFP 5 has a main surface 2a, a plurality of electrode pads 2c formed on the main surface 2a, and a back surface 2b opposite to the main surface 2a, and a semiconductor chip mounted on the upper surface 1ca of the die pad 1c. 2, a plurality of wires 4 that electrically connect a plurality of electrode pads 2 c of the semiconductor chip 2 and a plurality of inner leads (a part of the leads) 1 a, a bus bar 1 d, a semiconductor chip 2, and a plurality of wires 4 It has the sealing body 3 to seal.

  Further, each member will be described in detail. As shown in FIG. 3, the die pad (tab, chip mounting portion) 1c is a plate-shaped member, and has an upper surface (main surface, surface, chip mounting surface) 1ca, and upper surface. It has a lower surface (back surface, mounting surface) 1cb opposite to 1ca. The semiconductor chip 2 is bonded to the upper surface 1ca of the die pad 1c via an Ag paste 6 that is a conductive adhesive. 3 to 5, the outer size of the die pad 1c (the size of the upper surface 1ca) is larger than the outer size of the semiconductor chip 2 (the size of the main surface 2a or the back surface 2b). That is, the QFP 5 of the first embodiment has a large tab structure.

  As described above, by using the die pad 1c having the upper surface 1ca (or the lower surface 1cb) wider than the semiconductor chip 2, the heat dissipation effect from the die pad 1c can be enhanced, and the heat dissipation of the QFP 5 is improved. be able to.

  Further, as shown in FIG. 5, the bus bar (bridge bar, section bar) 1d is a lead material (plate-like member) formed in a ring shape, and is disposed around the semiconductor chip 2, and mainly the bus bar 1d. The resin balance is adjusted by dividing the supply amount of the resin between the upper side and the lower side.

  As shown in FIG. 3, the bus bar 1d has an upper surface (main surface, surface, chip mounting surface) 1da on the same side as the upper surface 1ca of the die pad 1c, and a lower surface (back surface) 1db opposite to the upper surface 1da. is doing. Furthermore, the bus bar 1d is arranged around the die pad 1c in a state of being connected to the die pad 1c through the second suspension lead 1g, as shown in FIGS. In other words, the die pad 1c is supported by the bus bar 1d via the second suspension lead 1g.

  The plurality of first suspension leads 1e connected to the bus bar 1d are opposite to the upper surface (main surface, surface, chip mounting surface) 1ea on the same side as the upper surface 1ca of the die pad 1c and the upper surface 1ea as shown in FIG. It has a lower surface (back surface) 1eb on the side, and is disposed on a diagonal line in the planar direction of the sealing body 3 as shown in FIG. That is, four first suspension leads 1e extend from the bus bar 1d on a diagonal line in the planar direction of the sealing body 3, and each first suspension lead 1e has a first in the vicinity of the bus bar 1d as shown in FIG. A bent portion 1f is formed.

  Further, as shown in FIG. 3, the plurality of inner leads 1a arranged around the bus bar 1d are an upper surface (main surface, surface, chip mounting surface) 1aa on the same side as the upper surface 1ca of the die pad 1c, and an upper surface 1aa. 5 is provided between the plurality of first suspension leads 1e as shown in FIG. That is, in each of the four regions cut by the four first suspension leads 1e arranged on the diagonal line in the planar direction of the sealing body 3 of the QFP 5, the plurality of inner leads 1a extend radially outward. Are arranged to be. Note that a plating layer (for example, silver plating) for improving the bonding with the wire 4 is formed at the bonding portion between the upper surface 1aa of each inner lead 1a and the wire 4. Further, a frame-shaped tape material 1i that suppresses flapping of each inner lead 1a during assembly of the QFP 5 is attached to the outside of the joint portion of the upper surface 1aa of the inner lead 1a with the wire 4 over the entire circumference. .

  Further, as shown in FIGS. 2 and 3, the sealing body 3 formed of a sealing resin has a front surface (main surface, upper surface) 3a and a mounting surface (back surface, lower surface) opposite to the surface 3a. 3b and the side surface 3c between the surface 3a and the mounting surface 3b, and the outer lead 1b that is a part of each of the plurality of leads is exposed from the side surface 3c of the sealing body 3. Further, the sealing body 3 seals the bus bar 1d, the semiconductor chip 2, and the plurality of wires 4 so that the lower surface 1cb of the die pad 1c is exposed from the mounting surface 3b.

  Further, each of the plurality of outer leads 1b exposed from the four side surfaces 3c of the sealing body 3 is directed from the surface 3a side of the sealing body 3 toward the mounting surface 3b side of the sealing body 3 outside the sealing body 3. Is bent. That is, each of the plurality of outer leads 1b integrally connected to each of the plurality of inner leads 1a is formed in a gull wing shape. This is to increase the electrical connection reliability between the outer lead 1b and the terminal 16a of the mother board 16 when the QFP 5 is mounted on the mother board (mounting board) 16, as shown in FIG. Further, as shown in FIG. 15, an outer plating 15 made of, for example, solder is formed on the surface of the outer lead 1b. In the mounting process of mounting the QFP 5 on the mother board 16, the outer lead 1b is electrically connected to the terminal 16a of the mother board 16 via a bonding material such as solder. For this reason, by providing exterior plating 15 made of solder on the surface of the outer lead 1b, it is possible to improve the bondability between the mother board 16 and the QFP 5 in the mounting process.

  The semiconductor chip 2 is made of, for example, silicon and the like. A plurality of semiconductor elements are formed on the main surface 2a, and the plurality of semiconductor elements constitute an integrated circuit. As shown in FIGS. 3 and 5, the planar shape of the semiconductor chip 2 is a quadrangle, and the plurality of electrode pads 2 c are arranged along the side of the main surface 2 a of the semiconductor chip 2. That is, since the QFP 5 is a multi-pin semiconductor package, the plurality of electrode pads 2c of the semiconductor chip 2 are arranged along all four sides of the main surface 2a, and correspond to these electrode pads 2c. Since the inner leads 1a are electrically connected by the wires 4, a plurality of wires 4 are densely arranged on each side of the main surface 2a of the semiconductor chip 2 (in FIG. 5, the wires 4 are Although only a few are described in the vicinity of the corner of the chip, a plurality of wires 4 are densely arranged near the center between the corners).

  The die pad 1c, the first suspension lead 1e, the bus bar 1d, the inner lead 1a, and the outer lead 1b are formed of a plate material such as a copper alloy having high heat dissipation. Moreover, the wire 4 is a gold wire, for example. Furthermore, the sealing body 3 is made of, for example, a thermosetting epoxy resin.

  In the QFP 5 of the first embodiment, as shown in FIG. 3, in the thickness direction of the sealing body 3, the bus bar 1 d has an interval (T 1) between the inner lead 1 a and the bus bar 1 d between the bus bar 1 d and the sealing body 3. It is the same as the interval (T2) between the mounting surface 3b (T1 = T2), or preferably (T1) is larger than the interval (T2) between the bus bar 1d and the mounting surface 3b of the sealing body 3 (T1> T2). ), The inner lead 1a and the mounting surface 3b of the sealing body 3 are disposed.

  That is, the distance (T1) between the lower surface 1ab of the inner lead 1a and the upper surface of the bus bar 1d (the surface facing the lower surface 1ab of the inner lead 1a) 1da is such that the lower surface 1db of the bus bar 1d and the mounting surface of the sealing body 3 (of the bus bar 1d It is the same as the distance (T2) between the lower surface 1db and the surface 3b (T1 = T2), or preferably (T1) is the distance (T2) between the lower surface 1db of the bus bar 1d and the mounting surface 3b of the sealing body 3 ) (T1> T2).

  Alternatively, in the thickness direction of the sealing body 3, the bus bar 1 d has the upper surface 1 da at the same position as the main surface 2 a of the semiconductor chip 2, or the upper surface 1 da of the bus bar 1 d has the main surface 2 a of the semiconductor chip 2 and the sealing body. 3 is disposed around the die pad 1c so as to be disposed at a height position between the three mounting surfaces 3b (G ≧ 0).

  In this way, the bus bar 1d is arranged such that (T1 = T2), preferably (T1> T2), or the upper surface 1da of the bus bar 1d is at the same position as the main surface 2a of the semiconductor chip 2, or the semiconductor chip 2 is arranged at a height between the main surface 2a of the sealing body 3 and the mounting surface 3b of the sealing body 3, thereby reducing the amount of resin supplied to the lower side of the bus bar 1d when the resin is filled in the resin molding process. Can do. In other words, as shown in FIG. 21, by increasing the amount of resin supplied to the upper side of the bus bar 1d during resin filling, the load for pressing the bus bar 1d downward can be increased.

  As a result, the bus bar 1d is pressed downward by the resin, and the die pad 1c supported by the bus bar 1d via the second suspension lead 1g is also pressed downward. As a result, the die pad 1 c is easily exposed to the mounting surface 3 b of the sealing body 3.

  That is, since the bus bar 1d is pressed downward by the resin when the resin is filled, the action of lifting the die pad 1c through the bus bar 1d can be reduced, and the lower surface 1cb of the die pad 1c is mounted on the mounting surface 3b of the sealing body 3. It becomes easy to expose and the die pad 1c can fully be exposed. As a result, the occurrence of resin flash burr can be suppressed.

  Further, since the bus bar 1d is disposed below the main surface 2a of the semiconductor chip 2, obstacles to the resin flow path can be reduced, and the resin filling property around the chip can be improved. .

  Since the QFP 5 of the first embodiment is multi-pin, the die pad 1c is lifted by a plurality of wires 4 via the semiconductor chip 2 and pulled in a direction that is difficult to be exposed from the mounting surface 3b of the sealing body 3. Therefore, the structure of the QFP 5 of the first embodiment that makes it easy to expose the die pad 1c from the mounting surface 3b of the sealing body 3 is very effective.

  In the QFP 5, as shown in FIG. 3, the semiconductor chip 2 has a main surface 2a between the upper surface 1aa of the inner lead 1a and the upper surface 1ca of the die pad 1c or the inner surface in the thickness direction of the sealing body 3. Arranged between the lower surface 1ab of the lead 1a and the upper surface 1ca of the die pad 1c, the main surface 2a is mounted on the die pad 1c so as to be positioned below the inner lead 1a.

  As a result, the die pad 1c is lifted by the plurality of launched wires 4 via the semiconductor chip 2 by the launch wire bonding from the chip side to the inner lead side, and from the mounting surface 3b of the sealing body 3. An action (arrow F shown in FIG. 32) that is difficult to be exposed occurs. This means that the larger the number of wires 4 due to the multi-pins, the greater the magnitude of the action.

  However, in the QFP 5 of the first embodiment, even in the multi-pin structure, the bus bar 1d is pressed downward by the resin, and the die pad 1c supported by the bus bar 1d via the second suspension lead 1g is also lower. Since the die pad 1c is lifted by the plurality of wires 4 via the semiconductor chip 2, it is possible to suppress the action of being difficult to be exposed from the sealing body 3.

  Thereby, the lower surface 1cb of the die pad 1c is easily exposed to the mounting surface 3b of the sealing body 3, and the die pad 1c can be sufficiently exposed. As a result, the occurrence of resin flash burrs can be suppressed as described above.

  In the QFP 5 of the first embodiment, as shown in FIG. 17, the planar shape of the die pad 1c has a pair of first sides 1cc facing each other and a pair of second sides facing each other and intersecting the first side 1cc. It consists of a quadrilateral with side 1cd.

  Furthermore, the planar shape of the bus bar 1d includes a third side 1dc aligned with the first side 1cc of the die pad 1c, a fourth side 1dd aligned with the second side 1cd of the die pad 1c, and a third side 1dc and a fourth side 1dd. It has an octagonal frame shape having a fifth side 1de positioned therebetween, and each of the four first suspension leads 1e is connected to the fifth side 1de of the bus bar 1d. At that time, the fifth side 1de of the bus bar 1d extends in a direction perpendicular to the extending direction of the first suspension lead 1e. That is, the bus bar 1d has an octagonal frame shape, and the fifth side 1de, which is a joint portion with each of the four first suspension leads 1e, extends in a direction perpendicular to the extending direction of the first suspension leads 1e. Exist. In other words, the bus bar 1d has an octagonal shape formed by chamfering each of the four corner portions with the fifth side 1de in a quadrangle composed of the third side 1dc facing each other and the fourth side 1dd facing each other.

  Since the bus bar 1d has a chamfered shape with the fifth side 1de at the joint portion with each first suspension lead 1e, the stress in the bus bar 1d can be relieved.

  The bus bar 1d is connected to the die pad 1c via a plurality of second suspension leads 1g arranged between the third side 1dc and the fourth side 1dd and the die pad 1c, and a plurality of second suspension leads. A second bent portion 1h is formed in each of 1g.

  That is, the second suspension lead 1g formed with the second bent portion 1h, which is a two-step bending offset, is connected to the third side 1dc and the fourth side 1dd of the bus bar 1d, respectively. In addition, it is preferable that a plurality of offset portions for the two-stage bending are provided on one side of the bus bar 1d. In the QFP 5 of the first embodiment, each side of the third side 1dc and the fourth side 1dd of the bus bar 1d. , Two second suspension leads 1g are provided, and a second bent portion 1h is formed in each.

  Thereby, since the location of the die pad 1c can be stabilized, the problem that a resin flash burr is formed on the surface exposed from the sealing body 3 in the die pad 1c can be suppressed. As a result, the heat dissipation of the semiconductor device can be improved.

  The die pad 1c is not connected to the second suspension lead 1g at the corner. In other words, the corner portion of the die pad 1 c is in close contact with a part of the sealing body 3. That is, in the QFP 5 according to the first embodiment, the corner portion of the rectangular die pad 1c is not connected to the suspension lead at all and is in a free state.

  Therefore, since there is no suspension lead and offset (bending) in the corner portion, even if distortion is generated by the first suspension lead 1e, this distortion can be released without being transmitted to the die pad 1c. Further, in the QFP 5, since the frame-shaped bus bar 1d disposed around the semiconductor chip 2 is provided, the contact area between the resin and the lead portion is increased, and the thermal strain of the resin can be dispersed. Thereby, since peeling of die pad 1c and resin can be reduced, the problem (resin crack) which a crack generate | occur | produces in the sealing body 3 can be suppressed.

  In the QFP 5, on the side surface 3c of the sealing body 3, as shown in FIG. 14, the first gate resin 3d formed on the upper surface side of the first suspension lead 1e and the upper surface of the first suspension lead 1e Is provided with a second gate resin 3e formed on the lower surface side which is the opposite side.

  That is, in the QFP 5 according to the first embodiment, the sealing body 3 is formed by injecting resin from the gates of the molding dies on both the upper side and the lower side of the first suspension lead 1e in the assembly molding process. Is. This is because the QFP 5 has a multi-pin structure, so if the resin is injected only from the upper side, the dense wires 4 become walls and the resin does not flow under the first suspension lead 1e, and many voids are formed. However, the formation of voids can be prevented by injecting resin from the upper and lower gates.

  Next, assembly of the semiconductor device (QFP5) of the first embodiment will be described.

  8 is a partial cross-sectional view showing an example of the structure of a lead frame used for assembling the semiconductor device shown in FIG. 1, and FIG. 9 is a partial cross-sectional view showing an example of the structure when a die bond material is applied in assembling the semiconductor device shown in FIG. FIG. 10 and FIG. 10 are partial cross-sectional views showing an example of the structure when attaching the semiconductor device shown in FIG. 11 is a partial cross-sectional view showing an example of the structure during wire bonding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 12 is a partial cross-sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. 13 is a partial cross-sectional view showing an example of a structure during resin molding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 14 is a partial cross-sectional view showing an example of the structure after resin molding in the assembly of the semiconductor device shown in FIG. FIG. 15 is a partial cross-sectional view showing an example of the structure after exterior plating in the assembly of the semiconductor device shown in FIG. 1, and FIG. 16 is a partial cross-sectional view showing an example of the structure after cut forming in the assembly of the semiconductor device shown in FIG. 17 is an enlarged partial plan view showing an example of the structure of the lead frame shown in FIG. 8, FIG. 18 is an enlarged partial plan view showing the structure of part A shown in FIG. 17, and FIG. 19 is a BB line in FIG. It is an expanded partial sectional view which shows the structure cut | disconnected along. 20 is a partial plan view showing an example of a structure when die bonding is completed in the assembly of the semiconductor device shown in FIG. 1, and FIG. 21 is an example of a resin flow state during resin molding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view shown.

  First, as shown in FIGS. 8 and 17 to 19, a die pad 1c having an upper surface 1ca and a lower surface 1cb opposite to the upper surface 1ca, a bus bar 1d arranged around the die pad 1c, and a first bent portion A plurality of first suspension leads 1e formed with 1f and connected to the bus bar 1d, a plurality of inner leads 1a arranged around the bus bar 1d, and a plurality of outer leads 1b connected to the plurality of inner leads 1a, respectively. A lead frame 1 is prepared. The lead frame 1 is made of, for example, a plate material such as a copper alloy having high heat dissipation. The die pad 1c and the bus bar 1d are connected via a plurality of second suspension leads 1g. That is, the die pad 1c is supported by the bus bar 1d via the plurality of second suspension leads 1g. Further, each second suspension lead 1g is formed with a second bent portion 1h, and the first bent portion 1f of the first suspension lead 1e and the second bent portion 1h of the second suspension lead 1g The entire suspension lead in the frame 1 is bent in two stages.

  Further, as shown in FIG. 19, the lead frame 1 used for assembling the QFP 5 according to the first embodiment has a distance (T1) between the lower surface 1ab of the inner lead 1a and the upper surface 1da of the bus bar 1d in the thickness direction. Is the same as the interval (T3) between the lower surface 1db of the bus bar 1d and the lower surface 1cb of the die pad 1c (T1 = T3), or larger than the interval (T3) between the lower surface 1db of the bus bar 1d and the lower surface 1cb of the die pad 1c (T1>). T3), a bus bar 1d is provided between the inner lead 1a and the upper surface 1ca of the die pad 1c.

  Thereafter, die bonding is performed as shown in FIGS. Here, the semiconductor chip 2 having the main surface 2a, the plurality of electrode pads 2c formed on the peripheral portion of the main surface 2a, and the back surface 2b opposite to the main surface 2a is mounted on the upper surface 1ca of the die pad 1c. .

  First, as shown in FIG. 9, a conductive Ag paste 6 as a die bond material (adhesive) is applied from the discharge nozzle 7 onto the upper surface 1ca of the die pad 1c. Thereafter, as shown in FIG. 10, the semiconductor chip 2 sucked and conveyed by the collet 8 is placed on the upper surface 1ca of the die pad 1c, and the semiconductor chip 2 is placed on the upper surface 1ca of the die pad 1c with the main surface 2a facing upward. It adheres via Ag paste 6.

  Thereafter, wire bonding is performed as shown in FIGS. Here, a plurality of electrode pads 2c (see FIG. 3) of the semiconductor chip 2 and a plurality of inner leads 1a corresponding thereto are electrically connected via a plurality of wires 4, respectively.

  First, the bonding stage 10 provided with a heat source is prepared. Then, as shown on the left side of FIG. 11, the lead frame 1 on which the semiconductor chip 2 is mounted on the die pad 1c is placed on the bonding stage 10 and heated (warmed).

  Next, as shown on the right side of FIG. 11, the heated die-bonded lead frame 1 is arranged on the bonding stage so that the die pad 1 c and the bus bar 1 d are positioned in the groove of the bonding stage 10. In a state where the lead pressing jig 11 holds the tape material 1i attached to the inner lead 1a or between the tape material 1i and the tip of the inner lead 1a (or the portion to which the wire 4 is connected). Wire bonding is performed. In this way, the inner lead 1a has a defect in which the tip of the inner lead 1a moves (flutters) by pressing the lead pressing jig 11 as close as possible to the portion to which the wire 4 is connected. Can be suppressed. Further, since the lead frame 1 and the semiconductor chip 2 are heated in advance before connecting the wires 4, it is possible to shorten the time and perform wire bonding. At the time of wire bonding, the wire 4 (for example, a gold wire) is guided by the capillary 9 as a bonding tool, and the electrode pad 2c of the semiconductor chip 2 and the upper surface 1aa of the inner lead 1a are wired as shown in FIG. 4 for electrical connection.

  Thereafter, as shown in FIGS. 13 and 21, resin molding (resin sealing) is performed. Here, the bus bar 1d is such that each outer lead (part) 1b of the plurality of leads is exposed from the side surface 3c of the sealing body 3 and the lower surface 1cb of the die pad 1c is exposed to the mounting surface 3b of the sealing body 3. The semiconductor chip 2 and the plurality of wires 4 are sealed with a sealing resin (resin) 13.

  First, an upper mold 12a having a first cavity 12aa and a first gate 12ab connected to the first cavity 12aa, a second cavity 12ba facing the first cavity 12aa, and a first cavity 12ab, and a second cavity A resin molding die (molding die) 12 including a lower die 12b having a second gate 12bb connected to 12ba is prepared. Although not shown, the planar shape of the cavities (first cavity 12aa and second cavity 12ba) is a rectangular shape (in this embodiment, a quadrangle), and the gates (first gate 12ab and second gate 12bb) are , Formed at the corners of the cavity. Further, an air vent or a flow cavity for discharging air remaining in the cavity is provided in a portion where the gates (first gate 12ab and second gate 12bb) are not formed (in this embodiment, other corners). However, it is formed so as to be connected to the cavity.

  As shown in FIG. 21, the upper mold 12a of the resin mold 12 has a first parting surface 12ac that contacts the upper surface 1j of the lead frame 1, while the lower mold 12b is formed of a lead frame. 2 has a second parting surface 12bc that comes into contact with the lower surface 1k.

  Here, although not shown, in the lead frame 1 before being placed in the resin molding die 12, the distance (bending depth) from each of the plurality of inner leads 1a to the die pad 1c is from the second parting surface 12bc. It is formed larger than the interval (depth) to the bottom surface 12bd of the second cavity 12ba (for example, it is formed larger by about 50 μm).

  Thereafter, as shown in FIGS. 13 and 21, the lead frame 1 on which the semiconductor chip 2 is mounted is attached to the upper mold 12a so that the semiconductor chip 2 is positioned between the first cavity 12aa and the second cavity 12ba. It arrange | positions between 1st cavity 12aa and 2nd cavity 12ba of the lower mold | type 12b, and the mold clamping (clamp) of the resin molding metal mold | die 12 is performed. At this time, the distance (bending depth) from the lower surface 1ab of each of the plurality of inner leads 1a to the lower surface 1cb of the die pad 1c is the distance (depth) from the second parting surface 12bc to the bottom surface 12bd of the second cavity 12ba. Therefore, the lower surface 1cb of the die pad 1c abuts against the bottom surface 12bd of the second cavity 12ba and is in a reliable contact state.

  Then, with the bottom surface 12bd of the second cavity 12ba in contact with the bottom surface 1cb of the die pad 1c, the first cavity 12aa and the second cavity 12ba are brought into contact with each other through the first gate 12ab and the second gate 12bb, as shown in FIG. As shown, a sealing resin 13 is supplied. At that time, as shown in the resin filling direction 14a in FIG. 13, by injecting resin from the upper and lower gates (first gate 12ab and second gate 12bb) of the lead frame 1, It is possible to prevent voids from being formed on the side (under the dense wires 4). That is, since the QFP 5 has a multi-pin structure, when the resin is injected only from the upper gate (first gate 12ab), the dense wires 4 become walls and the resin does not flow into the lower side of the lead frame 1. Although many voids are formed, the formation of voids can be prevented by injecting resin from the upper and lower gates.

  By injecting resin from the upper and lower gates, the first gate resin 3d is formed on the upper side of the first suspension lead 1e as shown in FIG. 14, while the second gate resin 3e is also formed on the lower side. .

  Further, the resin is injected into the first cavity 12aa and the second cavity 12ba in a state where the lower surface 1cb of the die pad 1c is brought into contact with the bottom surface 12bd of the second cavity 12ba, so that the die pad 1c is cured after the resin is cured. The lower surface 1cb of the sealing member 3 can be reliably exposed to the mounting surface 3b.

  Furthermore, since the lower surface 1cb of the die pad 1c can be reliably exposed to the mounting surface 3b of the sealing body 3, the formation of a resin flash burr on the lower surface 1cb of the die pad 1c can be extremely reduced.

  Therefore, in the assembly of the QFP 5 according to the first embodiment, it is possible to eliminate the deburring process after the resin molding. Thereby, after resin molding, dam cutting can be performed, and then the exterior plating 15 shown in FIG. 15 can be applied. That is, after resin molding, the resin outflow prevention dam 1m shown in FIG. 18 between the outer leads 1b can be cut, and the exterior plating 15 can be applied after the dam 1m is cut. That is, dam cutting can be performed after resin molding and before the coating process of exterior plating 15, and foreign matters generated by dam cutting can be removed by washing during the plating process. Moreover, when the lead frame 1 made of copper alloy is used, plating can be applied to the cut surface by dam cutting, so that oxidation of the cut surface can be suppressed. However, the dam cutting may be performed in the cutting forming process after the coating process of the exterior plating 15 without performing the dam cutting before the coating process of the exterior plating 15.

  Note that a small amount of resin flash burr formed on the lower surface 1cb of the die pad 1c may be removed by forming an electric field in the exterior plating application process. The deburring performed by applying an electric field in the exterior plating coating process is weaker than deburring such as high-pressure cleaning, but in the assembly of the QFP 5 of the first embodiment, the resin flash formed on the lower surface 1cb of the die pad 1c Since the amount of burrs is very small, it can be removed even by deburring in the exterior plating application process.

  When Pd plating (advance plating) is used as the exterior plating 15, the exterior plating 15 is not necessary.

  Thereafter, as shown in FIG. 16, each of the plurality of outer leads 1b exposed from the sealing body 3 is separated from the lead frame 1 and bent into a gull wing shape to complete the assembly of the QFP 5.

  In the assembly of the QFP 5 according to the first embodiment, the bus bar 1d in the QFP 5 has an interval (T1) between the inner lead 1a and the bus bar 1d (T2) between the bus bar 1d and the mounting surface 3b of the sealing body 3 (T2). T1 = T2), preferably (T1> T2), or the upper surface 1da of the bus bar 1d is at the same position as the main surface 2a of the semiconductor chip 2 or sealed with the main surface 2a of the semiconductor chip 2 By disposing it between the mounting surface 3b of the stationary body 3, the amount of resin supplied to the upper side of the bus bar 1d can be reduced as shown in the resin flow direction 14b during resin filling in the resin molding step of FIG. The load (P2, P3) for pressing the bus bar 1d downward can be increased.

  As a result, the die pad 1c supported by the bus bar 1d is also pressed downward (load P1) via the second suspension lead 1g, so that the die pad 1c is easily exposed to the mounting surface 3b of the sealing body 3 and sealed. The body 3 can be reliably exposed.

  Next, a semiconductor device of a modification of the first embodiment shown in FIG. 22 will be described.

  FIG. 22 is a sectional view showing the structure of a semiconductor device according to a modification of the first embodiment of the present invention. The semiconductor device of the modification shown in FIG. 22 is a QFP 20 having the same bus bar 1d as the QFP 5 shown in FIG. 1, but in this QFP 20, the bus bar 1d has an upper surface 1da inclined with respect to the planar direction. It is disposed at a height between the inner lead 1 a and the mounting surface 3 b of the sealing body 3. In the structure shown in FIG. 22, in the planar direction of the frame-shaped bus bar 1d, the inner side is inclined so as to be higher than the outer side, but on the contrary, the outer side is inclined so as to be higher than the inner side. Also good.

  The other structure of the QFP 20 is the same as that of the QFP 5 shown in FIG.

  According to the modified QFP 20, the load for pressing the bus bar 1d downward by the resin can be further increased, and as a result, the load for pressing the die pad 1c downward can be further increased. As a result, the die pad 1 c can be more easily exposed on the mounting surface 3 b of the sealing body 3 and can be more reliably exposed from the sealing body 3.

  Note that other effects obtained by the modified QFP 20 are the same as those of the QFP 5 shown in FIG.

  Next, the mounting structure of the QFP 5 according to the first embodiment will be described.

  FIG. 23 is a cross-sectional view showing an example of the mounting structure of the semiconductor device (QFP5) shown in FIG. 1, and shows the mounting structure of QFP5 in which the lower surface 1cb of the die pad 1c is exposed from the mounting surface 3b of the sealing body 3. . In this mounting structure, the outer lead 1b which is an external connection terminal of the QFP 5 is electrically connected to the terminal 16a formed on the main surface 16c of the mother board 16 which is the mounting substrate via the solder 19 and is sealed. The lower surface 1 cb of the die pad 1 c exposed from the mounting surface 3 b of the body 3 is electrically connected to a wide (large area) pattern (electrode pad 16 b) formed on the main surface 16 c of the mother board 16 via the solder 19. Yes.

  In the QFP 5 of the first embodiment, the lower surface 1cb of the die pad 1c can be surely exposed to the mounting surface 3b of the sealing body 3, and therefore, the back surface side of the QFP 5 is used for heat dissipation. By connecting the lower surface 1cb and the wide electrode pad 16b of the mother board 16 via the solder 19, the heat dissipation of the QFP 5 can be greatly enhanced.

(Embodiment 2)
24 is a plan view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention, FIG. 25 is a side view showing the structure of the semiconductor device shown in FIG. 24, and FIG. 26 is taken along the line AA shown in FIG. 27 is a sectional view showing the structure cut along the line, FIG. 27 is a sectional view showing the structure cut along the line BB shown in FIG. 24, and FIG. 28 is cut on the second suspension lead of the semiconductor device shown in FIG. It is sectional drawing which shows a structure.

  The semiconductor device of the second embodiment shown in FIG. 24 to FIG. 28 has a bus bar 1d and a part of the die pad 1c exposed from the sealing body 3 in the same manner as the QFP 5 of the first embodiment. The QFP 21 has a plurality of outer leads 1b exposed from each of the four side surfaces 3c of the sealing body 3. The difference between the QFP 21 of the second embodiment and the QFP 5 of the first embodiment is that the die pad 1 c is exposed on the surface 3 a side of the sealing body 3. That is, in the QFP 21, the back surface 1cf (the lower surface 1cb in the case of QFP5) opposite to the chip mounting side surface (main surface 1ce) of the die pad 1c is exposed from the surface 3a of the sealing body 3.

  As shown in FIG. 23, if there is a space for forming a wide (large area) pattern (electrode pad 16 b) on the surface of the mother board 16, the back surface 1 cf of the die pad 1 c is exposed from the mounting surface 3 b of the sealing body 3. In addition, it is possible to improve heat dissipation by connecting with a pattern formed on the mother board 16. However, when there is no space for forming such a pattern in the mother board 16, it is preferable to expose the die pad 1c to the surface 3a side of the sealing body 3 as in the QFP 21 of the second embodiment.

  Thereby, it becomes possible to attach a heat sink etc. to the die pad 1c exposed to the surface side, and it can improve the heat dissipation of a semiconductor device.

  Here, FIG. 29 is a sectional view showing an example of the first mounting structure of the semiconductor device shown in FIG. 24, and FIG. 30 is a sectional view showing an example of the second mounting structure of the semiconductor device shown in FIG. Both show a structure for further improving the heat dissipation of the QFP 21.

  In the mounting structure shown in FIG. 29, a heat spreader (heat radiating plate) 17 is arranged on the surface 3a of the sealing body 3 of the QFP 21 mounted on the mother board 16 via the solder 19, and the surface 3a of the sealing body 3 is arranged. The die pad 1 c exposed from is connected to the heat spreader 17 through the solder 19.

  In the mounting structure shown in FIG. 30, a heat sink (heat radiating plate) 18 is arranged on the surface 3 a of the sealing body 3 of the QFP 21 mounted on the mother board 16 via the solder 19. The die pad 1 c exposed from the surface 3 a is connected to the heat sink 18 via the solder 19.

  In the mounting structure of the QFP 21 shown in FIG. 29 and FIG. 30, the heat spreader 17 and the heat sink 18 such as the heat spreader 17 and the heat sink 18 are connected to the die pad 1c exposed on the surface 3a of the sealing body 3 of the QFP 21, thereby sealing. The heat dissipation of the QFP 21 can be further improved by utilizing the surface side of the stationary body 3.

  In the QFP 21 of the second embodiment, the semiconductor chip 2 is bonded to the main surface 1ce of the die pad 1c with the main surface 2a of the semiconductor chip 2 facing downward (the mounting surface 3b of the sealing body 3). A bus bar 1 d is arranged around the semiconductor chip 2. Therefore, the wire loops of the plurality of wires 4 that connect the electrode pads 2c formed on the main surface 2a and the inner leads 1a are formed downward. Thus, the die pad 1c is pulled by the plurality of wires 4 through the semiconductor chip 2 toward the lower side of the package. That is, the die pad 1 c is pulled in a direction that is difficult to be exposed on the surface 3 a of the sealing body 3.

  In the QFP 21 according to the second embodiment, the semiconductor chip 2 is bonded to the main surface 1ce of the die pad 1c with the main surface 2a of the semiconductor chip 2 facing downward (the mounting surface 3b of the sealing body 3). . Therefore, the die pad 1 c is pulled toward the lower side (mounting surface 3 b) of the sealing body 3 due to the influence of the weight of the semiconductor chip 2.

  For the reasons described above, between the back surface 1cf of the die pad 1c to which the semiconductor chip 2 is bonded via the Ag paste (adhesive) 6, and the surface (bottom surface) of the first cavity 12aa formed in the upper mold 12a. There is a possibility that a gap is formed in the back surface 1cf of the die pad 1c and the sealing body 3 covers the back surface 1cf.

  However, also in the QFP 21, as shown in FIG. 26, in the thickness direction of the sealing body 3, the bus bar 1d has an interval (T1) between the inner lead 1a and the bus bar 1d and the surface 3a of the bus bar 1d and the sealing body 3. (T1 = T2), preferably, the inner (T1) is larger than the interval (T2) between the bus bar 1d and the surface 3a of the sealing body 3 (T1> T2). It is arranged between the lead 1 a and the surface 3 a of the sealing body 3.

  That is, the distance (T1) between the upper surface 1aa of the inner lead 1a and the lower surface of the bus bar 1d (the surface facing the upper surface 1aa of the inner lead 1a) 1db is equal to the upper surface 1da of the bus bar 1d and the surface of the sealing body 3 (upper surface of the bus bar 1d). (Surface facing 1da) is equal to the interval (T2) from 3a (T1 = T2), preferably (T1) is from the interval (T2) between the upper surface 1da of the bus bar 1d and the surface 3a of the sealing body 3 Large (T1> T2).

  Alternatively, in the thickness direction of the sealing body 3, the bus bar 1 d has the lower surface 1 db at the same position as the main surface 2 a of the semiconductor chip 2, or the lower surface 1 db of the bus bar 1 d has the main surface 2 a of the semiconductor chip 2 and the sealing body. 3 is disposed around the die pad 1c so as to be disposed at a height between the surface 3a and the surface 3a (G ≧ 0).

  Thus, the bus bar 1d is arranged so as to satisfy (T1 = T2), preferably (T1> T2), or the lower surface 1db of the bus bar 1d is at the same position as the main surface 2a of the semiconductor chip 2, or the semiconductor chip 2 between the main surface 2a of the sealing member 3 and the surface 3a of the sealing body 3, so that the upper side of the bus bar 1d (between the bus bar 1d and the surface 3a of the sealing body 3) when the resin is filled in the resin molding process. The amount of resin supplied to the can be reduced. In other words, by increasing the amount of resin supplied to the lower side of the bus bar 1d when filling the resin, the load for pressing the bus bar 1d upward can be increased.

  As a result, the bus bar 1d is pressed upward by the resin, and the die pad 1c supported by the bus bar 1d via the second suspension lead 1g is also pressed upward. As a result, the die pad 1 c is easily exposed on the surface 3 a of the sealing body 3.

  That is, since the bus bar 1d is pressed upward by the resin when the resin is filled, the action of pulling the die pad 1c downward through the bus bar 1d can be reduced, and the back surface 1cf of the die pad 1c can be reduced to the front surface 3a of the sealing body 3. Can be easily exposed, and the die pad 1c can be sufficiently exposed. As a result, the occurrence of resin flash burrs can also be suppressed in the QFP 21 of the second embodiment.

  The other structure of QFP 21 according to the second embodiment and the other effects obtained by QFP 21 are the same as those of QFP 5 according to the first embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first and second embodiments, the case where the semiconductor device (QFP 5, 20, 21) has a large tab structure so as to increase the exposed area of the die pad 1c in consideration of the heat dissipation has been described. The semiconductor device is not limited to the large tab structure, and may have a small tab structure in which the upper surface 1ca (or the main surface 1ce) of the die pad 1c is smaller than that of the semiconductor chip 2.

  In the second embodiment, in the resin molding process, the amount of resin supplied to the upper side of the bus bar 1d (between the bus bar 1d and the surface 3a of the sealing body 3) during resin filling can be reduced. Although not shown, the resin molding process has been described in a state where the back surface 1cf of the die pad 1c is in contact with the surface (bottom surface) of the first cavity 12aa formed in the upper mold 12a. As described above, the resin molding step may be performed in a state where the lead frame 1 is turned upside down and the back surface 1cf of the die pad 1c is in contact with the surface (bottom surface) 12bd of the second cavity 12ba formed in the lower mold 12b. . In this case, in the molding process of the outer lead 1b exposed from the side surface 3c of the sealing body 3 after forming the sealing body 3, the direction opposite to that of the first embodiment (the sealing body 3 in which the die pad 1c is not exposed). Bend in the direction toward the surface. Thereby, when the semiconductor chip 2 having a large outer size is mounted on the die pad 1c, the self-weight of the semiconductor chip 2 can be used to further improve the adhesion between the back surface 1cf of the die pad 1c and the bottom surface of the cavity.

  The present invention is suitable for a high heat dissipation type electronic device.

1 Lead frame 1a Inner lead (part of lead)
1aa Upper surface 1ab Lower surface 1b Outer lead (other part of lead)
1c Die pad (tab, chip mounting part)
1ca upper surface (main surface, surface, chip mounting surface)
1cb bottom surface (back surface, mounting surface)
1cc 1st side 1cd 2nd side 1ce Main surface 1cf Back surface 1d Bus bar (bridge bar, section bar)
1da upper surface (main surface, surface, chip mounting surface)
1db bottom (back)
1dc 3rd side 1dd 4th side 1de 5th side 1e 1st suspension lead (suspension lead)
1ea Upper surface 1eb Lower surface 1f 1st bending part (bending part)
1g 2nd suspension lead 1h 2nd bending part (bending part)
1i Tape material 1j Upper surface 1k Lower surface 1m Dam 2 Semiconductor chip 2a Main surface 2b Back surface 2c Electrode pad 3 Sealing body 3a Surface (main surface, upper surface)
3b Mounting surface (back, bottom)
3c Side surface 3d First gate resin 3e Second gate resin 4 Wire 5 QFP (semiconductor device)
6 Ag paste (adhesive)
7 Discharge nozzle 8 Collet 9 Capillary 10 Bonding stage 11 Lead holding jig 12 Resin molding die (molding die)
12a Upper mold 12aa First cavity 12ab First gate 12ac First parting surface 12b Lower mold 12ba Second cavity 12bb Second gate 12bc Second parting surface 12bd Bottom surface 13 Sealing resin (resin)
14a Filling direction 14b Resin flow direction 15 Exterior plating 16 Motherboard (mounting board)
16a Terminal 16b Electrode pad 16c Main surface 17 Heat spreader (heat sink)
18 Heat sink
19 Solder 20 QFP (Semiconductor Device)
21 QFP (semiconductor device)
30 QFP

Claims (16)

A die pad having an upper surface and a lower surface opposite to the upper surface;
A bus bar disposed around the die pad;
A plurality of suspension leads formed with bent portions and connected to the bus bar;
A plurality of leads disposed around the bus bar;
A semiconductor chip having a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface, and mounted on the upper surface of the die pad;
A plurality of wires that electrically connect the plurality of electrode pads and the plurality of leads of the semiconductor chip, and
A front surface, a mounting surface opposite to the front surface, and a side surface between the front surface and the mounting surface, each of the plurality of leads is exposed from the side surface, and the lower surface of the die pad is A sealing body for sealing the bus bar, the semiconductor chip, and the plurality of wires so as to be exposed;
Including
Each of the plurality of suspension leads is formed with the bent portion,
In the thickness direction of the sealing body, the bus bar has the same interval between the lead and the bus bar as the interval between the bus bar and the mounting surface of the sealing body, or the mounting surface of the bus bar and the sealing body. The semiconductor device is disposed between the lead and the mounting surface of the sealing body so as to be larger than the distance between the lead and the sealing body.   The semiconductor device according to claim 1, wherein in the thickness direction of the sealing body, the semiconductor chip is arranged such that the main surface of the semiconductor chip is disposed between the lead and the upper surface of the die pad. A semiconductor device mounted on the upper surface of the die pad.   3. The semiconductor device according to claim 2, wherein in the thickness direction of the sealing body, the bus bar has an upper surface of the bus bar at the same position as the main surface of the semiconductor chip, or the upper surface of the bus bar is formed of the semiconductor chip. A semiconductor device, wherein the semiconductor device is disposed around the die pad so as to be disposed between the main surface and the mounting surface of the sealing body. 4. The semiconductor device according to claim 3, wherein the planar shape of the die pad is a quadrangle having a pair of first sides and a pair of second sides intersecting the first sides,
The planar shape of the bus bar is located between the third side aligned with the first side of the die pad, the fourth side aligned with the second side of the die pad, and the third side and the fourth side. Consisting of an octagonal frame with a fifth side,
Each of the plurality of suspension leads is connected to the fifth side of the bus bar.   5. The semiconductor device according to claim 4, wherein the fifth side of the bus bar extends in a direction perpendicular to the extending direction of the suspension leads. 5. The semiconductor device according to claim 4, wherein the bus bar is connected to the die pad via a plurality of second suspension leads arranged between the third side and the fourth side of the bus bar and the die pad. ,
Each of the plurality of second suspension leads has a bent portion formed therein.   7. The semiconductor device according to claim 6, wherein the corner portion of the die pad is not connected to the second suspension lead, and the corner portion is in close contact with a part of the sealing body. Semiconductor device.   4. The semiconductor device according to claim 3, wherein the side surface of the sealing body includes a first gate resin formed on an upper surface side of the suspension lead and a lower surface side opposite to the upper surface of the suspension lead. A semiconductor device comprising: a formed second gate resin.   9. The semiconductor device according to claim 8, wherein a planar shape of the semiconductor chip is a quadrangle, and the plurality of electrode pads are arranged along a side of the main surface of the semiconductor chip. .   10. The semiconductor device according to claim 9, wherein the bus bar is disposed between the lead and the mounting surface of the sealing body such that an upper surface of the bus bar is inclined with respect to a planar direction. A semiconductor device.   11. The semiconductor device according to claim 10, wherein an outer size of the die pad is larger than an outer size of the semiconductor chip. The semiconductor device according to claim 11, wherein the lower surface of the die pad is exposed from the mounting surface of the sealing body,
The semiconductor device, wherein the lower surface of the die pad exposed from the mounting surface of the sealing body is electrically connected to an electrode pad formed on a main surface of a mounting substrate. The semiconductor device according to claim 11, wherein the lower surface of the die pad is exposed from the surface of the sealing body,
A heat sink is arranged on the surface of the sealing body,
The die pad exposed from the surface of the sealing body is connected to the heat radiating plate. A method for manufacturing a semiconductor device comprising the following steps:
(A) a die pad having an upper surface and a lower surface opposite to the upper surface, a bus bar disposed around the die pad, a plurality of suspension leads formed with bent portions and connected to the bus bar, and the periphery of the bus bar Providing a lead frame comprising a plurality of leads disposed on;
(B) mounting a semiconductor chip having a main surface, a plurality of electrode pads formed on the main surface, and a back surface opposite to the main surface on the upper surface of the die pad;
(C) electrically connecting the plurality of electrode pads and the plurality of leads of the semiconductor chip via a plurality of wires;
(D) The bus bar, the semiconductor chip, and the plurality of wires are sealed with a resin so that a part of each of the plurality of leads is exposed from a side surface of the sealing body and the lower surface of the die pad is exposed. Process;
(E) separating each of the plurality of leads exposed from the sealing body from the lead frame;
here,
In the step (a), in the thickness direction of the lead frame, the interval between the lead and the bus bar is the same as the interval between the bus bar and the die pad, or larger than the interval between the bus bar and the die pad. Preparing the lead frame comprising the bus bar disposed between the lead and the upper surface of the die pad;
The step (d)
(D1) a first cavity and an upper mold having a first gate connected to the first cavity; a second cavity facing the first cavity; and a first cavity facing the first gate and connected to the second cavity. Preparing a molding die having a lower die having two gates;
(D2) After the step (d1), placing the lead frame on which the semiconductor chip is mounted between the first cavity of the upper die and the second cavity of the lower die;
(D3) After the step (d2), supplying the resin into the first cavity and the second cavity via the first gate and the second gate;
A method for manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 14,
The upper mold has a first parting surface that contacts an upper surface of the lead frame;
The lower mold has a second parting surface that contacts the lower surface of the lead frame;
A method of manufacturing a semiconductor device, wherein a distance from each of the plurality of leads to the die pad is larger than a distance from the second parting surface to a bottom surface of the second cavity.   16. The method of manufacturing a semiconductor device according to claim 15, wherein a dam between each lead is cut between the step (d) and the step (e), and an exterior plating is applied after the dam is cut. A method for manufacturing a semiconductor device.

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