JP2009231322A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent defects, such as, cracking and chipping of a semiconductor chip. <P>SOLUTION: The manufacturing method of a QFP (semiconductor device) 1 includes a process of preparing a lead frame; a process of bonding a chip (semiconductor chip) 2 to a die pad 5c; and a process of electrically connecting the pad (terminal) 2c of the chip 2 and the inner lead (lead) 5a of the lead frame via a wire (conductive member), and a process of forming a plating layer 5e bonded with the wire 6 at a part of the inner lead 5a. The plating layer 5e is formed in a first region 5f of a suspension lead 5d which supports the die pad 5c, as well, and the distal end on the inner side of the first region 5f is disposed more on the outer side than a chip disposition region 5g, where the chip 2 is disposed in the process of bonding the chip 2 with the die pad 5c. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effectively applied to a semiconductor device in which a semiconductor chip is mounted in a chip mounting region of a lead frame and the terminals of the semiconductor chip and leads of the lead frame are electrically connected. .

  There is a lead frame type semiconductor device in which a semiconductor chip is mounted on a die pad of a lead frame, and a terminal of the semiconductor chip and a lead of the lead frame are electrically connected by a wire such as a gold wire. In this lead frame type semiconductor device, a technique of forming a plating layer of Ag (silver) or the like partially on the outermost surface of the tip region of the lead (inner lead) is used to improve the bondability between the lead and the wire. (For example, Patent Document 1, Patent Document 2, or Patent Document 3).

In addition, the lead frame type semiconductor device has a technology for manufacturing semiconductor chips having different outer dimensions with a common lead frame by making the outer dimensions of the die pad supported by the suspension leads smaller than the outer dimensions of the semiconductor chip. There is (for example, Patent Document 4).
JP-A-9-307050 Japanese Patent Laid-Open No. 11-87587 JP 2006-303371 A JP 2007-31930 A

  By the way, as described above, when electrically connecting the terminal of the semiconductor chip and the lead via the wire, a plating layer is formed in the bonding region of the wire in the lead in order to improve the bondability between the wire and the lead. It is effective to keep it. In consideration of speeding up of the semiconductor device (speeding up of signal processing), it is desirable to form the wire as short as possible. Therefore, the plating layer is preferably formed in the region of the tip (inner lead side) of the lead (inner lead). Partial plating in which a plating layer is partially formed in the tip region of the inner lead is performed by bringing a mask into contact with the lead frame so as to cover a portion other than the region where the plating layer is formed. That is, the opening of the mask is matched only at the place where the plating layer is formed. When plating is performed in a state where the mask is in contact, a plating layer can be selectively formed on a portion exposed from the mask.

  However, it is difficult to form a plating layer locally only in the tip region of the inner lead due to problems such as mask processing accuracy and alignment accuracy. In particular, in recent years, in order to meet the demand for miniaturization and high functionality of semiconductor devices, leads that are external connection terminals have been made to have a narrow pitch and multiple pins. As described above, in the manufacturing process of a semiconductor device having a structure in which a large number of fine inner leads are arranged at a narrow pitch, when a mask that exposes only the tip region of the inner lead is brought into contact, the mask processing accuracy and alignment accuracy Due to this, it may become impossible to form a plating layer at a predetermined position. For this reason, in partial plating, an opening corresponding to a region wider than the tip region of the inner lead is formed in the mask, and a region for forming the plating layer on the inner lead is exposed from the opening of such a mask. It is necessary to perform plating.

  As a result of studying a semiconductor device in which partial plating is performed on a wire bonding scheduled region of an inner lead, the present inventor has found the following problems.

  26 and 27, which are enlarged plan views for explaining a comparative example of the present application, first, the opening 15a formed in the mask 15 may be provided only in the region where the wire is joined. However, with the miniaturization of the semiconductor device, the width of each of the plurality of inner leads 16a tends to become narrower. Thus, it is difficult to form a plurality of openings 15a corresponding to the tip regions of the inner leads 16a in the mask 15 because of the problem of processing accuracy. Therefore, it is effective to form the opening 15a formed in the mask 15 so that the tip portions of the plurality of inner leads 16a are opened together. At this time, when the plating layer is not formed in the region of the die pad 16b that supports the semiconductor chip, it is necessary to cover the region of the die pad 16b with a mask. Therefore, in order to support the portion covering the die pad 16b, a mask is also formed in a portion corresponding to the suspension lead 16c of the lead frame 16, as shown in FIG.

  However, as described above, there is a tendency that the width of the suspension lead 16c becomes narrow due to the downsizing of the semiconductor device. As a result, even if the suspension lead portion of the mask 15 is to be overlapped with the suspension lead 16 c of the lead frame 16, the suspension lead portion 16 c of the lead frame 16 can be reliably covered with the suspension lead portion of the mask 15 due to the problem of alignment accuracy. It becomes difficult.

  As a result, when the plating layers 17a and 17b (see FIG. 27) are formed on the lead frame 16 through the opening 15a of the mask 15, the plating layer 17b is also formed on the suspension lead 16c. Further, when plating is performed by exposing an area wider than the wire bonding scheduled area from the mask, as shown in FIG. 27, the plating layer 17b formed on the suspension lead 16c is formed on the die pad 16b rather than the tip of the inner lead 16a. It is formed to a position close to. Thereby, when mounting the semiconductor chip in a later process, if the region where the plating layer 17b is formed and the mounting region of the semiconductor chip overlap in the suspension lead 16c, the plating layer 17b and the semiconductor chip come into contact with each other and the semiconductor chip is cracked. It has been clarified by the present inventors that defects such as chipping occur.

  In particular, as described in Patent Document 4, when the outer dimension of the die pad is made smaller than the outer dimension of the semiconductor chip, the semiconductor chip is also mounted on the suspension lead. For this reason, when a plating layer is formed on a part of the suspension lead and the semiconductor chip is arranged so as to overlap with a part of the plating layer, the plating layer and the semiconductor chip come into contact with each other and the semiconductor chip is cracked or chipped. The possibility increases.

  Further, according to the method described in Patent Document 3 described above, the plating layer on the suspension lead is crushed and thinned, so that contact between the semiconductor chip and the plating layer can be prevented during die bonding. However, even in this case, if there is a height difference between the semiconductor chip mounting surface of the die pad and the surface of the plating layer, the semiconductor chip and the plating layer come into contact with each other. Defects such as chipping may occur. Moreover, since it is necessary to add the process of crushing the plating layer on a suspension lead, the new subject that a manufacturing efficiency falls arises.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of preventing the occurrence of defects such as cracks and chipping of a semiconductor chip in a lead frame type semiconductor device. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes a die pad having an outer dimension smaller than a semiconductor chip to be bonded, a plurality of leads arranged around the die pad, and the plurality of leads. A plurality of suspension leads disposed between the leads and supporting the die pad, and preparing a lead frame in which a plating layer is formed on each of the plurality of leads and the plurality of suspension leads. have. A step of bonding the semiconductor chip having a main surface on which the semiconductor element and a plurality of terminals are formed on the die pad; and a back surface located on the opposite side of the main surface; a plurality of terminals of the semiconductor chip; And electrically connecting the leads to each other through a conductive member. Here, the step of electrically connecting the plurality of terminals and the plurality of leads includes a step of bonding the plating layer and the conductive member. In addition, the inner tip of the first region where the plating layers of the plurality of suspension leads are formed is placed outside the chip placement region where the semiconductor chip is placed in the step of joining the semiconductor chip to the die pad. Is.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, it is possible to prevent the occurrence of defects such as cracks and chips in the semiconductor chip.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
<Structure of semiconductor device>
1 is a main part plan view showing an example of the internal structure of the semiconductor device according to the first embodiment. FIGS. 2 and 3 are main part cross-sectional views taken along lines AA and BB shown in FIG. 1, respectively. FIG. 4 is an enlarged plan view of the main part around the plating layer of the semiconductor device shown in FIG. 1, and FIG. 5 is an enlarged cross-sectional view of the main part around the plating layer of the semiconductor device shown in FIG. 4 and 5, illustration of the sealing body shown in FIGS. 1 to 3 is omitted for ease of viewing.

  The semiconductor device of the first embodiment shown in FIGS. 1 to 5 is a semiconductor package in which a plurality of semiconductor chips are embedded in a resin sealing body 4. A QFP (Quad Flat Package) 1 in which a plurality of outer leads 5b protruding from the side surfaces are formed in a gull wing shape will be described as an example.

  In FIG. 1, the number of terminals (pads) and the number of leads of the semiconductor chip are reduced for easy viewing. For example, a multi-pin type QFP having 200 or more leads (pins) is shown. You may apply to.

  The QFP (semiconductor device) 1 has a chip (semiconductor chip) 2 in which a semiconductor element and a plurality of pads (terminals) 2c are formed on a main surface 2a. The chip 2 is resin-sealed with a sealing body 4. The semiconductor element formed on the main surface 2a of the chip 2 is an element such as a transistor, for example, and a plurality of semiconductor elements constitute an integrated circuit.

  The chip 2 is bonded (mounted) to a die pad (chip mounting portion) 5 c having an outer dimension smaller than the outer dimension of the back surface 2 b of the chip 2. The die pad 5c has, for example, a substantially circular outer shape as shown in FIG. 1, and is supported by a plurality (four in FIG. 1) of suspension leads 5d arranged to extend radially outside the QFP 1. .

  Since the die pad 5c has an outer dimension smaller than the outer dimension of the back surface 2b of the chip 2, the outer periphery of the chip 2 protrudes from the outer shape of the die pad 5c. For this reason, a region facing the die pad 5c on the back surface 2b of the chip 2 is bonded to the die pad 5c via an adhesive 3 such as a silver (Ag) paste, for example. It is in close contact with the resin of the body 4.

  By making the outer dimension of the die pad 5c smaller than the outer dimension of the back surface 2b of the chip 2, the area where the back surface 2b of the chip 2 and the resin of the sealing body 4 are in close contact with each other can be widened. Can be prevented. Further, for example, even when a chip 2 having an outer dimension smaller than that of the chip 2 shown in FIG. 1 is mounted, it can be mounted without changing the outer dimension of the die pad 5c. That is, since chips 2 having different external dimensions can be manufactured with a common lead frame, standardization of the lead frame can be achieved.

  A plurality of inner leads 5a, which are a plurality of leads, are arranged around the die pad 5c so as to extend in four directions. The inner leads 5 a are integrally formed with a plurality of outer leads 5 b that respectively protrude from the four side surfaces of the sealing body 4. The plurality of outer leads 5b protruding from the side surface of the sealing body 4 serve as external connection terminals of the QFP 1.

  The plurality of suspension leads 5d that support the die pad 5c are respectively disposed between two intersecting directions among the four directions in which the inner leads 5a extend. Further, the plurality of suspension leads 5d are integrally formed so that each end portion (one end portion) of the plurality of suspension leads 5d is connected to the die pad 5c. In addition, an end portion (other end portion) opposite to the end portion is located on the outer edge portion side of the sealing body 4.

  The inner lead 5a, the outer lead 5b, the die pad 5c, and the suspension lead 5d each constitute part of a lead frame used for manufacturing the QFP 1, and are formed integrally before being separated into individual pieces.

  The pads 2c of the chip 2 are electrically connected to the inner leads 5a through wires (conductive members) 6, respectively. A plating layer 5e is formed at the joint between the wire 6 and the inner lead 5a, and the wire 6 is bonded to the plating layer 5e.

  The plating layer 5e is formed in order to improve the bondability (electrical bondability and mechanical bondability) between the wire 6 and the inner lead 5a. Since noble metal such as gold (Au) is generally used as the material constituting the wire 6, a noble metal having good bondability with noble metal such as gold is used for the outermost surface layer of the plating layer. For example, when the base material of the inner lead 5a is an iron (Fe) alloy such as 42 alloy, plating is performed by sequentially laminating copper (Cu) and silver on the surface of the inner lead 5a on the side to which the wire 6 is joined. It can be the layer 5e. Moreover, when the base material of the inner lead 5a is a copper alloy, it can be set as the plating layer 5e which laminated | stacked pure copper and silver in order on the surface at the side which joins the wire 6 of the inner lead 5a.

  The plating layer 5e is formed in the tip region of the inner lead 5a. This is to shorten the path length of the wire 6 by bringing the joint between the inner lead 5a and the wire 6 closer to the pad 2c of the chip 2 and to minimize the amount of gold used as an expensive material. is there. Similarly, since an expensive noble metal such as silver is used for the plating layer 5e, the plating layer 5e is formed not on the entire lead frame but on a part (tip portion) of the inner lead 5a.

  Here, the plating layer 5e is formed not only on a part of the inner lead 5a but also on a part of the suspension lead 5d. The plating layer 5e formed on the suspension lead 5d is formed in the first region 5f as shown in FIGS. The plating layer 5e formed on the suspension lead 5d is formed by a plating layer forming process, which will be described later, and details thereof will be described when the manufacturing method of the QFP 1 is described. Further, as shown in FIGS. 4 and 5, the tip on the inner side of the first region 5 f is arranged to be outside the chip arrangement region 5 g where the chip 2 is arranged. The QFP 1 thus prevents the chip 2 and the plating layer 5e from overlapping each other by making the inner tip of the first region 5f outside the chip arrangement region 5g, thereby preventing the chip 2 and the plating layer 5e from overlapping each other. This will prevent the occurrence of defects such as cracks and chips in the chip 2, which will be described in detail when the method for manufacturing the QFP 1 is described.

<Method for Manufacturing Semiconductor Device>
Next, a manufacturing method of QFP 1 shown in FIGS. 1 to 5 and a detailed structure of QFP 1 will be described. The QFP 1 of the first embodiment is obtained as follows. FIG. 6 is an enlarged plan view of a main part showing an enlarged portion corresponding to one semiconductor device of a lead frame used for manufacturing the semiconductor device of the first embodiment, and FIG. 7 is a plan view of the semiconductor device of the first embodiment. The principal part enlarged plan view which shows the state which has arrange | positioned the mask for partial plating in the lead frame used for manufacture, FIG.8 and FIG.9 is the principal part expanded cross section along CC line and DD line | wire which are shown in FIG. 7, respectively. FIG. 10 and 11 are enlarged cross-sectional views of main parts taken along lines EE and FF shown in FIG. 6, respectively. FIG. 12 is an enlarged view showing the periphery of the plating layer of the lead frame shown in FIG. FIG.

  (A) First, the lead frame 5 shown in FIG. 6 is prepared. In the lead frame 5 prepared in this step, a unit lead frame (hereinafter simply referred to as a lead frame) corresponding to one semiconductor device shown in FIG. 6 is planarized by a support frame (not shown) of the lead frame 5. A plurality of them connected to each other can be used. Further, the inner lead 5a, the outer lead 5b (see FIG. 1), the die pad 5c, and the suspension lead 5d formed on the lead frame 5 are integrally formed and connected to each other via a support frame of the lead frame.

  For example, the lead frame 5 shown in FIG. 6 is obtained as follows. First, an iron-based (for example, 42 alloy) or copper-based (for example, a copper alloy, or a copper surface on which a plated layer of Ni or the like is formed) is prepared and predetermined by etching or pressing. The inner lead 5a, the outer lead 5b (see FIG. 1), the die pad 5c, the suspension lead 5d, and the like are formed with this pattern. In the case of a lead frame having a relatively large number of inner leads 5a, the width of each inner lead 5a is narrowed. Therefore, the plating layer forming step described below is performed with the tips of the inner leads 5a connected, and thereafter In some cases, the connecting portion connecting the inner leads 5a is cut with a punch or the like.

  Next, as a plating layer forming step, a plating layer for joining the wire 6 to each part of the inner lead 5a and the suspension lead 5d is formed. In this step, the plating mask 7 is placed in contact with the non-plating region of the lead frame 5 (the region where the plating layer 5e is not formed). The plating mask 7 includes a back surface covering portion 7a that covers the back surface side of the lead frame 5 (see FIG. 6), an inner surface covering portion 7b that covers the inner surface of the inner surface 5a of the lead frame 5 and the lead frame 5. And an outer covering portion 7c that covers the outer side of the first region 5f on the front surface side. For example, as shown in FIG. 6, the inner covering portion 7b is connected to and supported by the outer covering portion 7c by a connecting portion 7d arranged outside the inner covering portion 7b.

  When the back surface covering portion 7a is brought into contact with the back surface side of the lead frame 5 and the inner surface covering portion 7b and the outer surface covering portion 7c are brought into contact with the front surface side, an opening 7e is formed in the first region 5f, which is a plating layer formation scheduled region. The In this step, the plating layer 5e is formed by introducing a plating solution into the opening 7e and supplying electric power, for example, in the case of electric field plating. Since the connecting portion 7d is arranged at a distance from the suspension lead 5d as shown in FIG. 9, the plating solution enters between the connection portion 7d and the suspension lead 5d, and the suspension lead 5d is also plated. Layer 5e is formed.

  Since the plating mask 7 is made of an elastic body such as silicon rubber, the plating mask 7 is deformed along each member constituting the lead frame 5. Therefore, as shown in FIG. 8, since the inner covering portion 7b and the back surface covering portion 7a are in close contact with each other in the region where the inner lead 5a is not disposed, the plating solution is prevented or suppressed from leaking into the region other than the opening 7e. be able to.

  Here, when the plating mask 7 is disposed, a displacement occurs, and when the plating mask 7 covers a region where the plating layer 5e of the inner lead 5a is to be formed, the plating layer 5e is not formed at a predetermined position. In the wire bonding step, which will be described later, this causes a bonding failure between the wire 6 (see FIG. 1) and the inner lead 5a. For this reason, a method of forming the plating layer 5e over a wide range by reducing the outer dimension of the inner covering portion 7b and increasing the width of the opening 7e is generally performed.

  However, if the width of the opening 7e is increased, the length of the plating layer 5e formed on the suspension lead 5d becomes longer, and therefore the chip 2 and the plating layer 5e may overlap in a die bonding process described later. If the chip 2 and the plating layer 5e overlap, the chip 2 and the plating layer 5e come into contact with each other, causing damage to the chip 2.

  Therefore, in the first embodiment, the outer dimension of the inner covering portion 7b is increased, and the outer edge of the inner covering portion 7b is disposed slightly inside the lead array line 5h formed by the tip portions of the plurality of inner leads 5a. Thereby, it can arrange | position so that the front-end | tip inside the 1st area | region 5f may become outside the chip | tip arrangement | positioning area | region 5g in which the chip | tip 2 shown in FIG.4 and FIG.5 is arrange | positioned.

  Further, in order to improve the alignment accuracy, the tips of adjacent inner leads 5a are arranged in a straight line. Thereby, since the outer edge part of the inner side coating | coated part 7b can be processed easily, a processing precision improves. As a result, the alignment accuracy is improved. In addition, as shown in FIG. 9, it is not necessary to individually align the inner covering portion 7b and the outer covering portion 7c, so that the alignment accuracy can be improved.

  Next, as shown in FIGS. 10 and 11, as the offset process, the plane position of the die pad 5c is offset from the plane position of the inner lead 5a (FIG. 10 and FIG. 11 show an example of downset, but upset may be used. ) In this step, after forming the plating layer 5e as shown in FIG. 10, the planar position of the die pad 5c is offset to a position different from the planar position of the inner lead 5a (see FIG. 11) by bending the suspension lead 5d. For example, the offset can be performed by bending a predetermined position of the suspension lead 5d using a punch and a die.

  The position where the suspension lead 5d is bent, that is, the bent portion 5i is disposed outside the front end inside the first region 5f as shown in FIG. That is, in this process, the outside is bent rather than the inner end of the first region 5f. Thereby, the inner end of the plating layer 5e is pulled outward. As a result, as shown in FIG. 12, the tip of the inner side of the first region 5f overlaps with the intersection 5k of the extension line of the lead arrangement line 5h formed by the tip of the inner lead 5a and the suspension lead 5d, or It will be arranged outside the intersection 5k.

  In the first embodiment, the lead frame is standardized by bonding the chip 2 to a die pad (chip mounting portion) 5c having an outer dimension smaller than the outer dimension of the back surface 2b of the chip 2 as shown in FIG. Therefore, the chip 2 is also disposed on the suspension lead 5d. However, the chip placement area 5g in which the chip 2 is placed is inside the lead array line 5h shown in FIG. This is to prevent the inner lead 5a and the chip 2 from coming into contact with each other. Therefore, the first region 5f is arranged at a position overlapping the intersection 5k of the extension line of the lead arrangement line 5h and the suspension lead, or outside the intersection 5k by disposing the first region 5f in FIG. The chip can be reliably arranged outside the chip arrangement region 5g shown in FIG.

  When the offset process is completed, as shown in FIG. 6, the lead frame 5 in a state where the position on the plane of the die pad 5c is offset from the plane position of the inner lead 5a is obtained.

  (B) Next, the chip 2 shown in FIG. 13 is prepared, and the chip 2 is bonded (mounted) to the die pad 5c (die bonding step).

  13 is an enlarged plan view of a main part showing a state in which an adhesive paste for bonding a semiconductor chip is applied to the die pad of the lead frame shown in FIG. 6, and FIG. 14 is a cross section taken along the line GG shown in FIG. It is a principal part expanded sectional view which shows the state which apply | coats an adhesive paste. 15 is an enlarged plan view of a main part showing a state in which a semiconductor chip is mounted on the die pad shown in FIG. 13, and FIGS. 16 and 17 are cross sections taken along lines HH and JJ, respectively, shown in FIG. FIG. 6 is an enlarged cross-sectional view of a main part showing a state in which a semiconductor chip is pressed against a die pad using a bonding jig. FIG. 18 is an enlarged perspective view of the main part of the chip suction portion of the bonding jig shown in FIGS. 16 and 17. FIG. 25 is an essential part enlarged cross-sectional view showing a state in which a semiconductor chip is pressed against a die pad of a semiconductor device, which is a comparative example of the first embodiment, using a bonding jig.

  In this step, first, an adhesive paste 3a such as a silver paste is applied on the die pad 5c. For application, for example, a dispenser 8 having a discharge nozzle at the tip as shown in FIG. 14 can be used. The adhesive paste 3a is a viscous paste and spreads on the surface of the die pad 5c when the chip 2 is pressed against the die pad 5c. Therefore, the adhesive paste 3a may be spotted at a plurality of locations as shown in FIG.

  Next, as shown in FIG. 15, the chip 2 is placed on the die pad 5c and pressed. Various bonding jigs can be used as a bonding jig that transports the chip 2 to a predetermined position of the die pad and presses the chip 2 against the die pad 5c. For example, a collet 9 shown in FIG. 17 can be used. A collet 9 shown in FIG. 17 is a suction holding tool for sucking and holding the chip 2 (see FIG. 16), and is called a pyramid collet. The suction surface of the collet 9 is concave, and the suction surface has four tapered surfaces 9a. In addition, an air inlet 9b is formed on the suction surface. By sucking air from the air inlet 9b, the chip 2 can be held or the die pad 5c (FIG. 16) without touching the pad 2c formed on the main surface 2a of the chip 2. See).

  Here, as shown in FIG. 25, when the tip of the first region 5f is arranged inside the chip arrangement region 5g, the back surface 2b of the chip 2 and the plating layer 5m overlap each other. When the chip 2 is pressed by the collet 9 in this state, the pressure from the collet 9 is concentrated and transmitted to a portion overlapping the plating layer 5m on the back surface 2b of the chip 2, that is, each corner of the chip 2. For this reason, the present inventors have found that defects such as cracks and chips are generated particularly at the corners of the chip 2.

  In the first embodiment, as shown in FIG. 17, since the tip of the first region 5f is arranged outside the chip arrangement region 5g, the back surface 2b of the chip 2 and the plating layer 5m do not overlap. Therefore, even when pressed by the collet 9, the pressure from the collet 9 is transmitted evenly to the entire chip 2, and the occurrence of defects such as cracks and chipping of the chip 2 can be prevented. In the first embodiment, the tip of the first region 5f is arranged outside the chip arrangement region 5g, thereby preventing contact between the back surface 2b of the chip 2 and the plating layer 5m. There is no need to add.

  After pressing the chip 2 against the die pad 5c, the adhesive paste 3a is heated and cured. When the adhesive paste 3a is cured, the adhesive 3 shown in FIG. 2 or 3 is obtained, and the bonding of the chip 2 is completed.

  (C) Next, as a wire bonding step, the chip 2 and each of the inner leads 5a as a plurality of leads are electrically connected.

  19 is an enlarged plan view of a main part showing a state where the chip mounted on the lead frame shown in FIG. 15 and the inner lead are electrically connected, and FIG. 20 is taken along the line KK shown in FIG. It is a principal part expanded sectional view.

  In this step, first, the lead frame 5 to which the chip 2 is bonded is placed on the wire bonding stage 10. Further, in order to fix the position of the inner lead 5 a during wire bonding, each inner lead 5 a is pressed against the wire bonding stage 10 by the holding jig 11. In addition, it is preferable to arrange | position the position which arrange | positions the pressing jig 11 in the vicinity of the plating layer 5e which is a wire bonding position.

  Next, the pad 2 c and the plating layer 5 e are electrically connected via the wire 6. Thereby, the chip 2 and the inner lead 5a are electrically connected. FIG. 20 shows an example in which the wire 6 and the pad 2c are first bonded as the first bond, and then the wire 6 and the plating layer 5e are bonded as the second bond. However, the order of the wire bonding is not limited to this. .

  (D) Next, the chip 2 bonded to the lead frame 5 is resin-sealed by the sealing body 4. FIG. 21 is an enlarged plan view of a main part showing a state after the chip shown in FIG. 19 is resin-sealed with a sealing body.

  In this step, for example, the lead frame 5 is sandwiched between molds (upper mold and lower mold) in which cavities are formed for each unit lead frame (lead frame corresponding to one semiconductor device), and the inside of the cavity The sealing resin is injected into and cured. When the mold is removed after the sealing resin is cured, the sealing body 4 is formed for each unit lead frame corresponding to one semiconductor device shown in FIG. 21, and the outer lead 5 b is formed from the side surface of the sealing body 4. It becomes a derived state.

  (E) Next, the dam bar (the connecting portion of each outlead 5b) connecting the outer leads 5b shown in FIG. 21 is cut, and the outer leads 5b are formed into a gull wing shape, whereby the QFP 1 shown in FIGS. can get.

(Embodiment 2)
FIG. 22 is an enlarged plan view of the main part showing the internal structure of the semiconductor device of the second embodiment, and FIGS. 23 and 24 are masks for forming a plating layer on the lead frame used for manufacturing the semiconductor device shown in FIG. It is a principal part expanded sectional view which shows the state which made it contact | abut. 23 and 24 are cross-sectional views of the region corresponding to the cross-sectional view described in FIG. 8 of the first embodiment. The structure of the QFP 20 described in the second embodiment is the same as that of the QFP 1 described in the first embodiment except for the position where the plating layer 5e is formed. Therefore, the overlapping description is omitted.

  The difference between the QFP 20 of the second embodiment and the QFP 1 described in the first embodiment is the position where the plating layer 5e is formed. The QFP 20 is not formed with the plating layer 5e at the tip of the inner lead 5a, but is formed outside thereof. That is, the plating layer 5e is not formed at the tip of the inner lead 5a.

  As described in the first embodiment, the plating layer 5e is formed to improve the bondability (electrical bondability and mechanical bondability) between the wire 6 and the inner lead 5a. Further, in order to shorten the path length of the wire 6 and minimize the amount of gold, which is an expensive material, it is preferable to form the wire 6 around the tip of the inner lead 5a.

  However, since the wire 6 (see FIG. 20) cannot be bonded to the tip of the inner lead 5a in the wire bonding process, the path length of the wire 6 can be obtained even if no plating layer is formed on the tip. Will not change significantly.

  On the other hand, in the plating layer process, since the plating layer 5e is not formed at the tip of the inner lead 5a, as shown in FIG. 23, the plating mask 7 (inner covering portion 7b) is covered so as to cover the tip of the inner lead 5a. It will contact. Therefore, as described in the first embodiment, the plating mask 7 is compared with the method in which the outer edge of the inner covering portion 7b is disposed slightly inside the lead arrangement line 5h formed by the tips of the inner leads 5a. Can be easily aligned.

  Further, if the plating mask 7 (inner covering portion 7b) comes into contact with the tip surface of the inner lead 5a as shown in FIG. 24 due to the processing accuracy or positioning accuracy of the plating mask 7. Even if it exists, a wire 6 (refer FIG. 20) can be joined to the plating layer 5e without a problem in a wire bonding process.

  Thus, according to the second embodiment, in addition to the effects described in the first embodiment, the positioning of the plating mask 7 can be easily performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first and second embodiments, QFP has been described as an example of a semiconductor device. However, the techniques described in the first and second embodiments form a plating layer in a region to be joined to the inner lead wire, and are widely applied to semiconductor devices having a die pad having a smaller outer dimension than a semiconductor chip. can do. In particular, when applied to a semiconductor device in which inner leads extend in four directions around a die pad, such as a QFN (Quad Flat Non-leaded package), a great effect can be obtained.

  The present invention is applicable to semiconductor devices such as QFP and QFN.

It is a principal part top view which shows an example of the internal structure of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing along the AA shown in FIG. It is principal part sectional drawing along the BB line shown in FIG. FIG. 2 is an enlarged plan view of a main part around a plating layer of the semiconductor device shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view of a main part around a plating layer of the semiconductor device shown in FIG. 3. It is a principal part enlarged plan view which expands and shows the part corresponding to one semiconductor device of the lead frame used for manufacture of the semiconductor device which is one embodiment of this invention. It is a principal part enlarged plan view which shows the state which has arrange | positioned the mask for partial plating in the lead frame used for manufacture of the semiconductor device which is one embodiment of this invention. It is a principal part expanded sectional view along CC line shown in FIG. It is a principal part expanded sectional view along the DD line shown in FIG. It is a principal part expanded sectional view along the EE line shown in FIG. It is a principal part expanded sectional view along the FF line shown in FIG. FIG. 7 is an enlarged cross-sectional view of a main part showing an enlarged periphery of a suspended plating layer of the lead frame shown in FIG. 6. FIG. 7 is an enlarged plan view of a main part showing a state where an adhesive paste for bonding a semiconductor chip is applied to a die pad of the lead frame shown in FIG. 6. FIG. 14 is an enlarged cross-sectional view of a main part illustrating a state in which an adhesive paste is applied, which is a cross-section along line GG illustrated in FIG. 13. FIG. 14 is an enlarged plan view showing a state where a semiconductor chip is mounted on the die pad shown in FIG. 13. FIG. 16 is an enlarged cross-sectional view taken along line HH shown in FIG. 15 and showing a state in which a semiconductor chip is pressed against a die pad using a bonding jig. FIG. 16 is an enlarged cross-sectional view taken along line JJ shown in FIG. 15 and showing a state in which the semiconductor chip is pressed against the die pad using a bonding jig. It is an expansion perspective view of the chip | tip adsorption | suction part of the bonding jig | tool shown to FIG. 16 and FIG. FIG. 16 is an essential part enlarged plan view showing a state where a chip mounted on the lead frame shown in FIG. 15 and an inner lead are electrically connected to each other; It is a principal part expanded sectional view along the KK line | wire shown in FIG. It is a principal part enlarged plan view which shows the state after resin-sealing the chip | tip shown in FIG. 19 with the sealing body. It is a principal part top view which shows an example of the internal structure of the semiconductor device which is other embodiment of this invention. FIG. 23 is an essential part enlarged cross-sectional view showing a state in which a mask for forming a plating layer is brought into contact with a lead frame used for manufacturing the semiconductor device shown in FIG. 22; FIG. 23 is an essential part enlarged cross-sectional view showing a state in which a mask for forming a plating layer is brought into contact with a lead frame used for manufacturing the semiconductor device shown in FIG. 22; It is an expanded sectional view which shows the state which presses a semiconductor chip on the die pad of the semiconductor device which is a comparative example of one embodiment of this invention using a bonding jig. It is an enlarged plan view showing a state where a plating mask is superimposed on a lead frame which is a comparative example of the present invention. FIG. 6 is an enlarged plan view in the vicinity of a suspended lead when a plating mask is superimposed on a lead frame that is a comparative example of the present invention.

Explanation of symbols

1,20 QFP (semiconductor device)
2 chips (semiconductor chips)
2a Main surface 2b Back surface 2c Pad (terminal)
3 Adhesive 3a Adhesive paste 4 Sealing body 5 Lead frame 5a Inner lead (lead)
5b Outer lead 5c Die pad (chip mounting part)
5d Hanging lead 5e, 5m Plating layer 5f First region 5g Chip placement region 5h Lead arrangement line 5i Bending portion 5k Intersection 6 Wire (conductive member)
7 Plating Mask 7a Back Cover 7b Inner Cover 7c Outer Cover 7d Connection 7e Opening 8 Dispenser 9 Collet (Bonding Jig)
9a Tapered surface 9b Inlet 10 Wire bonding stage 11 Holding jig 15 Mask 15a Opening 16 Lead frame 16a Inner lead 16b Die pad 16c Suspension leads 17a and 17b Plating layer

Claims (5)

A plurality of leads each including a die pad for bonding a semiconductor chip, a plurality of leads disposed around the die pad, and a plurality of suspension leads disposed on the plurality of leads and supporting the die pad; And preparing a lead frame in which a plating layer is formed on a part of each of the plurality of suspension leads,
Bonding the semiconductor chip having a main surface on which the semiconductor element and a plurality of terminals are formed on the die pad and a back surface located on the opposite side of the main surface;
Electrically connecting a plurality of terminals of the semiconductor chip and the plurality of leads via conductive members, respectively.
The die pad has a smaller outer dimension than the semiconductor chip,
The step of electrically connecting the plurality of terminals and the plurality of leads includes a step of bonding the plating layer and the conductive member,
The inner tip of the first region where the plating layers of the plurality of suspension leads are formed is disposed outside the chip placement region where the semiconductor chip is placed in the step of joining the semiconductor chip to the die pad. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
An inner tip of the first region is disposed at a position overlapping an intersection of an extension line of a lead arrangement line formed by inner tips of the plurality of leads and a suspension lead, or outside the intersection. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 2,
In the step of forming the plating layer, a method of manufacturing a semiconductor device is characterized in that a plating mask that is brought into contact with a non-plating region is brought into contact with tip ends of the plurality of leads. In the manufacturing method of the semiconductor device according to claim 3,
In the step of forming the plating layer, a method of manufacturing a semiconductor device is characterized in that a plating mask that is brought into contact with a non-plating region is brought into contact so as to cover tip portions of the plurality of leads. In the manufacturing method of the semiconductor device according to claim 2,
The step of preparing the lead frame includes the step of offsetting the planar position of the die pad to a position different from the planar position of the plurality of leads by bending the plurality of suspension leads after forming the plating layer, The method of manufacturing a semiconductor device, wherein, in the offsetting step, the outside is bent rather than the inner tip of the first region.

Images