JP2012074495A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve reliability of packaging though heat stress is applied by approximating a thermal expansion coefficient of the semiconductor device with a thermal expansion coefficient of a mounting board.SOLUTION: A semiconductor device 20 comprises a lead frame 10 including a die pad 15 and a plurality of lead parts 16 disposed around the die pad 15, a semiconductor element 21 loaded on the die pad 15 of the lead frame 10, and bonding wires 22 electrically connecting the lead parts 16 of the lead frame 10 with the semiconductor element 21. The lead frame 10, the semiconductor element 21 and the bonding wires 22 are encapsulated by an encapsulation resin part 23. The encapsulation resin part 23 has the semiconductor element 21, a central region 24 provided around the semiconductor element 21 and a peripheral region 25 provided on the circumference ot the central region 24. A thickness of the central region 24 is thicker than a thickness of the peripheral region 25.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of improving mounting reliability.

  In recent years, semiconductor devices have been increasingly integrated and highly functional, as represented by LSI ASICs, due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter and shorter electronic devices. It is going on. In such highly integrated and highly functional semiconductor devices, it is required to increase the total sum of external terminals (pins) and further increase the number of terminals (pins).

  As such a semiconductor device, there is a semiconductor package having a structure in which a semiconductor chip such as an IC chip or an LSI chip is mounted on a lead frame and sealed with an insulating resin. As such a semiconductor device, a thin type device having a small mounting area such as a quad flat non-leaded package (QFN) or a small outline non-leaded package (SON) is known. Also, a resin-encapsulated semiconductor device called a BGA (Ball Grid Array), which is a surface mount package having solder balls as external terminals of the package, is mass-produced. Furthermore, there is a semiconductor device called an LGA (Land Grid Array) as a surface mount package provided with external terminals made of matrix-like planar electrodes in place of BGA solder balls.

  As such a conventional semiconductor device, for example, those described in Patent Document 1 and Patent Document 2 are known.

  Patent Document 1 discloses a semiconductor integrated circuit device in which a lead frame has a circular outer shape and leads are radially expanded from a central die pad. According to this Patent Document 1, high mounting reliability can be obtained as a gull wing lead package, but it cannot cope with the reduction in thickness and size of a package that has been required in recent years.

  Patent Document 2 describes a chip having a hexagon or more polygon (or a circle). According to Patent Document 2, the chip is a hexagon or more polygon (or a circle), but it is considered difficult to manufacture such a polygon or a circle.

JP-A-8-227964 Japanese Patent Laid-Open No. 8-138898

  Incidentally, in recent years, for example, lead frame type small semiconductor devices (QFN, SON, LGA, etc.) have been required to further improve their mounting reliability. In particular, by making the thermal expansion coefficient of the semiconductor device closer to the thermal expansion coefficient of the mounting substrate, it is possible to further improve the mounting reliability when the semiconductor device is subjected to thermal stress by being used in a high temperature environment such as an automobile. It is desired.

  The present invention has been made in consideration of such points, and by making the thermal expansion coefficient of the semiconductor device close to the thermal expansion coefficient of the mounting substrate, it is possible to improve the reliability when thermal stress is applied. An object of the present invention is to provide a simple semiconductor device.

  The present invention relates to a lead frame having a die pad and a plurality of lead portions arranged around the die pad, a semiconductor element placed on the die pad of the lead frame, and a lead portion of the lead frame and the semiconductor element electrically A conductive portion to be connected; a lead frame; a semiconductor element; and a sealing resin portion for sealing the conductive portion. The sealing resin portion includes a central area provided around the semiconductor element and the semiconductor element, and a peripheral edge of the central area. The semiconductor device is characterized in that the thickness of the central region is larger than the thickness of the peripheral region.

  According to the present invention, each lead portion has a strip shape extending radially outward from the die pad and has an external terminal exposed outward, and the external terminals of the plurality of lead portions are at least one when viewed from a plane. The semiconductor device is arranged on two circumferences.

  According to the present invention, each lead part has two external terminals, one external terminal is composed of an upper terminal provided on the front side of each lead part, and the other external terminal is on the back side of each lead part. A semiconductor device comprising a lower terminal provided.

  The present invention is a semiconductor device characterized in that a step portion is formed between an internal terminal and a lower terminal of each lead portion.

  The present invention is a semiconductor device characterized in that a solder ball is provided on an upper terminal of at least one lead portion.

  The present invention is a semiconductor device characterized in that a radiation fin is mounted on an upper terminal of at least one lead portion.

  The present invention is a semiconductor device in which an electronic component is mounted on an upper terminal of at least one lead portion.

  The present invention is a semiconductor device characterized in that each lead portion is exposed to the surface side in the peripheral region of the sealing resin portion.

  The present invention is the semiconductor device characterized in that the central region of the sealing resin portion has a truncated cone shape, a columnar shape, a polygonal column shape, a truncated polygonal pyramid shape, or a dome shape.

  The present invention is the semiconductor device characterized in that the die pad has a circular shape when viewed from the surface side.

  The present invention is the semiconductor device characterized in that the die pad has a circular shape when viewed from the back side.

  The present invention is a semiconductor device characterized in that the shape of the front surface and the shape of the back surface of the die pad are different from each other.

  The present invention is a semiconductor device characterized in that a suspension lead having an external terminal is connected to a die pad.

  The present invention is characterized in that a recess into which the sealing resin portion enters is formed on the front surface and the back surface of the suspension lead, respectively, and the arrangement positions of the recesses on the surface and the back surface of the suspension lead are different from each other when viewed from the plane. It is a semiconductor device.

  The present invention is the semiconductor device characterized in that the back surface of the die pad is exposed to the outside of the sealing resin portion.

  The present invention is the semiconductor device characterized in that the back surface of the die pad is not exposed to the outside of the sealing resin portion.

  The present invention is the semiconductor device characterized in that the surface of the die pad is positioned on the back side from the surface of each lead portion.

  The present invention is a semiconductor device characterized in that a flange is provided along the surface periphery of the die pad.

  According to the present invention, by making the thickness of the central region of the sealing resin portion thicker than the peripheral region, the thickness of the peripheral region is reduced and the volume of the sealing resin portion having a relatively low thermal expansion coefficient is reduced. . As a result, the thermal expansion coefficient of the entire semiconductor device can be brought close to the thermal expansion coefficient of the mounting substrate, and the semiconductor device when the semiconductor device is heated when the semiconductor device is mounted or after the semiconductor device is mounted. Reliability can be improved.

1 is a perspective view showing a semiconductor device according to an embodiment of the present invention. Sectional drawing which shows the semiconductor device by one embodiment of this invention (II-II sectional view taken on the line of FIG. 1). FIG. 3 is a plan view showing the semiconductor device according to the embodiment of the present invention, in which a portion above the surface of the lead portion is omitted. 1 is a back view showing a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. Sectional drawing which shows the manufacturing method of a lead frame. Sectional drawing which shows the manufacturing method of a semiconductor device. Sectional drawing which shows the state in which the semiconductor device by one embodiment of this invention is mounted on the mounting board | substrate. The perspective view which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention (XI-XI sectional view taken on the line of FIG. 10). The perspective view which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention (XIII-XIII sectional view taken on the line of FIG. 12). The perspective view which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention (XV-XV sectional view taken on the line of FIG. 14). The perspective view which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention (XVII-XVII sectional view taken on the line of FIG. 16). The perspective view which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention (XIX-XIX sectional view taken on the line of FIG. 18). Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. FIG. 9 is a plan view showing a semiconductor device according to a modification of the present invention, in which a portion above the surface of the lead portion is omitted. FIG. 9 is a plan view showing a semiconductor device according to a modification of the present invention, in which a portion above the surface of the lead portion is omitted. FIG. 9 is a plan view showing a semiconductor device according to a modification of the present invention, in which a portion above the surface of the lead portion is omitted. The top view which shows the modification of a suspension lead. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention. Sectional drawing which shows the semiconductor device by the modification of this invention.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

Configuration of Semiconductor Device First, an embodiment of the present invention will be described with reference to FIGS. 1 to 6 are diagrams showing a semiconductor device according to an embodiment of the present invention. In FIG. 1, for the sake of convenience, the number of lead portions is less than the actual number (the same applies to FIGS. 10, 12, 14, 16, and 18).

  As shown in FIGS. 1 to 4, the semiconductor device 20 is mounted on a lead frame 10 having a die pad 15 and a plurality of lead portions 16 arranged around the die pad 15, and the die pad 15 of the lead frame 10. The semiconductor element 21 and a plurality of bonding wires (conductive parts) 22 that electrically connect the lead part 16 of the lead frame 10 and the semiconductor element 21 are provided. Further, the lead frame 10, the semiconductor element 21, and the bonding wire 22 are resin-sealed by a sealing resin portion 23. The semiconductor device 20 has a rectangular shape when viewed from the plane.

  The sealing resin portion 23 has a semiconductor element 21, a central region 24 provided around the semiconductor element 21, and a peripheral region 25 located on the periphery of the central region 24. Among these, the central region 24 projects to the surface side when viewed from the peripheral region 25, and the thickness of the central region 24 is thicker than the peripheral region 25. On the other hand, the surface of the peripheral region 25 is on the same plane as the surface 16 a of each lead portion 16. That is, in the peripheral region 25, each lead portion 16 is exposed on the surface side. Thus, the sealing resin part 23 is formed in a hat shape (cap shape) as a whole.

  Moreover, as shown in FIG. 1, the center area | region 24 of the sealing resin part 23 consists of frustoconical shape. That is, the surface (upper surface) of the central region 24 is a flat surface, and the side surface of the central region 24 has an inclined tapered shape. Since the side surface of the central region 24 is tapered as described above, the coefficient of thermal expansion generated between the central region 24 and the peripheral region 25 gradually changes. Thus, it is possible to mitigate the rapid change of the thermal expansion coefficient. As the sealing resin portion 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used.

  On the other hand, the lead frame 10 is made of a metal material such as copper, copper alloy, 42 alloy (Ni 42% Fe alloy) as a whole. The die pad 15 and the lead portion 16 of the lead frame 10 are each formed by, for example, etching processing using one metal substrate made of the above-described metal material.

  As shown in FIGS. 1 and 4, the die pad 15 has a circular shape when viewed from the front surface side, and also has a circular shape when viewed from the back surface side. As shown in FIG. 2, the entire back surface 15 b of the die pad 15 is exposed outside the sealing resin portion 23. On the other hand, the surface 15 a of the die pad 15 is a mounting surface of the semiconductor element 21 and is completely covered in the central region 24 of the sealing resin portion 23.

  Each lead portion 16 has a strip shape extending radially outward from the die pad 15, and the adjacent lead portions 16 are electrically insulated from each other. Each lead portion 16 has an internal terminal 17 to which the bonding wire 22 is connected, and an external terminal 18 provided on the outer side in the circumferential direction of the internal terminal 17 and exposed to the outside. In this case, each lead portion 16 has two external terminals 18. That is, each lead portion 16 has an upper terminal 18 a provided on the front surface side of each lead portion 16 and a lower terminal 18 b provided on the back surface side of each lead portion 16.

  As shown in FIGS. 5 and 6, each of the external terminals 18 (upper terminal 18 a and lower terminal 18 b) can be provided with a solder ball 41. FIG. 5 shows an example in which the solder ball 41 is provided on the upper terminal 18a, and FIG. 6 shows an example in which the solder ball 41 is provided on the lower terminal 18b. As shown in FIG. 5, when the solder balls 41 are provided on the upper terminals 18a, the height of each solder ball 41 is higher than the height of the central region 24 (the height from the surface 16a of the lead portion 16). It is preferable. In the present embodiment, as described above, the thickness of the central region 24 of the sealing resin portion 23 is larger than the thickness of the peripheral region 25. Thereby, the solder ball 41 can be provided on the upper terminal 18 a on the peripheral region 25, and as a result, the thickness of the entire semiconductor device 20 including the solder ball 41 can be reduced.

As shown in FIGS. 3 and 4, the external terminals 18 (upper terminals 18 a and lower terminals 18 b) of the plurality of lead portions 16 are arranged on the circumference as viewed from above. That is, as shown in FIG. 3, the upper terminal 18a, of the two circumference C ₁ and C ₂ are arranged on one of the circumference, and a plurality of upper terminals 18a are arranged in a staggered manner ing. Circumference C ₁ and C ₂ are in a concentric relationship with each other, their diameter is larger circumference C _1. In order to arrange a plurality of upper terminal 18a more densely, the shape of each upper terminal 18a is preferably wide as each approach the center of the circle C ₁ and C ₂ is the narrows shape. Examples of the shape of the upper terminal 18a include a trapezoidal shape as shown in FIG. For the same reason, the size of the upper terminal 18a disposed on the inner side of the circumference C ₂ is preferably smaller than the size of the upper terminal 18a disposed on the outside of the circumference C _1.

Similarly, the back surface of the semiconductor device 20 shown in FIG. 4, the lower terminal 18b, of the two circumferential C ₃ and C ₄ are arranged on either on the circumference, a plurality of lower terminal 18b is Arranged in a staggered pattern. Further, the circumferences C ₃ and C ₄ are concentric with each other, and the diameter of the circumference C ₃ is larger. Similarly, the shape of each lower terminal 18b, preferably in the shape in which the width is narrowed toward the center of the circumference C ₃ and C _4, respectively, the size of the lower terminal 18b which is disposed inside the circumference C ₄ Saga, is preferably smaller than the size of the lower terminal 18b disposed outside of the circumference C _3. The arrangement position of the external terminal 18 (upper terminal 18a and lower terminal 18b) is not limited to this. For example, the external terminal 18 (upper terminal 18a and lower terminal 18b) has one or more circumferences. It is also possible to arrange it above.

  On the other hand, as shown in FIGS. 1 and 3, a suspension lead 19 having an external terminal 29 is connected to the die pad 15. The suspension leads 19 are respectively provided at the four corners of the die pad 15 and extend radially from the die pad 15. The external terminals 29 of the suspension leads 19 include an upper terminal 29a (see FIGS. 1 and 3) provided on the front side of each suspension lead 19 and a lower terminal 29b (see FIG. 4) provided on the back side of each suspension lead 19. For example). The external terminals 29 (upper terminal 29a and lower terminal 29b) can be used as, for example, a ground (GND) terminal. With this configuration, the suspension lead 19 and the external terminal 29 can be used effectively. Note that the number of the suspension leads 19 is not limited to four, and may be other than four, for example, two.

  In FIGS. 1 and 2, various semiconductor elements generally used in the past can be used as the semiconductor element 21. The semiconductor element 21 has a plurality of terminal portions 21a to which bonding wires 22 are attached. The semiconductor element 21 is fixed to the surface 15a of the die pad 15 by, for example, die bonding paste.

  Each bonding wire 22 is made of a material having good conductivity, such as gold, and one end thereof is connected to the terminal portion 21 a of the semiconductor element 21 and the other end is connected to the internal terminal 17 of the lead portion 16. .

Method for Manufacturing Semiconductor Device Next, a method for manufacturing the semiconductor device 20 shown in FIGS. 1 to 4 will be described with reference to FIGS. 7 (a)-(d) and FIGS. 8 (a)-(f). In the following, a process of manufacturing a plurality of semiconductor devices 20 from one metal substrate 11 will be described. However, the present invention is not limited to this, and one semiconductor device 20 can be manufactured from one metal substrate 11. It is.

  First, as shown in FIG. 7A, a metal substrate 11 constituting the lead frame 10 is prepared. As the metal substrate 11, a substrate made of copper, copper alloy, 42 alloy (Ni 42% Fe alloy) or the like can be used as described above. In addition, it is preferable to use what the metal substrate 11 performed the degreasing | defatting etc. on both surfaces, and performed the washing process.

  Next, a photosensitive resist is applied to the front and back surfaces of the metal substrate 11, dried, exposed through a desired photomask, and then developed to form etching resist layers 32 and 33 (FIG. 7B). ). In addition, a conventionally well-known thing can be used as a photosensitive resist.

  Next, the etching resist layers 32 and 33 are used as an anticorrosion film, and the metal substrate 11 is etched with an etching solution (FIG. 7C). The corrosive liquid can be appropriately selected according to the material of the metal substrate 11 to be used. For example, when copper is used as the metal substrate 11, an aqueous ferric chloride solution is usually used and sprayed from both surfaces of the metal substrate 11. It can be performed by etching.

  Next, the etching resist layers 32 and 33 are peeled and removed. Thus, the lead frame 10 having the die pad 15 and the plurality of lead portions 16 arranged around the die pad 15 is obtained (FIG. 7D).

  The lead frame 10 thus obtained is a multi-faced lead frame having a plurality of die pads 15 and a plurality of lead portions 16. The plurality of die pads 15 and the plurality of lead portions 16 are connected to each other through a tie bar 34 (FIG. 8A).

  Next, the semiconductor element 21 is mounted on the surface 15 a of the die pad 15 of the lead frame 10. In this case, the semiconductor element 21 is mounted on the surface 15a of the die pad 15 and fixed using a die bonding paste (die attach step) (FIG. 8B).

  Next, each terminal portion 21a of the semiconductor element 21 and the internal terminal 17 of each lead portion 16 are electrically connected to each other by a bonding wire 22 (wire bonding step) (FIG. 8C).

  Next, the sealing resin portion 23 is formed by performing injection molding or transfer molding of a thermosetting resin or thermoplastic resin on the lead frame 10 using the mold 35 (FIG. 8D). As a result, the lead frame 10, the semiconductor element 21, and the bonding wire 22 are sealed. At this time, the central region 24 is formed around the semiconductor element 21 and the semiconductor element 21, and the peripheral region 25 is formed at the periphery of the central region 24.

  Next, the lead frame 10 is separated for each semiconductor element 21 by dicing the sealing resin portion 23 between the semiconductor elements 21 (FIG. 8E). At this time, the lead frame 10 is first placed and fixed on the dicing tape 37, and then the lead frame 10 and the sealing resin portion 23 between the semiconductor elements 21 are rotated while rotating a blade 38 made of, for example, a diamond grindstone. Disconnect.

  In this way, the semiconductor device 20 shown in FIGS. 1 to 4 can be obtained (FIG. 8F).

Operation and Effect of the Present Embodiment Next , the operation of the present embodiment having such a configuration will be described with reference to FIG. FIG. 9 is a cross-sectional view showing a state where the semiconductor device according to the present embodiment is mounted on a mounting substrate.

  That is, as shown in FIG. 9, the semiconductor device 20 according to the present embodiment is arranged and mounted on the mounting substrate 45. In this case, the semiconductor device 20 is fixedly mounted on the mounting substrate 45 by the solder balls 41 provided on the lower terminals 18 b of the lead parts 16 and the solder parts 42 provided on the back surface 15 b of the die pad 15. The mounting substrate 45 is mainly made of glass epoxy resin.

  By the way, it is conceivable that various heats are applied to the semiconductor device 20 depending on the usage environment after being mounted on the mounting substrate 45 by soldering or after being mounted on the mounting substrate 45. In this case, if the thermal expansion coefficient of the entire semiconductor device 20 is different from the thermal expansion coefficient of the mounting substrate 45, thermal stress is generated due to the difference in thermal expansion coefficient between the semiconductor device 20 and the mounting substrate 45. As a result, the solder balls 41 and the solder portions 42 located between the semiconductor device 20 and the mounting substrate 45 may be damaged.

In general, the thermal expansion coefficient of the lead frame 10 is relatively close to the thermal expansion coefficient of the mounting substrate 45. On the other hand, the thermal expansion coefficient of the sealing resin portion 23 is smaller than the thermal expansion coefficient of the lead frame 10. As an example (although not limited thereto), the thermal expansion coefficients of the lead frame 10 made of copper, the mounting substrate 45 mainly made of glass epoxy resin, and the sealing resin portion 23 made of epoxy resin are about 17 respectively. It is * 10 < ^-6 > (/ K), about 16 * 10 < ^-6 > (/ K), and about 10 * 10 < ^-6 > (/ K). The thermal expansion coefficient of the semiconductor element 21 made of Si is about 3.5 × 10 ⁻⁶ (/ K).

  Therefore, the larger the proportion of the sealing resin portion 23 in the semiconductor device 20, the more the thermal expansion coefficient of the entire semiconductor device 20 tends to deviate from the thermal expansion coefficient of the mounting substrate 45. On the other hand, in the present embodiment, by making the thickness of the central region 24 of the sealing resin portion 23 thicker than the peripheral region 25 (that is, making the peripheral region 25 thinner), the sealing having a relatively low thermal expansion coefficient. The volume of the stop resin portion 23 is reduced. As a result, the thermal expansion coefficient of the entire semiconductor device 20 can be brought close to the thermal expansion coefficient of the mounting substrate 45, so that thermal stress when heat is applied to the semiconductor device 20 is reduced, and mounting reliability is improved. Can do.

  Further, according to the present embodiment, the external terminals 18 (the upper terminals 18a and the lower terminals 18b) of the plurality of lead portions 16 are arranged on the circumference as viewed from above. Therefore, the thermal stress caused by the difference in thermal expansion between the semiconductor device 20 and the mounting substrate 45 is applied evenly to the solder balls 41 provided on the external terminals 18, and the specific solder balls 41 are It can be prevented from being damaged.

  Further, according to the present embodiment, since the back surface 15b of the die pad 15 is exposed outside the sealing resin portion 23, the solder portion 42 is provided on the entire back surface 15b, and the die pad 15 is attached to the mounting substrate 45. Can be attached. Further, the heat from the semiconductor element 21 can be radiated from the back surface 15 b of the die pad 15. Furthermore, since the die pad 15 has a circular shape, when heat is applied to the semiconductor device 20, thermal stress due to the difference in thermal expansion coefficient between the semiconductor device 20 and the mounting substrate 45 is uniformly distributed in the circumferential direction. Therefore, thermal stress does not concentrate on a specific portion of the solder portion 42 provided on the back surface 15b of the die pad 15, and damage to the solder portion 42 can be prevented.

  Furthermore, according to the present embodiment, in the peripheral region 25 of the sealing resin portion 23, each lead portion 16 is exposed on the surface side, and the upper terminal 18a is also provided on the surface side of each lead portion 16. . Thus, the test of the semiconductor device 20 can be performed using only the upper terminal 18a, and there is no possibility of damaging the lower terminal 18b when the test of the semiconductor device 20 is performed. Furthermore, since the solder balls 41 can be provided also on the surface side of the lead portion 16, the mounting method of the semiconductor device 20 is diversified. Furthermore, the semiconductor device 20 including the solder balls 41 can be thinned.

Modification of the semiconductor device Next, FIGS. 10 to 32, will be described various modified examples of the semiconductor device according to the present invention. 10 to 32, the same parts as those of the embodiment shown in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  10 and 11 show a semiconductor device 20A according to a modification of the present embodiment. That is, FIG. 10 is a perspective view of the semiconductor device 20A, and FIG. 11 is a cross-sectional view of the semiconductor device 20A. In the semiconductor device 20A shown in FIGS. 10 and 11, unlike the embodiment shown in FIGS. 1 to 9, the central region 24 of the sealing resin portion 23 has a cylindrical shape. That is, the upper surface of the central region 24 is flat, and the side surface of the central region 24 is perpendicular to the surface 16 a of the lead portion 16. Even in the case of such a configuration, it is possible to obtain substantially the same effect as that of the embodiment shown in FIGS. 1 to 9 described above. In addition, the shape of the central region 24 may be a polygonal column shape or a truncated polygonal pyramid shape. In addition, it is preferable that the part concerning the boundary part of the center area | region 24 and the peripheral area | region 25 among the sealing resin parts 23 is made into a taper or round shape. Since the thermal expansion coefficient generated between the central region 24 and the peripheral region 25 is gradually changed, the rapid change of the thermal expansion coefficient between the central region 24 and the peripheral region 25 is alleviated, and the warp is reduced. This is because the distortion can be prevented and concentration of distortion can be avoided.

  12 and 13 show a semiconductor device 20B according to another modification. That is, FIG. 12 is a perspective view of the semiconductor device 20B, and FIG. 13 is a cross-sectional view of the semiconductor device 20B. In the semiconductor device 20B shown in FIGS. 12 and 13, unlike the embodiment shown in FIGS. 1 to 9, the central region 24 of the sealing resin portion 23 has a dome shape. That is, the entire surface of the central region 24 is a curved surface. In this case, the surface of the central region 24 may be a part of a spherical surface. Even in such a configuration, it is possible to obtain substantially the same effect as that of the above-described embodiment shown in FIGS.

  On the other hand, FIGS. 14 to 19 show semiconductor devices 20C, 20D, and 20E according to other modifications. 14 is a perspective view of the semiconductor device 20C, and FIG. 15 is a cross-sectional view of the semiconductor device 20C. FIG. 16 is a perspective view of the semiconductor device 20D, and FIG. 17 is a cross-sectional view of the semiconductor device 20D. 18 is a perspective view of the semiconductor device 20E, and FIG. 19 is a cross-sectional view of the semiconductor device 20E.

  14 to 19, unlike the embodiment shown in FIGS. 1 to 9, the upper terminal 18 a is not provided on the surface side of each lead portion 16, and the upper terminal is also provided on the surface side of the suspension lead 19. 29a is not provided. Further, in FIGS. 14 to 19, the diameter of the central region 24 is the same as the length of one side of the semiconductor devices 20C, 20D, and 20E or slightly smaller than the length of one side of the semiconductor devices 20C, 20D, and 20E. ing. With this configuration, in addition to the effects of the embodiment shown in FIGS. 1 to 9 described above, the overall size of the semiconductor devices 20C, 20D, and 20E with respect to the size of the semiconductor element 21 can be configured compactly. Is obtained. The shape of the central region 24 may be a frustoconical shape as shown in FIGS. 14 and 15, may be a cylindrical shape as shown in FIGS. 16 and 17, or is shown in FIGS. 18 and 19. It is good also as a dome shape.

  FIG. 20 shows a semiconductor device 20F according to still another modification. In FIG. 20, a planar annular ring stiffener 52 is bonded to the upper terminal 18 a of each lead portion 16 via an adhesive layer 51. Further, a heat radiating fin 54 is mounted on the ring stiffener 52 via an adhesive layer 53. The ring stiffener 52 can be made of, for example, copper or a 42 alloy, and the heat radiation fin 54 can be made of, for example, aluminum. With such a configuration, heat from the semiconductor element 21 can be released through the heat radiating fins 54, so that the reliability of the semiconductor device 20F against heat can be further improved.

  FIG. 21 shows a semiconductor device 20G according to another modification. In FIG. 21, electronic components 57 and 58 are mounted on the upper terminals 18 a of the lead portions 16 via solder portions or conductive paste portions 56. Examples of such electronic components 57 and 58 include a capacitor, a resistance element, and a ring interposer. The electronic parts 57 and 58 may be made of the same kind of electronic parts or different kinds of electronic parts. With such a configuration, the electronic components 57 and 58 can be arranged using the space on the peripheral region 25, and the semiconductor device 20G can be made compact.

  FIG. 22 and FIG. 23 are plan views showing semiconductor devices 20H and 20I according to a modification of the present embodiment, respectively, and are diagrams in which portions above the surface of the lead portion 16 are omitted (corresponding to FIG. 3). Figure). In the semiconductor devices 20H and 20I shown in FIGS. 22 and 23, the shape of the front surface 15a of the die pad 15 and the shape of the back surface 15b are different from each other in the embodiment shown in FIGS. That is, in FIG. 22, the die pad 15 has a circular shape when viewed from the front surface 15a side and a rectangular shape when viewed from the back surface 15b side. In FIG. 23, the die pad 15 has a rectangular shape when viewed from the front surface 15a side and a circular shape when viewed from the back surface 15b side. 22 and FIG. 23, since the sealing resin portion 23 enters the center side from the periphery of the die pad 15, the adhesion between the die pad 15 and the sealing resin portion 23 can be improved.

FIG. 24 is a plan view showing a semiconductor device 20J according to another modification, in which a portion above the surface of the lead portion 16 is omitted (corresponding to FIG. 3). In the semiconductor device 20J shown in FIG. 24, unlike the embodiment shown in FIGS. 1 to 9, each suspension lead 19 extends from the die pad 15 toward the center of the four sides of the semiconductor device 20J. Further, the upper terminal 18 a is not provided on the surface side of each lead portion 16. The internal terminal 17 of each lead portion 16 is disposed on one of the two circumferences C ₅ and C ₆ . In this case, since the suspension leads 19 are not provided at the four corners of the semiconductor device 20J, the number of the lead portions 16 can be increased, and the number of pins of the semiconductor device 20J can be increased.

  FIG. 25 is a plan view showing a modification of the suspension lead 19 of the lead frame 10. In FIG. 25, recesses 61 and 62 into which the sealing resin portion 23 enters are formed on the front and back surfaces of the external terminal 29 in the suspension lead 19. As shown in FIG. 25, the arrangement positions of the concave portion 61 on the front surface and the concave portion 62 on the back surface of the suspension lead 19 are different from each other as viewed from the plane, and are alternately arranged. These recesses 61 and 62 are each formed by half etching when the lead frame 10 is manufactured using the metal substrate 11 (see FIGS. 7A to 7D). With such a configuration, the sealing resin portion 23 enters the recesses 61 and 62, so that the connection strength between the suspension lead 19 and the sealing resin portion 23 can be increased.

  26 and 27 are cross-sectional views showing semiconductor devices 20K and 20L according to a modification of the present embodiment, respectively. 26 and 27, unlike the embodiment shown in FIGS. 1 to 9, the back surface 15b of the die pad 15 is not exposed outside the sealing resin portion 23 and is completely covered by the sealing resin portion 23. It has been broken. Thus, by preventing the back surface 15b of the die pad 15 from being exposed outside the sealing resin portion 23, the adhesion between the die pad 15 and the sealing resin portion 23 can be enhanced.

  28 and 29 are cross-sectional views showing semiconductor devices 20M and 20N according to other modifications, respectively. 28 and 29, the die pad 15 is thinner than the embodiment shown in FIGS. That is, the surface 15 a of the die pad 15 is located on the back side (that is, the lower position) than the surface 16 a of each lead portion 16. On the other hand, the back surface 15 b of the die pad 15 is exposed outside the sealing resin portion 23. Thus, by reducing the thickness of the die pad 15 and positioning the front surface 15a of the die pad 15 on the back surface side, the semiconductor devices 20M and 20N can be configured to be thin.

  30 and 31 are cross-sectional views showing semiconductor devices 20P and 20Q according to other modified examples, respectively. 30 and 31, unlike the embodiment shown in FIGS. 1 to 9, an annular flange 47 is provided along the periphery of the surface 15 a of the die pad 15. The semiconductor element 21 is accommodated inside the annular flange 47. By providing the flange 47 on the periphery of the surface 15a of the die pad 15 in this way, it is possible to prevent the die pad 15 from sagging or deforming.

  FIG. 32 is a cross-sectional view showing a semiconductor device 20R according to still another modification. In FIG. 32, a stepped portion 48 is formed between the internal terminal 17 and the lower terminal 18 b of each lead portion 16. Such a step portion 48 is thinner than the thickness of the lead portion 16 in the lower terminal 18b and thicker than the thickness of the lead portion 16 in the internal terminal 17, and is formed by etching each lead portion 16 in two steps. Can do. Thereby, the thickness of the lead part 16 in the vicinity of the lower terminal 18b can be increased, and the strength of the lead part 16 in the vicinity of the lower terminal 18b can be increased. On the other hand, since the thickness of the lead portion 16 is reduced in the vicinity of the internal terminal 17, the internal terminal 17 can be fine pitched. In FIG. 32, the surface 15a of the die pad 15 is positioned on the back side (that is, the lower position) than the surface 16a of each lead portion 16, and the semiconductor device 20R is made thinner.

  The semiconductor devices 20K, 20M, 20P, and 20R shown in FIGS. 26, 28, 30, and 32 described above correspond to the semiconductor device 20 shown in FIGS. 1 to 4 in the configuration of the central region 24. . On the other hand, in the semiconductor devices 20L, 20N, and 20Q shown in FIGS. 27, 29, and 31, the configuration of the central region 24 corresponds to the semiconductor device 20A shown in FIGS.

  It is also possible to appropriately combine a plurality of constituent elements disclosed in the embodiment and the modification examples as necessary. Or you may delete a some component from all the components shown by the said embodiment and modification.

DESCRIPTION OF SYMBOLS 10 Lead frame 15 Die pad 16 Lead part 17 Internal terminal 18 External terminal 18a Upper terminal 18b Lower terminal 19 Hanging lead 20, 20A-20R Semiconductor device 21 Semiconductor element 22 Bonding wire (conductive part)
23 Sealing resin part 24 Central area 25 Peripheral area 29 External terminal 29a Upper terminal 29b Lower terminal 41 Solder ball 42 Solder part 45 Mounting substrate 47 Flange 48 Step part 54 Radiation fin 57, 58 Electronic component 61, 62 Recessed part

Claims (18)

A lead frame having a die pad and a plurality of lead portions disposed around the die pad;
A semiconductor element mounted on a die pad of a lead frame;
A conductive portion that electrically connects the lead portion of the lead frame and the semiconductor element;
A lead frame, a semiconductor element, and a sealing resin portion for sealing the conductive portion;
The sealing resin portion has a semiconductor element and a central region provided around the semiconductor element, and a peripheral region located at the periphery of the central region,
A semiconductor device characterized in that the thickness of the central region is thicker than the thickness of the peripheral region.   Each lead portion has a strip shape extending radially outward from the die pad, and has an external terminal exposed to the outside, and the external terminals of the plurality of lead portions are on at least one circumference when viewed from above. The semiconductor device according to claim 1, wherein the semiconductor device is disposed on the substrate.   Each lead part has two external terminals, one external terminal is composed of an upper terminal provided on the front side of each lead part, and the other external terminal is a lower part provided on the back side of each lead part 3. The semiconductor device according to claim 2, comprising a terminal.   4. The semiconductor device according to claim 3, wherein a step portion is formed between the internal terminal and the lower terminal of each lead portion.   4. The semiconductor device according to claim 3, wherein a solder ball is provided on an upper terminal of at least one lead portion.   4. The semiconductor device according to claim 3, wherein a radiation fin is mounted on an upper terminal of at least one lead portion.   4. The semiconductor device according to claim 3, wherein an electronic component is mounted on an upper terminal of at least one lead portion.   8. The semiconductor device according to claim 1, wherein each lead portion is exposed to a front surface side in a peripheral region of the sealing resin portion. 9.   The central region of the sealing resin portion has a truncated cone shape, a columnar shape, a polygonal column shape, a truncated polygonal pyramid shape, or a dome-shaped shape, according to any one of claims 1 to 7. Semiconductor device.   The semiconductor device according to claim 1, wherein the die pad has a circular shape when viewed from the front side.   The semiconductor device according to claim 1, wherein the die pad has a circular shape when viewed from the back side.   12. The semiconductor device according to claim 10, wherein the shape of the front surface and the shape of the back surface of the die pad are different from each other.   The semiconductor device according to claim 1, wherein a suspension lead having an external terminal is connected to the die pad.   14. A recess into which the sealing resin portion enters is formed on each of the front and back surfaces of the suspension lead, and the arrangement positions of the recesses on the front surface and the rear surface of the suspension lead are different from each other when viewed from above. The semiconductor device described.   15. The semiconductor device according to claim 1, wherein the back surface of the die pad is exposed outside the sealing resin portion.   The semiconductor device according to claim 1, wherein the back surface of the die pad is not exposed to the outside of the sealing resin portion.   17. The semiconductor device according to claim 1, wherein a surface of the die pad is positioned on a back surface side from a surface of each lead portion.   The semiconductor device according to claim 1, wherein a flange is provided along a peripheral surface of the die pad.

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