JPS62145754A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62145754A
JPS62145754A JP60285505A JP28550585A JPS62145754A JP S62145754 A JPS62145754 A JP S62145754A JP 60285505 A JP60285505 A JP 60285505A JP 28550585 A JP28550585 A JP 28550585A JP S62145754 A JPS62145754 A JP S62145754A
Authority
JP
Japan
Prior art keywords
resin
leads
molded
pellet
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60285505A
Other languages
Japanese (ja)
Inventor
Yosaburo Kiyota
清田　與三郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60285505A priority Critical patent/JPS62145754A/en
Publication of JPS62145754A publication Critical patent/JPS62145754A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To improve the reliability of a semiconductor device by providing an oxide film inside a semiconductor pellet in which leads for connecting the pellet are resin-molded to prevent atmospheric air from entering into the resin. CONSTITUTION:A lead frame 1 is integrally formed of a plurality of leads 2 dispose radially, a flat plate 3 of the ends of the leads 2 and a frame 4 for bundling it. Au-plated layers 6 are formed on the plate 3 and at the endmost ends of the leads 2, and oxide films 8 are formed over the front and back surfaces of a region 7. The films 8 are formed by heating the region 7 of the frame 1 at approx. 400 deg.C in O2 atmosphere. The frame 1 is molded with resin 11 from the front and back surfaces of the leads 2 at the portion designated by broken lines at a pellet 9 and the periphery of the pellet 9. Thus, finely irregular portion is formed on the surface, the molded resin 11 is intruded into the irregular portion to be bonded, mechanically connected and sealed. Accordingly, no gap is formed in the molded portion of the resin 11 and the leads 2 to shut off the invasion of the atmospheric air.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係り、特に半導体ペレットを搭載
するリードフレームの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to the structure of a lead frame on which a semiconductor pellet is mounted.

〔発明の背景〕[Background of the invention]

半導体装置は、その電気的動作をする半導体ペレットが
微小なため、パッケージ化され外的障害防止とともにそ
の取扱いを容易にしている。そして、前記パッケージに
は半導体ペレットの各電極に接続されたリードが突出し
ている。In semiconductor devices, the semiconductor pellets that perform electrical operations are minute, so they are packaged to prevent external damage and to facilitate handling. Leads connected to each electrode of the semiconductor pellet protrude from the package.

具体的な例としては、デュアルイン型のレジンモールド
半導体装置があり、その製造においては、まず放射形状
に配置される複数のリードと、これらリードの先端部に
配置される平板と、これらを結束するフレームとからな
るリードフレームを用意し、前記平板上に半導体ペレッ
トをダイボンドした後、半導体ペレットの各電極とこれ
らに対応する他のリードの先端部をワイヤボンディング
でそれぞれ接続する。そして、前記半導体ペレットとそ
の周辺部をリードフレームの表裏面からレジンをモール
ドすることにより被覆し、前記リードフレームのフレー
ム部のみをプレス等で除去するとともに、リード部を一
定の方向に折曲げることにより完成する。A specific example is a dual-in type resin-molded semiconductor device. In its manufacture, first, a plurality of leads are arranged in a radial shape, a flat plate is arranged at the tips of these leads, and these are tied together. After a semiconductor pellet is die-bonded onto the flat plate, each electrode of the semiconductor pellet and the corresponding tip end of another lead are connected by wire bonding. Then, the semiconductor pellet and its surrounding parts are covered by molding resin from the front and back surfaces of the lead frame, and only the frame part of the lead frame is removed by a press or the like, and the lead part is bent in a certain direction. Completed by

なお、このような半導体装置の構造は、例えば特公昭５
４−５２６４号公報および特公昭５６−４３８５４号公
報等に詳記されている。　　　′しかしながら、９のよ
うに構成される半導体装置は、レジンの各リード部取出
口において、レジンと各リードとが十分に接着され密着
されているものの、実際にはレジンと各リードとのモー
ルド部分に幅が数庫程度の微小な隙間を有している。Note that the structure of such a semiconductor device is, for example,
It is described in detail in Japanese Patent Publication No. 4-5264 and Japanese Patent Publication No. 56-43854. 'However, in the semiconductor device configured as shown in 9, although the resin and each lead are sufficiently bonded and tightly attached at each lead outlet of the resin, in reality, the molded portion between the resin and each lead is There is a tiny gap about the width of a few cabinets.

このため、この微小な隙間から外気が侵入し、レジン内
のリードを腐蝕させ、さらにこの腐蝕により隙間を一層
拡大させて外気の侵入、腐蝕を促進させる結果となり、
長期間の使用に対して信頼性を損なうという問題があっ
た。For this reason, outside air enters through this minute gap, corroding the leads inside the resin, and this corrosion further expands the gap, causing outside air to enter and accelerate corrosion.
There was a problem in that the reliability deteriorated after long-term use.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、レジン内への外気の侵入を防止し、信
頼性を向上させることができる半導体装置を提供するこ
とにある。An object of the present invention is to provide a semiconductor device that can prevent outside air from entering into the resin and improve reliability.

〔発明の概要〕[Summary of the invention]

本発明の一実施例によれば、半導体ペレットを接続する
リードの少なくともレジンモールドされる内側に酸化膜
を設けることにより、リードとレジンとが確実に密着さ
れた半導体装置が提供される。According to one embodiment of the present invention, by providing an oxide film at least on the resin-molded inside of the lead connecting the semiconductor pellet, a semiconductor device in which the lead and the resin are reliably bonded is provided.

〔発明の実施例〕 次に図面を用いて本発明の実施例を詳細に説明する。[Embodiments of the invention] Next, embodiments of the present invention will be described in detail using the drawings.

第１図は本発明による半導体装置の一実施例を説明する
ためのリードフレームの平面図である。FIG. 1 is a plan view of a lead frame for explaining one embodiment of a semiconductor device according to the present invention.

同図において、リードフレーム１は、放射形状に配置さ
れる複数個のリード２と、これらのリード２の先端部に
比較的面積が大なる平板３と、これらのリード２および
平板３を結束するフレーム４とから一体的に形成されて
いる。そして、このリードフレーム１は、Ｎ　ｉ　４２
％、残りＦｅ等を含む４２７０イと称する金属板を所定
の形状にプレス成形して形成されるとともに、平板３お
よびこれらのリード２の先端部には第２図に要部断面図
で示すようにプレス段５を境界としてプレス加工が施さ
れ、その板厚ｔ、が他の部分の板厚ｔ２よりも薄くして
形成されている。さらに平板３上およびこれらのリード
２の最先端部には、第１図に示すように右方向に流れる
細かいハツチングで示す領域に厚さ約２ρ程度のＡｕメ
ッキ層６が形成゛され、さらにこれらのり−ド２の先端
部分には、左方向に流れる細かいハツチングで示す領域
７にその表裏面にわたって酸化膜８が形成されている。In the figure, a lead frame 1 includes a plurality of leads 2 arranged in a radial shape, a flat plate 3 having a relatively large area at the tips of the leads 2, and a bundle of the leads 2 and the flat plate 3. It is integrally formed with the frame 4. This lead frame 1 has N i 42
%, remaining Fe, etc., is press-molded into a predetermined shape, and the tips of the flat plate 3 and these leads 2 are coated with metal plates as shown in the cross-sectional view of main parts in FIG. Pressing is performed using the press step 5 as a boundary, and the plate thickness t is made thinner than the plate thickness t2 of other parts. Furthermore, on the flat plate 3 and at the leading edge of these leads 2, an Au plating layer 6 with a thickness of about 2ρ is formed in the area indicated by the fine hatching flowing to the right as shown in FIG. At the tip of the glue board 2, an oxide film 8 is formed over its front and back surfaces in a region 7 shown by fine hatching that flows leftward.

この酸化膜８はリードフレーム１の酸化領域７をＯ３雰
囲気中で約４００℃程度の温度で加熱することにより容
易に形成される。This oxide film 8 is easily formed by heating the oxidized region 7 of the lead frame 1 at a temperature of about 400° C. in an O3 atmosphere.

このようにして形成されたリードフレーム１は、第３図
に示すように平板３上に半導体ペレット９がＡｕ−８ｉ
共晶により固着されて搭載され、さらに半導体ペレット
９に形成された約１ｏＯｐｎ角の各電極は、これらにそ
れぞれ対応するり−ド２の最先端部に形成されたＡｕメ
ッキ層６に直径約３２ｐのＡｕ線１０がネイルヘッドボ
ンディング法により接続され、半導体ペレット９とその
周辺部を破線りで示す部分でリード２の表裏面からレジ
ン１１がモールドされている。In the lead frame 1 thus formed, as shown in FIG.
Each electrode of approximately 1o Open angle formed on the semiconductor pellet 9, which is fixed and mounted by eutectic, is attached to the Au plating layer 6 formed at the leading edge of the corresponding lead 2 with a diameter of approximately 32p. The Au wires 10 are connected by the nail head bonding method, and resin 11 is molded from the front and back surfaces of the leads 2 at the portions of the semiconductor pellet 9 and its periphery indicated by broken lines.

このようにリードフレーム１のレジン１１がモールドさ
れる内側に酸化膜８を設けたことにより、表面に微細な
凹凸が形成されるので、モールドされたレジン１１はそ
の微細な凹凸部に食い込んで接着され、機械的に結合し
て密着されることになる。したがって、レジン１１とリ
ード２とのモールド部分には隙間が発生しなくなり、外
気の侵入を遮断することができるので、レジン１１内の
リードの腐蝕を確実に防止することができる。By providing the oxide film 8 on the inside where the resin 11 of the lead frame 1 is molded, fine irregularities are formed on the surface, so the molded resin 11 bites into the fine irregularities and adheres. They will be mechanically bonded and tightly bonded. Therefore, no gap is generated between the molded portion of the resin 11 and the lead 2, and the intrusion of outside air can be blocked, so that corrosion of the lead within the resin 11 can be reliably prevented.

なお、前述した実施例においては、半導体装置としてデ
ュアルイン型のレジンモールド半導体装置を例に掲げた
場合について説明したが、本発明はこれに限定されるも
めではなく、小信号用のレジンモールド型半導体装置で
も良く、要は一端に半導体ペレットに形成された各電極
にボンディングワイヤを介して接続されるリードと、半
導体ペレットおよびこれらのリードとが梗脂モールドさ
れて構成される半導体装置であれば特に限定されるもの
ではない。In the above-described embodiments, a dual-in type resin molded semiconductor device was used as an example of the semiconductor device, but the present invention is not limited to this, and is applicable to a small signal resin molded semiconductor device. It may be a semiconductor device, as long as it has a lead connected to each electrode formed on a semiconductor pellet at one end via a bonding wire, and the semiconductor pellet and these leads are molded with tallow. It is not particularly limited.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半導体ペレットを
接続するリードの少なくともレジンモールドされる内側
に酸化膜を設けたことにより、レジンとリードとが完全
に密着され、外気の侵入を防止し、リードの腐蝕を確実
に防止することができるので、信頼性の高い半導体装置
が得られるという極めて優れた効果を有する。As explained above, according to the present invention, an oxide film is provided at least on the inside of the lead that connects the semiconductor pellet to be molded with resin, so that the resin and the lead are completely adhered to each other, preventing outside air from entering. Since corrosion of the leads can be reliably prevented, a highly reliable semiconductor device can be obtained, which is an extremely excellent effect.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ないし第４図は本発明による半導体装置の一実施
例を説明するための図である。 １・・・リードフレーム、２・・・リード、３・・・平
板、４・・・フレーム、５・・・プレス段、６・・・Ａ
ｕメッキ層、７・・・酸化領域、８・・・酸化膜、９・
・・半導体ペレット、１０・・・Ａｕ線、１１・・・レ
ジン。1 to 4 are diagrams for explaining one embodiment of a semiconductor device according to the present invention. 1... Lead frame, 2... Lead, 3... Flat plate, 4... Frame, 5... Press step, 6... A
u plating layer, 7... oxidized region, 8... oxide film, 9.
...Semiconductor pellet, 10...Au wire, 11...Resin.

Claims (1)

【特許請求の範囲】[Claims] 半導体ペレットに形成した各電極にワイヤを介して接続
させるリードと、前記半導体ペレットとリードとをモー
ルドする樹脂とからなる半導体装置において、前記リー
ドの少なくとも樹脂モールドさせる内側に酸化膜を設け
たことを特徴とする半導体装置。In a semiconductor device comprising a lead connected to each electrode formed on a semiconductor pellet via a wire, and a resin molding the semiconductor pellet and the lead, an oxide film is provided at least on the inside of the lead that is molded with the resin. Characteristic semiconductor devices.
JP60285505A 1985-12-20 1985-12-20 Semiconductor device Pending JPS62145754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60285505A JPS62145754A (en) 1985-12-20 1985-12-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60285505A JPS62145754A (en) 1985-12-20 1985-12-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62145754A true JPS62145754A (en) 1987-06-29

Family

ID=17692395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60285505A Pending JPS62145754A (en) 1985-12-20 1985-12-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62145754A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231322A (en) * 2008-03-19 2009-10-08 Renesas Technology Corp Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009231322A (en) * 2008-03-19 2009-10-08 Renesas Technology Corp Manufacturing method of semiconductor device

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