JPS6333851A - Package for ic - Google Patents
Package for icInfo
- Publication number
- JPS6333851A JPS6333851A JP17703386A JP17703386A JPS6333851A JP S6333851 A JPS6333851 A JP S6333851A JP 17703386 A JP17703386 A JP 17703386A JP 17703386 A JP17703386 A JP 17703386A JP S6333851 A JPS6333851 A JP S6333851A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- resin
- exposed
- package
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 238000007789 sealing Methods 0.000 abstract description 7
- 238000005498 polishing Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
この発明は半導体集積回路（ＩＣ）の実装技術（ＩＣパ
ッケージ）に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor integrated circuit (IC) packaging technology (IC package).
ＩＣパッケージの８０％以上はＯＩＬのような樹脂封止
パッケージである。More than 80% of IC packages are resin-sealed packages such as OIL.
第５図乃至第９図はこの種の従来例で、第９図の如きリ
ードフレーム（１）の搭載部（２）に、第６図の如く、
ＩＣ（３）をグイボンドし、第７図の如く、ＩＣ（３）
とリードフレーム（１）の端子（４）をワイヤボンドし
、第８図の如く、ＩＣ（３）とワイヤボンド部の外周を
樹脂（５）で封止し、端子（４）を独立させて第５図の
如きＩＣパッケージとして完成させている。5 to 9 show conventional examples of this type, in which a lead frame (1) as shown in FIG. 9 is mounted on a mounting portion (2) as shown in FIG. 6.
Guibond IC(3), as shown in Figure 7, IC(3)
and the terminal (4) of the lead frame (1) are wire-bonded, and as shown in Figure 8, the outer periphery of the IC (3) and the wire-bonded part is sealed with resin (5), and the terminal (4) is made independent. The IC package was completed as shown in Fig. 5.
この発明は小型化されたＩＣパッケージを提供すること
にある。The object of this invention is to provide a miniaturized IC package.
この発明の要旨とするところは、ＩＣの表面電極よりワ
イヤーを立上げると共に該ｒＣ及びワイヤーを該ワイヤ
ーの先端部のみが露呈するように樹脂封止し、該ワイヤ
ーの樹脂より露呈する部分を電極として成ることを特徴
とするＩＣパッケージである。The gist of this invention is to raise a wire from the surface electrode of an IC, seal the rC and the wire with a resin so that only the tip of the wire is exposed, and use the part of the wire exposed from the resin as an electrode. This is an IC package characterized by the following.
以下、この発明を図面に示す実施例に基づいて説明する
。The present invention will be described below based on embodiments shown in the drawings.
この発明のＩＣパッケージは、第１図の如く、ＩＣ（３
）の表面に該ＩＣ（３）の電極に接続したワイヤー（６
）を立上げ、該ＩＣ（３）及びワイヤー（６）を樹脂（
５）にて封止すると共にワイヤー（６）の先端を樹脂（
５）の表面より電極（７）として露呈せしめて成るもの
である。The IC package of this invention has an IC (3
) has a wire (6) connected to the electrode of the IC (3).
) and put the IC (3) and wire (6) into the resin (
5) and seal the tip of the wire (6) with resin (
5) is exposed from the surface as an electrode (7).
上記のようなＩＣパッケージは例えば次のように製造す
る。The above IC package is manufactured, for example, as follows.
リードフレーム（１）の搭載部（２）にＩＣ（３）をダ
イボンド、ワイヤボンドし、ＩＣ（３）のワイヤボンド
部の外周を樹脂（５）で封止したものを用いる。ここま
での製造工程は従来のものと同じである。樹脂（５）で
の封止は例えば、トランスファー成型により行う。An IC (3) is die-bonded or wire-bonded to a mounting part (2) of a lead frame (1), and the outer periphery of the wire-bonded part of the IC (3) is sealed with a resin (5). The manufacturing process up to this point is the same as the conventional one. The sealing with the resin (5) is performed, for example, by transfer molding.
つづいてＩＣ（３）の周辺部の樹脂（５）及び端子（４
）を除去する。第２図の破線Ａ−Ａの外側を除去するの
である。Next, the resin (5) and the terminal (4) around the IC (3).
) to remove. The area outside the broken line A--A in FIG. 2 is removed.
さらに樹脂（５）の表面を研磨する等して、ＩＣ（３）
の電極に接続して立上げたワイヤー（６）の上端部を露
呈せしめる。そして露呈するワイヤー（６）の上端部を
電極とする。第２図の破線Ｂ−Ｂの上方を除去するので
ある。Furthermore, by polishing the surface of the resin (5), etc., the IC (3)
The upper end of the raised wire (6) connected to the electrode is exposed. The exposed upper end of the wire (6) is then used as an electrode. The area above the broken line B--B in FIG. 2 is removed.
以上述べたようにこのＩＣパッケージではリードフレー
ム（１）の端子（４）はＩＣ（３）の電極に接続するワ
イヤー（６）を樹脂（５）でつつみこみ固定するまでの
仮配線に使用するものであって最終的に除去するもので
あるから、従来のものの如（各電極に分離している必要
はなく、ワイヤー（６）を並べてワイヤーボンドできる
第一３図の如き長板状のものでもよいし、また第４図の
如＜ＩＣ（３）をグイボンドする搭載部（２）の外周部
からなるものであって、該搭載部（２）の周囲に順序よ
くワイヤー（６）の端部をワイヤーボンドするようにし
たものでもよいのである。この場合は、樹脂（５）で封
止した後ワイヤーボンドされた搭載部（２）の周囲を切
除するのである。As mentioned above, in this IC package, the terminals (4) of the lead frame (1) are used for temporary wiring until the wires (6) connected to the electrodes of the IC (3) are wrapped in resin (5) and fixed. Since it is something that will be removed in the end, it is possible to use a conventional one (it does not need to be separated into each electrode, but a long plate-like one as shown in Fig. 13 where the wires (6) can be lined up and wire-bonded). Also, as shown in Fig. 4, it consists of the outer periphery of the mounting part (2) to which the IC (3) is firmly bonded, and the ends of the wires (6) are arranged in order around the mounting part (2). It may also be wire-bonded. In this case, the periphery of the wire-bonded mounting portion (2) is cut off after sealing with resin (5).
上記のように本発明によるＩＣパンケージは、ＩＣ（３
）の表面電極より立上げるワイヤー（６）の封止（５）
よりの露呈部分を電極としているものであって、従来の
この種のものの如く封止樹脂（５）より突出する端子を
用いておらず、また封止樹脂も端子を保持する必要がな
く小さくなっているので小型化されているのである。As described above, the IC package according to the present invention includes an IC (3
) Sealing of the wire (6) raised from the surface electrode (5)
The exposed part of the wire is used as an electrode, and there is no terminal protruding from the sealing resin (5) as in conventional products of this kind, and the sealing resin is also smaller as there is no need to hold the terminal. Because of this, it has been made smaller.
第１図乃至第４図に示すこの発明の一実施例を示す図で
、第１図及び第２図は断面図、第３図及び第４図は平面
図である。第５図乃至第９図は従来例を示す図で、第５
図は断面図、第６図及び第７図は側面図、第８図は断面
図、第９図は平面図である。
（１）・・・リードフレーム、（２）・・・搭載部、（
３）・・・ＩＣ１（４）・・・端子、（５）・・・樹脂
、（６）・・・ワイヤー、（７）・・・電極。1 to 4 are views showing one embodiment of the present invention, in which FIGS. 1 and 2 are sectional views, and FIGS. 3 and 4 are plan views. 5 to 9 are diagrams showing conventional examples.
The figure is a sectional view, FIGS. 6 and 7 are side views, FIG. 8 is a sectional view, and FIG. 9 is a plan view. (1)...Lead frame, (2)...Mounting section, (
3)...IC1 (4)...terminal, (5)...resin, (6)...wire, (7)...electrode.
Claims (1)
ＩＣ及びワイヤーを該ワイヤーの先端部のみが露呈する
ように樹脂封止し、該ワイヤーの樹脂より露呈する部分
を電極として成ることを特徴とするＩＣパッケージ。(1) A wire is raised from the surface electrode of the IC, and the IC and the wire are sealed with resin so that only the tip of the wire is exposed, and the portion of the wire exposed from the resin is used as an electrode. IC package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17703386A JPS6333851A (en) | 1986-07-28 | 1986-07-28 | Package for ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17703386A JPS6333851A (en) | 1986-07-28 | 1986-07-28 | Package for ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6333851A true JPS6333851A (en) | 1988-02-13 |
Family
ID=16023972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17703386A Pending JPS6333851A (en) | 1986-07-28 | 1986-07-28 | Package for ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6333851A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0771029A3 (en) * | 1995-10-24 | 1997-07-30 | Oki Electric Ind Co Ltd | Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same |
| WO2001088975A3 (en) * | 2000-05-13 | 2002-06-20 | Micronas Gmbh | Method for producing a component |
-
1986
- 1986-07-28 JP JP17703386A patent/JPS6333851A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0771029A3 (en) * | 1995-10-24 | 1997-07-30 | Oki Electric Ind Co Ltd | Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same |
| US5864174A (en) * | 1995-10-24 | 1999-01-26 | Oki Electric Industry Co., Ltd. | Semiconductor device having a die pad structure for preventing cracks in a molding resin |
| EP1039541A1 (en) * | 1995-10-24 | 2000-09-27 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| US6177725B1 (en) | 1995-10-24 | 2001-01-23 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| EP1168440A1 (en) * | 1995-10-24 | 2002-01-02 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| US6459145B1 (en) | 1995-10-24 | 2002-10-01 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor |
| US6569755B2 (en) | 1995-10-24 | 2003-05-27 | Oki Electric Industry Co., Ltd. | Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same |
| WO2001088975A3 (en) * | 2000-05-13 | 2002-06-20 | Micronas Gmbh | Method for producing a component |
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