JPS62119933A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS62119933A
JPS62119933A JP60260598A JP26059885A JPS62119933A JP S62119933 A JPS62119933 A JP S62119933A JP 60260598 A JP60260598 A JP 60260598A JP 26059885 A JP26059885 A JP 26059885A JP S62119933 A JPS62119933 A JP S62119933A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
insulator
chip
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60260598A
Other languages
Japanese (ja)
Inventor
Kiichi Tanaka
田中　喜一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP60260598A priority Critical patent/JPS62119933A/en
Publication of JPS62119933A publication Critical patent/JPS62119933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To limit the deformation of long junction wire by a method wherein an insulator higher than the surface level of IC chip is provided on the periphery of an island. CONSTITUTION:An insulator 5 higher than the surface level of an IC chip 3 is provided on the periphery of an island 1 of a leadframe. Thus a junction wire 6 between a lead 2 and a pad 4, even if hangs down, can be held by the insulator 5, relieving the need to limit the length of the junction wire.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路装置、特に集積回路チップの端子（
以下パッドと称す）とリードフレームのリードとの間を
長いボンディング線で接続することが必要な集積回路装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuit devices, particularly terminals of integrated circuit chips (
The present invention relates to an integrated circuit device in which it is necessary to connect a pad (hereinafter referred to as a pad) and a lead of a lead frame with a long bonding wire.

〔従来の技術〕[Conventional technology]

従来の集積回路装置では、第２図の断面図に示すように
、リードフレームのアイランド１に載置した集積回路チ
ップ３のパッド４とリードフレームのリード２との間は
ボンディング線６で直接結ばれている。In the conventional integrated circuit device, as shown in the cross-sectional view of FIG. 2, the pads 4 of the integrated circuit chip 3 placed on the island 1 of the lead frame and the leads 2 of the lead frame are directly connected by bonding wires 6. It is.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の従来の集積回路装置では、第２図に示されている
ように、集積回路チップ３とリード２との間を接続して
いるボンディング線６の中央部が自重によって、同図６
′のように垂れ下ってチップ３と接脂しテップの基板電
位となった９、樹脂モールドパッケージにおいては、樹
脂封入時の樹脂の流れにより、ボンディング線同士が接
触する場合がある。そのため、ボンディング線の長さが
厳しく制限されるため、集積回路チップの大きさによシ
それぞれ異なった大きさの多種類のリードフレームを用
意する必要がめるという欠点がある。In the above-mentioned conventional integrated circuit device, as shown in FIG. 2, the center portion of the bonding wire 6 connecting the integrated circuit chip 3 and the leads 2 is bent due to its own weight, as shown in FIG.
In a resin mold package, the bonding wires may come into contact with each other due to the flow of resin during resin encapsulation. As a result, the length of the bonding wires is severely limited, resulting in the disadvantage that it is necessary to prepare many types of lead frames, each having a different size depending on the size of the integrated circuit chip.

′１ｆｃ１適癌なリードフレームがない場合、多大な工
数と時間をかけ、新規に作成しなければならないという
ことになる。'1fc1 If a suitable lead frame is not available, a large amount of man-hours and time will be required to create a new one.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し本発明の集積回路装置では、リードフ
レームのアイランドに載置される集積回路テップ上面と
同等以上の高さをもち、前記集積回路チップとリードフ
レームのリードとの間を接続するボンディング線の垂れ
下りを支持する絶縁体が前記アイ２ンドの縁辺部に設け
られている。To solve the above problem, the integrated circuit device of the present invention has a height equal to or higher than the top surface of the integrated circuit chip placed on the island of the lead frame, and connects the integrated circuit chip and the leads of the lead frame. An insulator is provided at the edge of the eye 2 to support the hanging of the bonding wire.

〔実施例〕〔Example〕

つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.

第１図は本発明の一実施例に係る集積回路装置の樹脂封
止前の部分断面図である。第１図において、集積回路チ
ップ３が載置されたり−ド７レームのアイランド１の縁
辺部に、集積回路テップ３の上面と同等以上の高さをも
つ絶縁体５が設けられている。そして、絶縁体５の上を
飛び越して、チップ３のパッド４とリード２との間に接
続されたボンディング＃ｊ１６は、同図６′のように中
央部が垂れ下がっても、絶縁体５によプ支持される。FIG. 1 is a partial sectional view of an integrated circuit device according to an embodiment of the present invention before resin sealing. In FIG. 1, an insulator 5 having a height equal to or higher than the top surface of the integrated circuit chip 3 is provided at the edge of the island 1 of the frame on which the integrated circuit chip 3 is mounted. Bonding #j16, which jumps over the insulator 5 and is connected between the pad 4 of the chip 3 and the lead 2, is bonded to the insulator 5 even if the center part hangs down as shown in FIG. 6'. supported.

〔発明の効果〕 以上説明したように、本発明は、集積回路チップとリー
ドの間に絶縁体を配置することにより、ボンディング線
の変形を制限し、これによりボンディング線の長さに関
する制限を緩和することとな９、リードフレームを共通
化できる効果がある０[Effects of the Invention] As explained above, the present invention limits the deformation of the bonding wire by arranging an insulator between the integrated circuit chip and the leads, thereby easing restrictions on the length of the bonding wire. 9. It has the effect of making lead frames common 0

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の樹脂封止前の部分断面図、
第２図は従来の集積回路装置の樹脂封止前の部分断面図
である。 １・・・・・・リードフレームのアイランド、２・・・
・・・リードフレームのリード、３・・・・・・集積回
路チップ、４・・・・・・チップのパッド、５・・・・
・・絶縁体、６・・・・・・ボンディング線。FIG. 1 is a partial cross-sectional view of an embodiment of the present invention before resin sealing;
FIG. 2 is a partial sectional view of a conventional integrated circuit device before being sealed with resin. 1...Lead frame island, 2...
...lead of lead frame, 3...integrated circuit chip, 4...pad of chip, 5...
...Insulator, 6...Bonding wire.

Claims (1)

【特許請求の範囲】[Claims] リードフレームのアイランドに集積回路チップが固着さ
れ、前記チップと前記リードフレームのリードとの間が
ボンディング線で接続され樹脂封止された集積回路装置
において、前記アイランドの縁辺に前記集積回路チップ
の上面と同等以上の高さを有する絶縁体が設けられてい
ることを特徴とする集積回路装置。In an integrated circuit device in which an integrated circuit chip is fixed to an island of a lead frame, and the chip and the lead of the lead frame are connected with bonding wires and sealed with resin, the upper surface of the integrated circuit chip is attached to the edge of the island. An integrated circuit device characterized by being provided with an insulator having a height equal to or higher than that of the integrated circuit device.
JP60260598A 1985-11-19 1985-11-19 Integrated circuit device Pending JPS62119933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60260598A JPS62119933A (en) 1985-11-19 1985-11-19 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60260598A JPS62119933A (en) 1985-11-19 1985-11-19 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS62119933A true JPS62119933A (en) 1987-06-01

Family

ID=17350169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60260598A Pending JPS62119933A (en) 1985-11-19 1985-11-19 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS62119933A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091772A (en) * 1989-05-18 1992-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and package
JP6986796B1 (en) * 2021-06-04 2021-12-22 ハイソル株式会社 Coil structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091772A (en) * 1989-05-18 1992-02-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and package
JP6986796B1 (en) * 2021-06-04 2021-12-22 ハイソル株式会社 Coil structure
JP2022186186A (en) * 2021-06-04 2022-12-15 ハイソル株式会社 Coil structure body

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