JPH0199245A - Ic package - Google Patents
Ic packageInfo
- Publication number
- JPH0199245A JPH0199245A JP25683687A JP25683687A JPH0199245A JP H0199245 A JPH0199245 A JP H0199245A JP 25683687 A JP25683687 A JP 25683687A JP 25683687 A JP25683687 A JP 25683687A JP H0199245 A JPH0199245 A JP H0199245A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- package
- mold
- frame
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分舒〕
この発明は、例えばＩＣをセットに組み込む場合に実装
面積を小さくし、また高入力インピーダンス端子の静電
破壊を防止することができるＩＣパッケージに関するも
のである。[Detailed Description of the Invention] [Industrial Application] The present invention provides an IC package that can reduce the mounting area when incorporating an IC into a set, and can prevent electrostatic damage to high input impedance terminals. It is related to.
第９図は従来のＤＩＰ型ＩＣパッケージを示すものであ
り、図において、１はＩＣチップ、２はリードフレーム
、３は金線、４はサポートテープ、５は封止樹脂である
。FIG. 9 shows a conventional DIP type IC package. In the figure, 1 is an IC chip, 2 is a lead frame, 3 is a gold wire, 4 is a support tape, and 5 is a sealing resin.
この従来のＩＣパッケージでは、第９図に示すように封
止゛樹脂５のモールドの外側にリードフレーム２を出し
て端子とし、これを外部のソケットや基板にさし込むこ
とで実装するようにしている。In this conventional IC package, as shown in FIG. 9, the lead frame 2 is exposed outside the mold of the sealing resin 5 to serve as a terminal, and the lead frame 2 is mounted by inserting it into an external socket or board. ing.
［発明が解決しようとする問題点〕
従来のＩＣパッケージでは、リードフレームをモールド
から外側に出しているので、ＩＣの足となる部分をつく
るためにフレームが長くなり、またＩＣの足置外の部分
をモールドする必要からパッケー誠がチップに対して大
きくなるという問題があった。またＩＣの足がモールド
から出ているので、高入力インピーダンス端子の場合、
手で触れると静電破壊を起こす可能性をもつという問題
があった。[Problems to be Solved by the Invention] In conventional IC packages, the lead frame is exposed outside the mold, so the frame becomes long to make the parts that will become the legs of the IC, and There was a problem in that the package size became larger than the chip because it was necessary to mold the parts. Also, since the legs of the IC are protruding from the mold, in the case of high input impedance terminals,
There was a problem in that touching it with your hands could cause electrostatic damage.
乙の発明は上記のような問題点を解消するためになされ
たもので、ＩＣパッケージを小さくすることができろと
ともに、静電破壊を未然に防止することができるＩＣパ
ッケージを得ることを目的とする。B's invention was made to solve the above problems, and aims to provide an IC package that can be made smaller and prevent electrostatic damage. do.
この発明に係るＩＣパッケージは、リードフレームをモ
ールドの内側に納め、ＩＣと外部装置との接点をパッケ
ージ内部に設けたものである。In the IC package according to the present invention, a lead frame is housed inside a mold, and a contact point between the IC and an external device is provided inside the package.
この発明では、リードフレームをモールドの内側に納め
、ＩＣと外部装置との接点をパッケージの内部に設ける
ことにより、ＩＣのリードフレームが小さくなり、また
ＩＣのビンに不用意に触れることがないので、静電破壊
を起こすおそれはない。In this invention, the lead frame is housed inside the mold and the contact between the IC and the external device is provided inside the package, so the IC lead frame can be made smaller and the IC bottle can be prevented from being accidentally touched. , there is no risk of electrostatic damage.
以下この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例によるＩＣパッケージの全
体構成図、第２図は第１図の矢印■方向からみた図であ
る。Ｉ、Ｃチップ１とモールド内に納まろように短くし
たリードフレーム２とを金線３でワイヤボンドし、リー
ドフレーム２をサポートテープ４で固定したものを樹脂
５でモールドしたものであるが、リードフレーム２にバ
ンプ６を設けるとともに、樹脂５中のリードフレーム２
と外部端子７を接触させるため樹ｌｌ１５に穴８をあけ
ている。FIG. 1 is an overall configuration diagram of an IC package according to an embodiment of the present invention, and FIG. 2 is a diagram as viewed from the direction of the arrow 2 in FIG. The I, C chip 1 and a lead frame 2 shortened to fit within the mold are wire-bonded with gold wire 3, and the lead frame 2 is fixed with support tape 4, which is then molded with resin 5. In addition to providing bumps 6 on the lead frame 2, the lead frame 2 in the resin 5
A hole 8 is made in the tree 15 in order to bring the external terminal 7 into contact with the external terminal 7.
次に上記実施例の製法を第３図〜第７図により説明する
。まず第３図のようにＩＣチップ１をリードフレーム２
にダイボンドし、またＩＣチップ１からリードフレーム
２にワイヤボンドする。上記工程のあと、第４図に示す
ようにリードフレーム２にＥＣチップ１がのっている面
のみをＶ！４１１１５でモールドする。ここでリードフ
レーム２をカットして第５図の状態となる。第５図の状
態のものを第６図に示すピン９が出ている型の上に置き
、リードフレーム２のＩＣチップ１がのっていない方の
面を［１でモールドする。モールドを完了したものが第
７図である。そしてこの第７図の六８にハンダを流し込
んでバンプ６を形成することにより第２図の完成品とな
る。Next, the manufacturing method of the above embodiment will be explained with reference to FIGS. 3 to 7. First, as shown in Figure 3, place the IC chip 1 on the lead frame 2.
The IC chip 1 is die-bonded to the lead frame 2, and the IC chip 1 is wire-bonded to the lead frame 2. After the above steps, as shown in FIG. 4, only the surface of the lead frame 2 on which the EC chip 1 is placed is V! Mold with 41115. At this point, the lead frame 2 is cut to obtain the state shown in FIG. 5. The product in the state shown in FIG. 5 is placed on the mold shown in FIG. 6 from which the pins 9 are exposed, and the surface of the lead frame 2 on which the IC chip 1 is not placed is molded with [1]. FIG. 7 shows the completed mold. By pouring solder into the 68 shown in FIG. 7 to form bumps 6, the finished product shown in FIG. 2 is obtained.
なお上記実施例では、リードフレーム２は完全にモール
ドの中にあるが、リードフレーム２が第８図のようにＩ
Ｃパッケージの裏面に接していてもよい。In the above embodiment, the lead frame 2 is completely inside the mold, but the lead frame 2 is completely inside the mold as shown in FIG.
It may be in contact with the back surface of the C package.
以上のようにこの発明によれば、モールドからリードフ
レームが突き出ていないので、ＩＣのパッケージを小さ
くでき、ＩＣをセットに組むときの実装面積を小さくで
き、また高入力インピーダンス端子の場合、リードが出
ていないので、静電破壊を防ぐことができる。また、従
来のようなリードフレーム部分が不必要なため、多連フ
レームの場合、一定面積から数多くのＩＣが製造できる
などの効果がある。As described above, according to the present invention, since the lead frame does not protrude from the mold, the IC package can be made smaller, the mounting area when assembling the IC into a set can be reduced, and in the case of high input impedance terminals, the lead frame can be made smaller. Since no electricity is emitted, electrostatic damage can be prevented. Furthermore, since the conventional lead frame part is unnecessary, in the case of a multiple frame, there is an advantage that a large number of ICs can be manufactured from a fixed area.
第１図はこの発明の一実施例によるＩＣパッケージの全
体構成図で一部を切欠いて示した斜視図、第２図は第１
図の■方向からみた断面図、第３図〜第７図はＩＣパッ
ケージの製造方法を説明する図、第８図はこの発明の他
の実施例を示す図、第９図は従来のアセンブリ技術を用
いたＩＣパッケージを示す一部切欠きの斜視図である。
図中、１はＩＣチップ、２はリードフレーム、３は金線
、５は封止樹脂、６はバンプ、７は外部端子、８は穴で
ある。
尚、図中同一符号は同−又は相当部分を示す。FIG. 1 is a partially cutaway perspective view showing the overall configuration of an IC package according to an embodiment of the present invention, and FIG.
3 to 7 are diagrams illustrating a method of manufacturing an IC package, FIG. 8 is a diagram showing another embodiment of the present invention, and FIG. 9 is a diagram illustrating a conventional assembly technique. FIG. 2 is a partially cutaway perspective view showing an IC package using the IC package. In the figure, 1 is an IC chip, 2 is a lead frame, 3 is a gold wire, 5 is a sealing resin, 6 is a bump, 7 is an external terminal, and 8 is a hole. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (3)
れ、モールドの外部に突き出ていないことを特徴とする
ＩＣパッケージ。(1) An IC package characterized in that external connection leads are housed inside a resin mold and do not protrude outside the mold.
プを付設し、このバンプと通ずる穴を樹脂に設けてなる
特許請求の範囲第１項記載のＩＣパッケージ。(2) The IC package according to claim 1, wherein a bump is attached to a part of the sword frame housed in the resin, and a hole communicating with the bump is provided in the resin.
接するように配置されている特許請求の範囲ＩＣパッケ
ージ。(3) The IC package as claimed in claim 1, wherein a part of the lead frame is arranged so as to be in contact with the back surface of the IC package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25683687A JPH0199245A (en) | 1987-10-12 | 1987-10-12 | Ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25683687A JPH0199245A (en) | 1987-10-12 | 1987-10-12 | Ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0199245A true JPH0199245A (en) | 1989-04-18 |
Family
ID=17298098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25683687A Pending JPH0199245A (en) | 1987-10-12 | 1987-10-12 | Ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0199245A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333211B1 (en) | 1998-08-26 | 2001-12-25 | Shinko Electric Industries, Co., Ltd. | Process for manufacturing a premold type semiconductor package using support pins in the mold and external connector bumps |
| KR100761861B1 (en) * | 2006-10-11 | 2007-09-28 | 삼성전자주식회사 | Semiconductor package preventing the static electricity |
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
-
1987
- 1987-10-12 JP JP25683687A patent/JPH0199245A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333211B1 (en) | 1998-08-26 | 2001-12-25 | Shinko Electric Industries, Co., Ltd. | Process for manufacturing a premold type semiconductor package using support pins in the mold and external connector bumps |
| US6577000B2 (en) | 1998-08-26 | 2003-06-10 | Shinko Electric Industries Co., Ld. | Premold type semiconductor package |
| US9620391B2 (en) | 2002-10-11 | 2017-04-11 | Micronas Gmbh | Electronic component with a leadframe |
| KR100761861B1 (en) * | 2006-10-11 | 2007-09-28 | 삼성전자주식회사 | Semiconductor package preventing the static electricity |
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