JPH07211850A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07211850A
JPH07211850A JP232394A JP232394A JPH07211850A JP H07211850 A JPH07211850 A JP H07211850A JP 232394 A JP232394 A JP 232394A JP 232394 A JP232394 A JP 232394A JP H07211850 A JPH07211850 A JP H07211850A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead
bonding
die pad
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP232394A
Other languages
Japanese (ja)
Inventor
Motoaki Sato
元昭 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP232394A priority Critical patent/JPH07211850A/en
Publication of JPH07211850A publication Critical patent/JPH07211850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PURPOSE:To realize a piece of very low loop wire by shortening a bonding wire for connecting the bonding pad of a semiconductor chip and a lead. CONSTITUTION:A die pad 2 comprises a central part 2a for mounting a semiconductor chip 7 and a peripheral part 2b. An inner lead 4 is fixed on the peripheral part 2b with an insulating tape 6. At this time, the central part 2a of the die pad 2 is located lower than the inner lead 4, so that the surface of a bonding pad 8 of the mounted semiconductor chip 7 and the surface of the inner lead 4 are aligned on the approxiamtely same horizontal plane. The bonding pad 8 and the inner lead 4 are connected with a bonding wire 3. Thus the inductance can be electrically reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、半導体チップを樹脂
封止した半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is resin-sealed.

【０００２】[0002]

【従来の技術】半導体チップを樹脂封止した従来の半導
体装置を図４ないし図６を参照しながら説明する。図４
は従来の半導体装置の断面図、図５はその分解斜視図、
図６はその平面図である。2. Description of the Related Art A conventional semiconductor device in which a semiconductor chip is resin-sealed will be described with reference to FIGS. Figure 4
Is a cross-sectional view of a conventional semiconductor device, FIG. 5 is its exploded perspective view,
FIG. 6 is a plan view thereof.

【０００３】従来の半導体装置のリードフレーム１１
は、ダイパッド１２とリードからなり、リードはインナ
ーリード１４と外部端子のアウターリード１５からな
る。このリードフレーム１１は一体成形しているため、
ダイパッド１２とインナーリード１４との間に一定の距
離をとり、ダイパッド１２上に半導体チップ７を搭載
し、半導体チップ７のボンディングパッド８にインナー
リード１４をボンディングワイヤ１３で接続し、樹脂封
止していた。Conventional semiconductor device lead frame 11
Is composed of a die pad 12 and leads, and the leads are composed of inner leads 14 and outer leads 15 of external terminals. Since this lead frame 11 is integrally molded,
A certain distance is provided between the die pad 12 and the inner lead 14, the semiconductor chip 7 is mounted on the die pad 12, the inner lead 14 is connected to the bonding pad 8 of the semiconductor chip 7 with the bonding wire 13, and the resin is sealed. Was there.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら上記従来
の構成では、リードフレーム１１は一体成形しているた
め、ダイパッド１２とインナーリード１４との間に一定
の距離が必要であり、ボンディングワイヤ１３の長さが
長くなっていた。このようにボンディングワイヤ１３が
長くなると、外部環境から半導体チップ７を保護してい
る封止樹脂９の表面にボンディングワイヤ１３が露出す
る恐れがある。また、ワイヤボンディングした後の封止
工程で、注入樹脂の圧力によりワイヤループ形状が変わ
らないように注意が必要である。また、封止前のワイヤ
ボンディングした後の状態では、耐衝撃性に弱い。特に
超低ループワイヤが必要となる薄型パッケージでは適切
なループコントロールの障害になるという問題があっ
た。However, in the above-mentioned conventional structure, since the lead frame 11 is integrally molded, a certain distance is required between the die pad 12 and the inner lead 14, and the length of the bonding wire 13 is long. Was getting longer. If the bonding wire 13 becomes long in this way, the bonding wire 13 may be exposed on the surface of the sealing resin 9 that protects the semiconductor chip 7 from the external environment. Further, it is necessary to take care so that the wire loop shape does not change due to the pressure of the injected resin in the sealing step after wire bonding. In addition, impact resistance is weak in the state after wire bonding before sealing. Especially, in a thin package that requires an ultra-low loop wire, there is a problem that it becomes an obstacle to proper loop control.

【０００５】この発明の目的は、上記従来の問題を解決
するもので、半導体チップのボンディングパッドとリー
ドとを接続するボンディングワイヤを短くし、超低ルー
プワイヤを実現できる半導体装置を提供することであ
る。An object of the present invention is to solve the above-mentioned conventional problems, and to provide a semiconductor device capable of realizing an ultra-low loop wire by shortening a bonding wire connecting a bonding pad and a lead of a semiconductor chip. is there.

【０００６】[0006]

【課題を解決するための手段】この発明の半導体装置
は、ダイパッドは半導体チップを搭載する中央部とその
周辺部からなり、リードを周辺部の上に周辺部と絶縁し
て固定することにより、搭載した半導体チップのボンデ
ィングパッドとリードの表面とを略同一水平面上に位置
決めしたことを特徴とする。According to the semiconductor device of the present invention, the die pad is composed of a central portion on which a semiconductor chip is mounted and its peripheral portion, and by fixing the leads on the peripheral portion insulatively from the peripheral portion, The bonding pad of the mounted semiconductor chip and the surface of the lead are positioned on substantially the same horizontal plane.

【０００７】[0007]

【作用】この発明の構成によれば、ダイパッドは中央部
とその周辺部からなり、リードをダイパッドの周辺部の
上に、この周辺部と絶縁して固定することにより、ダイ
パッドの中央部に搭載した半導体チップのボンディング
パッドとリードの表面とを略同一水平面上に位置決めし
ているため、半導体チップとリードとを接近させること
ができる。そのため、半導体チップのボンディングパッ
ドとリードを接続するボンディングワイヤを短くでき、
複雑なループコントロールを必要とせずに、簡易なワイ
ヤボンド装置でも超低ループを実現することができる。According to the structure of the present invention, the die pad is composed of the central portion and its peripheral portion, and the leads are mounted on the peripheral portion of the die pad by being insulated and fixed to the peripheral portion of the die pad. Since the bonding pad of the semiconductor chip and the surface of the lead are positioned on substantially the same horizontal plane, the semiconductor chip and the lead can be brought close to each other. Therefore, the bonding wire connecting the bonding pad of the semiconductor chip and the lead can be shortened,
An ultra-low loop can be realized even with a simple wire bond device without requiring complicated loop control.

【０００８】[0008]

【実施例】この発明の一実施例の半導体装置を図面を参
照しながら説明する。図１はこの発明の一実施例の半導
体装置の断面図、図２はその分解斜視図、図３はその平
面図である。図１ないし図３において、１はリードフレ
ーム、２はダイパッド、３はボンディングワイヤ、４は
インナーリード、５はアウターリード、６は絶縁テー
プ、７は半導体チップ、８は半導体チップ７のボンディ
ングパッド、９は封止樹脂である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an exploded perspective view thereof, and FIG. 3 is a plan view thereof. 1 to 3, 1 is a lead frame, 2 is a die pad, 3 is a bonding wire, 4 is an inner lead, 5 is an outer lead, 6 is an insulating tape, 7 is a semiconductor chip, 8 is a bonding pad of the semiconductor chip 7, 9 is a sealing resin.

【０００９】この半導体装置は、リードフレーム１が、
インナーリード４およびアウターリード５からなるリー
ドと、ダイパッド２との２重構造になっている。ダイパ
ッド２は半導体チップ７を搭載する中央部２ａとその周
辺部２ｂからなり、インナーリード４を周辺部２ｂの上
に絶縁テープ６で固定している。この際、ダイパッド２
の中央部２ａをインナーリード４より下に位置させ、搭
載した半導体チップ７のボンディングパッド８とインナ
ーリード４の表面とが略同一水平面上になるように位置
決めしている。そして、ボンディングパッド８とインナ
ーリード４をボンディングワイヤ３で接続している。In this semiconductor device, the lead frame 1 is
It has a double structure of a die pad 2 and a lead including an inner lead 4 and an outer lead 5. The die pad 2 is composed of a central portion 2a on which the semiconductor chip 7 is mounted and a peripheral portion 2b thereof, and the inner leads 4 are fixed on the peripheral portion 2b with an insulating tape 6. At this time, die pad 2
Is positioned below the inner lead 4 so that the bonding pad 8 of the mounted semiconductor chip 7 and the surface of the inner lead 4 are on substantially the same horizontal plane. Then, the bonding pad 8 and the inner lead 4 are connected by the bonding wire 3.

【００１０】この実施例によれば、ダイパッド２の周辺
部２ｂの上にインナーリード４を絶縁テープ６で固定す
ることにより、半導体チップ７とインナーリード４との
間隔を数十〜数百μｍまで短くすることができる。さら
に、ワイヤボンディングする箇所が略同一水平面上にな
るように位置決めしたことにより、半導体チップ７のボ
ンディングパッド８とインナーリード４を接続するボン
ディングワイヤ３を短くでき、複雑なループコントロー
ルを必要とせずに、簡易なワイヤボンド装置でも超低ル
ープを実現することができる。これにより、電気的にも
インダクタンスの低減を図ることができる。According to this embodiment, the inner lead 4 is fixed on the peripheral portion 2b of the die pad 2 with the insulating tape 6, so that the distance between the semiconductor chip 7 and the inner lead 4 is several tens to several hundreds of μm. Can be shortened. Furthermore, by positioning the wire bonding locations so that they are on substantially the same horizontal plane, the bonding wire 3 connecting the bonding pad 8 of the semiconductor chip 7 and the inner lead 4 can be shortened, and complicated loop control is not required. An ultra-low loop can be realized with a simple wire bonder. As a result, the inductance can be reduced electrically.

【００１１】[0011]

【発明の効果】この発明の半導体装置は、ダイパッドが
中央部とその周辺部からなり、リードをダイパッドの周
辺部の上に、この周辺部と絶縁して固定することによ
り、ダイパッドの中央部に搭載した半導体チップのボン
ディングパッドとリードの表面とを略同一水平面上に位
置決めしているため、半導体チップとリードとを接近さ
せることができる。そのため、半導体チップのボンディ
ングパッドとリードを接続するボンディングワイヤを短
くでき、複雑なループコントロールを必要とせずに、簡
易なワイヤボンド装置でも超低ループを実現することが
できる。これにより、電気的にもインダクタンスの低減
を図ることができる。According to the semiconductor device of the present invention, the die pad is composed of the central portion and the peripheral portion thereof, and the leads are fixed on the peripheral portion of the die pad while being insulated from the peripheral portion. Since the bonding pad of the mounted semiconductor chip and the surface of the lead are positioned on substantially the same horizontal plane, the semiconductor chip and the lead can be brought close to each other. Therefore, the bonding wire connecting the bonding pad of the semiconductor chip and the lead can be shortened, and an ultra-low loop can be realized by a simple wire bond device without requiring complicated loop control. As a result, the inductance can be reduced electrically.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の一実施例の半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図２】同実施例の半導体装置の分解斜視図である。FIG. 2 is an exploded perspective view of the semiconductor device according to the embodiment.

【図３】同実施例の半導体装置の平面図である。FIG. 3 is a plan view of the semiconductor device of the same example.

【図４】従来の半導体装置の断面図である。FIG. 4 is a sectional view of a conventional semiconductor device.

【図５】従来の半導体装置の分解斜視図である。FIG. 5 is an exploded perspective view of a conventional semiconductor device.

【図６】従来の半導体装置の平面図である。FIG. 6 is a plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

２ ダイパッド ２ａ ダイパッドの中央部 ２ｂ ダイパッドの周辺部 ３ ボンディングワイヤ ４ インナーリード ５ アウターリード ６ 絶縁テープ ７ 半導体チップ ８ ボンディングパッド ９ 封止樹脂 2 die pad 2a central part of die pad 2b peripheral part of die pad 3 bonding wire 4 inner lead 5 outer lead 6 insulating tape 7 semiconductor chip 8 bonding pad 9 sealing resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 ダイパッドに搭載した半導体チップのボ
ンディングパッドをボンディングワイヤでリードに接続
して樹脂封止した半導体装置であって、 前記ダイパッドは前記半導体チップを搭載する中央部と
その周辺部からなり、前記リードを前記周辺部の上に前
記周辺部と絶縁して固定することにより、搭載した前記
半導体チップのボンディングパッドと前記リードの表面
とを略同一水平面上に位置決めしたことを特徴とする半
導体装置。1. A semiconductor device in which a bonding pad of a semiconductor chip mounted on a die pad is connected to a lead with a bonding wire and resin-sealed, wherein the die pad includes a central portion on which the semiconductor chip is mounted and a peripheral portion thereof. A semiconductor, characterized in that the bonding pad of the mounted semiconductor chip and the surface of the lead are positioned on substantially the same horizontal plane by fixing the lead on the peripheral portion while being insulated from the peripheral portion. apparatus.
JP232394A 1994-01-14 1994-01-14 Semiconductor device Pending JPH07211850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP232394A JPH07211850A (en) 1994-01-14 1994-01-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP232394A JPH07211850A (en) 1994-01-14 1994-01-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07211850A true JPH07211850A (en) 1995-08-11

Family

ID=11526118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP232394A Pending JPH07211850A (en) 1994-01-14 1994-01-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07211850A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11103003A (en) * 1997-07-31 1999-04-13 Matsushita Electron Corp Semiconductor device and lead frame
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
JP2013030670A (en) * 2011-07-29 2013-02-07 Mitsubishi Electric Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11103003A (en) * 1997-07-31 1999-04-13 Matsushita Electron Corp Semiconductor device and lead frame
US6208023B1 (en) 1997-07-31 2001-03-27 Matsushita Electronics Corporation Lead frame for use with an RF powered semiconductor
JP2013030670A (en) * 2011-07-29 2013-02-07 Mitsubishi Electric Corp Semiconductor device

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