JPH05206193A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05206193A
JPH05206193A JP4013378A JP1337892A JPH05206193A JP H05206193 A JPH05206193 A JP H05206193A JP 4013378 A JP4013378 A JP 4013378A JP 1337892 A JP1337892 A JP 1337892A JP H05206193 A JPH05206193 A JP H05206193A
Authority
JP
Japan
Prior art keywords
semiconductor element
wire
insulating thin
thin plate
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4013378A
Other languages
Japanese (ja)
Inventor
Yoshihiro Matsumoto
義宏 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4013378A priority Critical patent/JPH05206193A/en
Publication of JPH05206193A publication Critical patent/JPH05206193A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make thin a package without malfunction of deformation or contact of bonding wires with a semiconductor element by mounting an insulating thin board which is bored at the same position as a bonding pad of a semiconductor element on the semiconductor element, and by bonding the thin board through a hole. CONSTITUTION:A Teflon insulating thin board 1 has a hole at the same position as a bonding pad of a semiconductor element 2. After mounting the insulating thin board 1 on the semiconductor element 2, the semiconductor element 2 and a lead frame 3 are bonded through Au line wire 4, and then are molded with mold resin 5. The Au line wires 4 do not contact with the semiconductor element 2, even if it is deformed at the time of molding. In addition, wire bonding at the shortest distance can be ensured, because the insulating thin board 1 is used between wires, thereby a package can be made thin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体装置に関し、特
に半導体素子表面に絶縁性薄板をはさみ込んだモールド
パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a mold package in which an insulating thin plate is sandwiched on the surface of a semiconductor element.

【０００２】[0002]

【従来の技術】従来、この種の半導体装置のパッケージ
は、プラスチックのモールド樹脂等の非導電性材を成形
することにより、半導体素子をとり囲む構造となってい
る。2. Description of the Related Art Conventionally, a semiconductor device package of this type has a structure surrounding a semiconductor element by molding a non-conductive material such as plastic molding resin.

【０００３】すなわち、半導体素子は、リードフレーム
のアイランド部にマウントされた後、リードフレームの
内部リード部と、半導体素子の外部との電気的接続をと
るためのアルミパッドとを、Ａｕ線やＡｌ線といった導
電性ワイヤーで接続し、モールド樹脂等の非導電性材で
封止、成形することでパッケージとしている。That is, after the semiconductor element is mounted on the island portion of the lead frame, the inner lead portion of the lead frame and the aluminum pad for making an electrical connection with the outside of the semiconductor element are connected to Au wire or Al. A package is formed by connecting with a conductive wire such as a wire and sealing and molding with a non-conductive material such as a mold resin.

【０００４】従って、半導体素子表面と、モールド樹脂
との間には何も挿入されていないのが通常である。Therefore, it is usual that nothing is inserted between the surface of the semiconductor element and the molding resin.

【０００５】[0005]

【発明が解決しようとする課題】半導体素子（ペレッ
ト）上のアルミパッドと、リードフレームとの電気的接
続は、通常Ａｕ線、Ａｌ線等の導電性ワイヤーによって
接続することで行なっている。The electrical connection between the aluminum pad on the semiconductor element (pellet) and the lead frame is usually made by connecting with a conductive wire such as Au wire or Al wire.

【０００６】この際、導電性ワイヤーの長さ、太さ、材
質や半導体チップのアルミパッドと、リードフレームの
内部リードとの位置関係によっては、ワイヤーがペレッ
トに接触したり、封入時に張力がかかり切断したり、樹
脂の封入方向にワイヤーが流れたりする問題点がある。At this time, depending on the length and thickness of the conductive wire, the material, and the positional relationship between the aluminum pad of the semiconductor chip and the internal lead of the lead frame, the wire may come into contact with the pellet or a tension may be applied during encapsulation. There are problems such as cutting and wires flowing in the resin enclosing direction.

【０００７】さらに、ワイヤーの上述した不具合を避け
るために、ワイヤーにペレットからの一定の高さが必要
で、パッケージの薄型化には不利となる問題点があっ
た。Furthermore, in order to avoid the above-mentioned problems of the wire, the wire needs to have a certain height from the pellet, which is disadvantageous in reducing the thickness of the package.

【０００８】[0008]

【課題を解決するための手段】本発明の半導体装置のパ
ッケージでは、半導体素子をリードフレームにマウント
後、半導体素子表面に絶縁性薄板を適当な接着材で装着
する。In the package of the semiconductor device of the present invention, after mounting the semiconductor element on the lead frame, an insulating thin plate is attached to the surface of the semiconductor element with an appropriate adhesive material.

【０００９】この絶縁性薄板には、半導体素子のアルミ
パッド部と同じ位置に、アルミパッド（約１００μm
□）より、数μm 大きい穴があいており、この穴を通し
て導電性のワイヤーで半導体素子のアルミパッドとリー
ドフレームの内部リードとを接続させた構造となってい
る。This insulating thin plate has an aluminum pad (about 100 μm) at the same position as the aluminum pad portion of the semiconductor element.
From □), there is a hole that is several μm larger, and the structure is such that the aluminum pad of the semiconductor element and the internal lead of the lead frame are connected by a conductive wire through this hole.

【００１０】この構造の為、導電性ワイヤーがペレット
に接触することはなく、ワイヤーの高さも低くすること
が可能である。Due to this structure, the conductive wire does not come into contact with the pellet, and the height of the wire can be reduced.

【００１１】[0011]

【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【００１２】図１は、本発明の実施例１の縦断面図であ
る。また、図２（ａ）は、本実施例で用いた絶縁性薄板
の上方より見た図である。絶縁性薄板の厚さは約２００
μmであり、材質はテフロンである。従って、耐熱性、
耐薬品性に優れている。FIG. 1 is a vertical sectional view of a first embodiment of the present invention. Further, FIG. 2A is a view seen from above the insulating thin plate used in this example. The thickness of the insulating thin plate is about 200
μm, and the material is Teflon. Therefore, heat resistance,
Has excellent chemical resistance.

【００１３】半導体素子のアルミパッド位置に合わせて
絶縁性薄板１には１２０μm 四方の四角い穴があけられ
ており、この穴を通して半導体素子２のアルミパッド
と、リードフレーム３の内部リードとを、３０μm φの
Ａｕ線ワイヤー４で接続する。A 120 μm square hole is formed in the insulating thin plate 1 in accordance with the position of the aluminum pad of the semiconductor element, and the aluminum pad of the semiconductor element 2 and the inner lead of the lead frame 3 are 30 μm through this hole. Connect with φ Au wire 4.

【００１４】絶縁性薄板１の穴の周囲は２０μm 程の導
電性の縁取り７があり、本実施例ではＣｕが蒸着されて
いる（図２（ｂ））。これによってワイヤーが穴の縁で
こすれて切断されにくい構造となっている。Around the hole of the insulating thin plate 1 is a conductive edging 7 of about 20 μm, and Cu is vapor-deposited in this embodiment (FIG. 2 (b)). This makes it difficult for the wire to rub against the edge of the hole and be cut.

【００１５】図３は、本発明の実施例２で用いた絶縁性
薄板の上方より見た図である。FIG. 3 is a view of the insulating thin plate used in Example 2 of the present invention as seen from above.

【００１６】ワイヤーがあたる穴の部分はすべてテフロ
ンでできており、それ以外の部分は、導電性薄板８でで
きている。All of the holes hit by the wires are made of Teflon, and the other parts are made of the conductive thin plate 8.

【００１７】導電性薄板としては、Ｃｕ板を使用してい
る。A Cu plate is used as the conductive thin plate.

【００１８】本実施例では、導電性薄板８が外部からの
電界及び磁界を緩和する効果を有する。In this embodiment, the conductive thin plate 8 has an effect of relaxing an electric field and a magnetic field from the outside.

【００１９】[0019]

【発明の効果】以上説明した様に、本発明は半導体素子
の表面に半導体素子のアルミパッドと同じ位置に穴を形
成させた絶縁性薄板を装着し、上述した穴を通して半導
体素子のアルミパッドとリードフレームとの電気的接続
をとる構造としたのでワイヤーがペレットに接続したり
せず、また、ワイヤーを最短距離で接続できるため、樹
脂封入時にワイヤーが流れるといった不具合が起こりに
くい。As described above, according to the present invention, an insulating thin plate having a hole formed at the same position as the aluminum pad of the semiconductor element is mounted on the surface of the semiconductor element, and the aluminum pad of the semiconductor element is formed through the hole described above. Since the wire is electrically connected to the lead frame, the wire is not connected to the pellet, and the wire can be connected in the shortest distance. Therefore, the problem of the wire flowing during resin encapsulation is unlikely to occur.

【００２０】さらにワイヤーのペレットからの高さを低
くすることができ、パッケージの薄型化にも有利となる
といった効果を有する。Further, the height of the wire from the pellet can be reduced, which is advantageous in reducing the thickness of the package.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１の縦断面図である。FIG. 1 is a vertical sectional view of a first embodiment of the present invention.

【図２】（ａ）は本発明の実施例１で用いた絶縁性薄板
の上方より見た図である。（ｂ）は本発明の絶縁性薄板
のボンディング用穴部分の拡大図である。FIG. 2A is a view of the insulating thin plate used in Example 1 of the present invention as viewed from above. (B) is an enlarged view of a bonding hole portion of the insulating thin plate of the present invention.

【図３】本発明の実施例２で用いた絶縁性薄板の上方よ
り見た図である。FIG. 3 is a view of an insulating thin plate used in Example 2 of the present invention as seen from above.

【符号の説明】[Explanation of symbols]

１ 絶縁性薄板 ２ 半導体素子（チップ） ３ リードフレーム ４ Ａｕ線ワイヤー ５ モールド樹脂 ６ ボンディング用穴 ７ 導電性（Ｃｕ）の縁取り ８ 導電性薄板 1 Insulating Thin Plate 2 Semiconductor Element (Chip) 3 Lead Frame 4 Au Wire Wire 5 Mold Resin 6 Bonding Hole 7 Conductive (Cu) Edge 8 Conductive Thin Plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体装置のモールドパッケージにおい
て、半導体素子の表面に半導体素子のアルミパッドと同
じ位置に穴を形成させた絶縁性薄板を装着し、上述した
穴を通して半導体素子のアルミパッドとリードフレーム
とを電気的に接続することを特徴とする半導体装置。1. In a mold package of a semiconductor device, an insulating thin plate having a hole formed at the same position as the aluminum pad of the semiconductor element is mounted on the surface of the semiconductor element, and the aluminum pad of the semiconductor element and the lead frame are inserted through the holes described above. A semiconductor device, which is electrically connected to.
JP4013378A 1992-01-28 1992-01-28 Semiconductor device Withdrawn JPH05206193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4013378A JPH05206193A (en) 1992-01-28 1992-01-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4013378A JPH05206193A (en) 1992-01-28 1992-01-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05206193A true JPH05206193A (en) 1993-08-13

Family

ID=11831437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4013378A Withdrawn JPH05206193A (en) 1992-01-28 1992-01-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05206193A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483459B1 (en) * 1998-08-14 2005-07-07 삼성전자주식회사 Fine-pitch ball grid array device
US7739118B2 (en) 2004-06-01 2010-06-15 Nec Corporation Information transmission system and information transmission method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100483459B1 (en) * 1998-08-14 2005-07-07 삼성전자주식회사 Fine-pitch ball grid array device
US7739118B2 (en) 2004-06-01 2010-06-15 Nec Corporation Information transmission system and information transmission method

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