JP3644555B2 - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device Download PDF

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Publication number
JP3644555B2
JP3644555B2 JP02881596A JP2881596A JP3644555B2 JP 3644555 B2 JP3644555 B2 JP 3644555B2 JP 02881596 A JP02881596 A JP 02881596A JP 2881596 A JP2881596 A JP 2881596A JP 3644555 B2 JP3644555 B2 JP 3644555B2
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die pad
insulator
semiconductor element
lead
frame
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JPH09223772A (en
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文彦 大岡
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、リードフレームとこのリードフレームを用いた樹脂封止型の半導体装置とに関するものである。
【０００２】
【従来の技術】
従来のリードフレームは、図４に示すように、フレーム本体３１の樹脂封止パッケージライン３２内に、先端側が金（Ａｕ）や銀（Ａｇ）でメッキされた複数の内部リード３３を有しており、複数の内部リード３３の先端によって囲まれる位置に、半導体素子を搭載するための台座であるダイパット３４が設けられている。またフレーム本体３１の樹脂封止パッケージライン３２外に、半導体装置を製造する際の樹脂流れ止めとなるタイバー３５と、外部リード３６とを有して構成されている。
【０００３】
このようなリードフレーム３を用いて樹脂封止型の半導体装置を製造するにあたっては、図５に示すように、まずダイパット３４上に導電性接着材４１を介して半導体素子４２を接合させる。次いで、こうしてダイパッド３４上に搭載された半導体素子４２と上記内部リード３３とを金属細線４３で接続する。その後、内部リード３３と半導体素子４２とを樹脂４４によって一体に封止し、このことにより半導体装置４を得る。
【０００４】
【発明が解決しようとする課題】
ところが上記した従来のリードフレームでは、半導体素子のサイズにより、ダイパットのサイズおよび内部リードの先端までの長さを適正な寸法にするために、リードフレームを多種類作成しなければならない。よって、製造に非常に煩雑な作業を要する。
またダイパッドの上面が、内部リードの上面とほぼ同じ高さ位置にあり、しかもダイパット上に導電性接着材４１のみを介して半導体素子が搭載されるため、半導体素子がダイパッドからずれて配置されてしまった場合に、半導体素子と内部リードとが非常に接触し易いといった難点も有している。
【０００５】
さらに現状では、半導体素子の高集積化に伴って必要な内部リード数および外部リード数が増大しており、これらリードが微細に加工されているので、特に先端側が固定されていない内部リードの先端にバタツキが生じる。このような内部リードの先端のバタツキは、ダイパッド上に搭載された半導体素子と内部リードとの金属細線による接続の信頼性を低下させる等、半導体装置の製造に悪影響を与えてしまうのである。
したがって、１種類で各種のサイズの半導体素子を搭載でき、かつ高信頼性の半導体装置を製造できるリードフレームおよび半導体装置の開発が切望されている。
【０００６】
【課題を解決するための手段】
上記課題を解決するための本発明のリードフレームは、複数の内部リードを有し、この内部リードの先端によって囲まれるとともに内部リードの先端とは離間した位置に半導体素子を搭載するためのダイパッドを配設したフレーム本体と、複数の内部リード上でかつその先端側に、複数の内部リード全てに跨がった状態で上記ダイパッドの周方向に沿って連続して設けられた枠状の絶縁体とを備えている。また、上記ダイパッドは、半導体素子の外形より小さい外形に形成されるとともに、上記枠状の絶縁体に囲まれた中空部の中央に位置するように配置されている。そして、上記複数の内部リードは、少なくとも上記絶縁体より後端側が導電性材料でメッキされてなるメッキ領域を有し、絶縁体は、このメッキ領域におけるメッキの厚みよりも厚く形成されている。
【０００７】
また本発明の半導体装置は、ダイパッドと、各々の先端部が前記ダイパッドの周縁近傍に離間して位置し、該ダイパッドの周縁近傍から離れる方向に延在するように設けられた複数のリードと、前記複数のリード上に絶縁体を介して配置され、前記ダイパッドよりサイズの大きい半導体素子と、前記ダイパッド、前記複数のリードそれぞれの一部、前記半導体素子をそれぞれ封止する樹脂とを有している。そして、前記絶縁体は枠の形状をしており、前記ダイパッドが、該枠に囲まれた中空部の中央に位置するように配置されている。
【０００８】
本発明のリードフレームでは、ダイパッドの外形が、搭載する半導体素子の外形より小さく形成され、内部リード上でかつその先端側にメッキ領域におけるメッキの厚みよりも厚い絶縁体が設けられているので、リードフレームにおいて絶縁体の上面が最も高い位置となる。よって、ダイパッド上に半導体素子を搭載する際には、ダイパッドとともに絶縁体が半導体素子の台座となるため、半導体素子の裏面が内部リードの上面位置よりも常に高く配置されることになる。また絶縁体が、複数の内部リードの全てに跨がった状態でダイパッドの周方向に沿って連続して設けられていることから、各内部リードの先端が絶縁体によって固定されるので、内部リードの先端のバタツキが防止される。
【０００９】
本発明の半導体装置では、複数のリード上に、枠状の絶縁体を介してダイパッドよりサイズの大きい半導体素子が搭載されることから、半導体素子とリードとの接触が防止される。さらに、リード上に絶縁体が設けられることで、リードの先端部のバタツキが防止されるため、半導体素子とリードとの接続の信頼性が向上する。
【００１０】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて説明する。
図１は本発明のリードフレームの一実施形態を示す平面図であり、図２は図１におけるＡ部の拡大平面図である。
このリードフレーム１は、樹脂封止パッケージライン１２内に複数の内部リード１３を有するフレーム本体１１と、複数の内部リード１３上でかつその先端側に設けられた絶縁体１８とを有して構成されている。
【００１１】
フレーム本体１１は、例えばＣｕや４２アロイ材等の合金からなり、複数の内部リード１３の先端によって囲まれる位置に、半導体素子を搭載するための例えば平面視略矩形状のダイパット１４が設けられている。このダイパッド１４は、搭載する半導体素子の外形より小さい外形に形成されており、各内部リード１３の先端が、互いにショートしない程度までダイパッド１４に向けて延びている。また各内部リード１３はそれぞれ、上記の絶縁体１８より後端側でかつ樹脂封止パッケージライン１２より内側が、ＡｕやＡｇ等の導電性材料で例えば１０ｎｍ程度の厚みにメッキされ、メッキ領域１７（図１および図２中ドットで示す部分）とされている。
【００１２】
またフレーム本体１１は、樹脂封止パッケージライン１２外に、半導体装置を製造する際の樹脂流れ止めとなるタイバー１５と、外部リード１６とを有して構成されている。
【００１３】
絶縁体１８は、例えば絶縁性と耐熱性とを兼ね備えたフッ素系樹脂、ポリイミド樹脂等の絶縁テープからなり、複数の内部リード１３上でかつその先端側に、複数の内部リード１３の全てに跨がった状態でダイパッド１４の周方向に沿って連続して設けられている。また絶縁体１８は、内部リード１３のメッキ領域１７におけるメッキの厚みよりも厚く形成されている。ここでは、ダイパッド１４が平面視略矩形状をなしていることから、絶縁体１８が平面視略矩形の枠状に形成され、絶縁体１８の枠の外周縁が搭載する半導体素子の周縁よりも大きく形成されている。また絶縁体１８は、１００ｎｍ程度の厚みに形成されている。そして複数の内部リード１３上でかつその先端側に、エポキシ系等の接着材により貼り付けられて固定されている。
【００１４】
このように構成されるリードフレーム１を形成するには、まずＣｕや４２アロイ材等の合金からなる薄板材を加工して上記形状のフレーム本体１１を形成し、次いで内部リード１３の所定位置をメッキしてメッキ領域１７を形成する。そして予め平面視略矩形の枠状に形成した絶縁テープを、接着材により内部リード１３上に貼り付け、あるいは絶縁テープを内部リード１３上に平面視略矩形の枠状に貼り付けて絶縁体１８を設け、このことによってリードフレーム１を得る。
【００１５】
またこのリードフレーム１を用いて半導体装置を製造するあたっては、図３に示すように、まずダイパッド１４上にＡｇペースト等の導電性接着材２１を塗布しておき、次いでダイパッド１４上に半導体素子２２を配置して接合する。
なお、リードフレーム１は、前述したようにダイパッド１４の外形が、搭載する半導体素子の外形より小さく形成され、内部リード１３上でかつその先端側にメッキ領域１７におけるメッキの厚みよりも厚い絶縁体１８が設けられているので、絶縁体１８の上面がリードフレーム１において最も高い位置となる。よって、ダイパッド１４上に半導体素子２２を配置する際には、ダイパッド１４とともに絶縁体１８が半導体素子２２の台座となり、この結果、ダイパッド１４上面と絶縁体１８の上面とに跨がって半導体素子２２が搭載された状態となる。
【００１６】
次いで金属細線２３により、半導体素子２２とメッキ領域１７の内部リード１３とを接続し、その後、半導体素子２２と内部リード１３とを樹脂２４により一体に封止する。以上の工程によって、本発明の半導体装置の一実施形態となる半導体装置２が製造される。
【００１７】
この半導体装置２に用いたリードフレーム１では、台座となる絶縁体１８の上面位置がメッキされた内部リード１３の上面位置よりも高く、したがって半導体素子２２の裏面が内部リード１３の上面位置よりも常に高く配置されるので、リードフレーム１にいずれのサイズの半導体素子２２を搭載しても、半導体素子２２と内部リード１３との接触を防止することができる。したがって、１種類のリードフレーム１が従来の何種類ものリードフレームの役割を果たすことになるので、このようなリードフレーム１を用いた半導体装置２は、製造に要する作業を簡略化でき、製造コストの低減を図ることができるものとなる。
【００１８】
またリードフレーム１では、絶縁体１８の上面位置がメッキされた内部リード１３の上面位置よりも高くなっているので、半導体装置２の製造に際して、半導体素子２２が所定の位置からずれて配置されても半導体素子２２と内部リード１３との接触を防止することができる。
さらに絶縁体１８が、複数の内部リード１３の全てに跨がった状態で、ダイパッド１４の周方向に沿って連続して設けられていることから、各内部リード１３の先端が絶縁体１８によって固定されているので、内部リード１３のバタツキを防止することができる。よって、このようなリードフレーム１を用いた半導体装置２は、半導体素子２２がいずれのサイズであっても、電気的信頼性が高いものとなる。
【００１９】
なお、本実施形態では、内部リードの絶縁体よりも後端側から樹脂封止パッケージラインまでをメッキ領域としたが、内部リードの先端側から樹脂封止パッケージラインまでをメッキ領域とすることもできる。この場合には、リード作成時のメッキマスクとして、ダイパッドおよび内部リードを含むメッキマスクと用いてメッキを行ってメッキ領域を形成し、次いでメッキされた内部リード上でかつその先端側に絶縁体を形成すればよい。
【００２０】
また本実施形態では、メッキ領域を樹脂封止パッケージラインまで形成したが、少なくとも内部リードの絶縁体よりも後端側にメッキ領域が形成されて、半導体素子と内部リードとが電気的に接続されれば任意に設定可能である。
さらに本実施形態では、絶縁体の枠の外周縁が搭載する半導体素子の周縁よりも大きく形成されているとしたが、絶縁体の枠の外周縁が搭載する半導体素子の周縁よりも小さく形成されていてもよい。この場合にも、半導体素子の裏面を内部リードの上面位置よりも常に高く配置できるので、当然のごとく上記実施形態と同様の効果を得ることができる。
【００２１】
【発明の効果】
以上説明したように本発明のリードフレームによれば、ダイパッドとともに絶縁体が搭載する半導体素子の台座となることから、半導体素子の裏面を内部リードの上面位置よりも常に高く配置することができるので、いずれのサイズの半導体素子を搭載することができ、また半導体素子が所定の位置よりずれて配置されても、半導体素子と内部リードとの接触を防止することができる。また各内部リードの先端が、複数の内部リードの全てに跨がった状態でダイパッドの周方向に沿って連続して設けられ絶縁体によって固定されるので、内部リードの先端のバタツキを防止することができる。
また本発明の半導体装置は、上記したリードフレームを用いることから、いずれのサイズの半導体素子が搭載されていても、また半導体素子が所定の位置よりずれて配置されていても、電気的信頼性が高いものとなる。また半導体装置の製造に要する作業を簡略化でき、このことにより製造コストの低減を図ることができるものとなる。
【図面の簡単な説明】
【図１】本発明のリードフレームの一実施形態を示す平面図である。
【図２】図１におけるＡ部の拡大平面図である。
【図３】本発明の半導体装置の一実施形態例を示す断面図である。
【図４】従来のリードフレームの一例を示す平面図である。
【図５】従来の半導体装置の一例を示す断面図である。
【符号の説明】
１ リードフレーム
２ 半導体装置
１１ フレーム本体
１３ 内部リード
１４ ダイパッド
１７ メッキ領域
１８ 絶縁体
２２ 半導体素子
２３ 金属細線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a lead frame and a resin-encapsulated semiconductor device using the lead frame.
[0002]
[Prior art]
As shown in FIG. 4, the conventional lead frame has a plurality of internal leads 33 whose tip side is plated with gold (Au) or silver (Ag) in the resin-sealed package line 32 of the frame body 31. A die pad 34, which is a base for mounting a semiconductor element, is provided at a position surrounded by the tips of the plurality of internal leads 33. In addition, the frame main body 31 is configured to have a tie bar 35 and an external lead 36 that serve as a resin flow stop when the semiconductor device is manufactured outside the resin-sealed package line 32.
[0003]
In manufacturing a resin-encapsulated semiconductor device using such a lead frame 3, a semiconductor element 42 is first bonded onto a die pad 34 via a conductive adhesive 41 as shown in FIG. 5. Next, the semiconductor element 42 thus mounted on the die pad 34 and the internal lead 33 are connected by a thin metal wire 43. Thereafter, the internal lead 33 and the semiconductor element 42 are integrally sealed with the resin 44, whereby the semiconductor device 4 is obtained.
[0004]
[Problems to be solved by the invention]
However, in the conventional lead frame described above, various types of lead frames must be prepared in order to make the size of the die pad and the length to the tip of the internal lead appropriate depending on the size of the semiconductor element. Therefore, a very complicated operation is required for manufacturing.
In addition, since the upper surface of the die pad is substantially at the same height as the upper surface of the internal lead, and the semiconductor element is mounted on the die pad only through the conductive adhesive 41, the semiconductor element is displaced from the die pad. In such a case, there is a problem that the semiconductor element and the internal lead are very easy to contact.
[0005]
Furthermore, at present, the number of necessary internal leads and external leads is increasing with the high integration of semiconductor elements, and since these leads are finely processed, the tip of the internal lead that is not fixed particularly at the tip side Flickering occurs. Such fluttering at the tip of the internal lead adversely affects the manufacturing of the semiconductor device, such as reducing the reliability of the connection between the semiconductor element mounted on the die pad and the internal lead by the fine metal wire.
Therefore, development of a lead frame and a semiconductor device capable of mounting a single type of various-sized semiconductor elements and manufacturing a highly reliable semiconductor device is desired.
[0006]
[Means for Solving the Problems]
A lead frame of the present invention for solving the above-described problems has a plurality of internal leads, and a die pad for mounting a semiconductor element at a position surrounded by the tips of the internal leads and separated from the tips of the internal leads. A frame-shaped insulator continuously provided along the circumferential direction of the die pad in a state where the frame main body is disposed on the plurality of internal leads and on the front end side of the frame main body, and straddles all of the plurality of internal leads. And. The die pad is formed to have an outer shape smaller than the outer shape of the semiconductor element, and is disposed so as to be positioned at the center of the hollow portion surrounded by the frame-shaped insulator. Each of the plurality of internal leads has a plated region in which at least the rear end side of the insulator is plated with a conductive material, and the insulator is formed thicker than the plating thickness in the plated region.
[0007]
Further, the semiconductor device of the present invention is a die pad, a plurality of leads provided so that each tip portion is spaced apart from the periphery of the die pad and extends away from the vicinity of the periphery of the die pad, wherein on the plurality of leads are disposed through an insulator, and a large semiconductor device of size than the die pad, the die pad, a portion of each of the plurality of leads, and a resin for sealing said semiconductor element, respectively Yes. The insulator has a frame shape, and the die pad is disposed so as to be positioned at the center of the hollow portion surrounded by the frame.
[0008]
In the lead frame of the present invention, the outer shape of the die pad is formed to be smaller than the outer shape of the semiconductor element to be mounted, and an insulator thicker than the plating thickness in the plating region is provided on the inner lead and on the tip side thereof. In the lead frame, the upper surface of the insulator is the highest position. Therefore, when the semiconductor element is mounted on the die pad, since the insulator serves as a base for the semiconductor element together with the die pad, the back surface of the semiconductor element is always disposed higher than the upper surface position of the internal lead. In addition, since the insulator is continuously provided along the circumferential direction of the die pad in a state of straddling all of the plurality of internal leads, the tip of each internal lead is fixed by the insulator. Fluctuation of the tip of the lead is prevented.
[0009]
In the semiconductor device of the present invention, a semiconductor element having a size larger than that of the die pad is mounted on a plurality of leads via a frame-like insulator, so that contact between the semiconductor element and the lead is prevented. Further, since the insulator is provided on the lead, the leading end of the lead is prevented from fluttering, so that the reliability of the connection between the semiconductor element and the lead is improved.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing an embodiment of the lead frame of the present invention, and FIG. 2 is an enlarged plan view of a portion A in FIG.
The lead frame 1 includes a frame main body 11 having a plurality of internal leads 13 in a resin-sealed package line 12, and an insulator 18 provided on the plurality of internal leads 13 and on the distal end side thereof. Has been.
[0011]
The frame body 11 is made of, for example, an alloy such as Cu or 42 alloy material, and a die pad 14 having a substantially rectangular shape in plan view for mounting a semiconductor element is provided at a position surrounded by the tips of the plurality of internal leads 13. Yes. The die pad 14 is formed in an outer shape smaller than the outer shape of the semiconductor element to be mounted, and the tips of the internal leads 13 extend toward the die pad 14 to the extent that they do not short-circuit each other. Each internal lead 13 is plated with a conductive material such as Au or Ag to a thickness of, for example, about 10 nm on the rear end side from the insulator 18 and inside the resin-encapsulated package line 12. (Portion indicated by dots in FIGS. 1 and 2).
[0012]
In addition, the frame body 11 includes a tie bar 15 that serves as a resin flow stopper when manufacturing a semiconductor device and an external lead 16 in addition to the resin-encapsulated package line 12.
[0013]
The insulator 18 is made of, for example, an insulating tape made of fluorine resin, polyimide resin, or the like that has both insulating properties and heat resistance. The insulator 18 extends over the plurality of internal leads 13 and on the distal end side of the plurality of internal leads 13. It is continuously provided along the circumferential direction of the die pad 14 in a bent state. The insulator 18 is formed thicker than the plating thickness in the plating region 17 of the internal lead 13. Here, since the die pad 14 has a substantially rectangular shape in plan view, the insulator 18 is formed in a substantially rectangular frame shape in plan view, and the outer peripheral edge of the frame of the insulator 18 is more than the peripheral edge of the semiconductor element to be mounted. Largely formed. The insulator 18 is formed to a thickness of about 100 nm. Then, it is affixed and fixed on the plurality of internal leads 13 to the front end side thereof with an epoxy-based adhesive or the like.
[0014]
In order to form the lead frame 1 configured as described above, a thin plate material made of an alloy such as Cu or 42 alloy material is first processed to form the frame main body 11 having the above shape, and then the predetermined position of the internal lead 13 is set. Plating region 17 is formed by plating. Then, an insulating tape previously formed in a substantially rectangular frame shape in plan view is attached to the internal lead 13 with an adhesive, or an insulating tape is attached to the internal lead 13 in a substantially rectangular frame shape in plan view. Thus, the lead frame 1 is obtained.
[0015]
In manufacturing a semiconductor device using the lead frame 1, as shown in FIG. 3, first, a conductive adhesive 21 such as an Ag paste is applied on the die pad 14, and then the semiconductor is formed on the die pad 14. The element 22 is disposed and bonded.
As described above, the lead frame 1 is an insulator in which the outer shape of the die pad 14 is smaller than the outer shape of the semiconductor element to be mounted, and is thicker than the plating thickness in the plating region 17 on the inner lead 13 and on the tip side. 18 is provided, the upper surface of the insulator 18 is at the highest position in the lead frame 1. Therefore, when the semiconductor element 22 is disposed on the die pad 14, the insulator 18 becomes the pedestal of the semiconductor element 22 together with the die pad 14. As a result, the semiconductor element 22 straddles the upper surface of the die pad 14 and the upper surface of the insulator 18. 22 is mounted.
[0016]
Next, the semiconductor element 22 and the internal lead 13 of the plating region 17 are connected by the fine metal wire 23, and then the semiconductor element 22 and the internal lead 13 are integrally sealed with a resin 24. Through the above steps, the semiconductor device 2 which is an embodiment of the semiconductor device of the present invention is manufactured.
[0017]
In the lead frame 1 used in the semiconductor device 2, the upper surface position of the insulator 18 serving as a pedestal is higher than the upper surface position of the plated internal lead 13, so that the back surface of the semiconductor element 22 is higher than the upper surface position of the internal lead 13. Since it is always arranged high, contact of the semiconductor element 22 and the internal lead 13 can be prevented regardless of the size of the semiconductor element 22 mounted on the lead frame 1. Accordingly, since one type of lead frame 1 serves as a number of types of conventional lead frames, the semiconductor device 2 using such a lead frame 1 can simplify the work required for manufacturing, and the manufacturing cost can be reduced. Can be reduced.
[0018]
In the lead frame 1, the upper surface position of the insulator 18 is higher than the upper surface position of the plated internal lead 13, so that the semiconductor element 22 is displaced from a predetermined position when the semiconductor device 2 is manufactured. Also, the contact between the semiconductor element 22 and the internal lead 13 can be prevented.
Furthermore, since the insulator 18 is continuously provided along the circumferential direction of the die pad 14 in a state of straddling all of the plurality of internal leads 13, the tip of each internal lead 13 is formed by the insulator 18. Since it is fixed, it is possible to prevent the internal lead 13 from flickering. Therefore, the semiconductor device 2 using such a lead frame 1 has high electrical reliability regardless of the size of the semiconductor element 22.
[0019]
In the present embodiment, the plating area extends from the rear end side to the resin-encapsulated package line from the insulator of the internal lead, but the plating area may also extend from the front end side of the internal lead to the resin-encapsulated package line. it can. In this case, plating is performed using a plating mask including a die pad and internal leads as a plating mask at the time of lead creation to form a plating region, and then an insulator is formed on the plated internal leads and on the tip side thereof. What is necessary is just to form.
[0020]
In this embodiment, the plating area is formed up to the resin-encapsulated package line. However, the plating area is formed at least on the rear end side of the insulator of the internal lead, and the semiconductor element and the internal lead are electrically connected. Can be set arbitrarily.
Further, in this embodiment, the outer peripheral edge of the insulator frame is formed larger than the peripheral edge of the semiconductor element to be mounted, but the outer peripheral edge of the insulator frame is formed smaller than the peripheral edge of the semiconductor element to be mounted. It may be. Also in this case, since the back surface of the semiconductor element can always be arranged higher than the position of the upper surface of the internal lead, it is possible to obtain the same effect as that of the above embodiment as a matter of course.
[0021]
【The invention's effect】
As described above, according to the lead frame of the present invention, since it becomes a pedestal of the semiconductor element mounted with the insulator together with the die pad, the back surface of the semiconductor element can always be disposed higher than the upper surface position of the internal lead. Any size of semiconductor element can be mounted, and even if the semiconductor element is displaced from a predetermined position, contact between the semiconductor element and the internal lead can be prevented. In addition, since the tip of each internal lead is provided continuously along the circumferential direction of the die pad in a state of straddling all of the plurality of internal leads and is fixed by an insulator, it prevents flickering of the tip of the internal lead. be able to.
In addition, since the semiconductor device of the present invention uses the above-described lead frame, the electrical reliability is ensured regardless of which size of semiconductor element is mounted or the semiconductor element is displaced from a predetermined position. Is expensive. In addition, the work required for manufacturing the semiconductor device can be simplified, which can reduce the manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a plan view showing an embodiment of a lead frame of the present invention.
FIG. 2 is an enlarged plan view of a portion A in FIG.
FIG. 3 is a cross-sectional view showing an embodiment of a semiconductor device of the present invention.
FIG. 4 is a plan view showing an example of a conventional lead frame.
FIG. 5 is a cross-sectional view showing an example of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Lead frame 2 Semiconductor device 11 Frame main body 13 Internal lead 14 Die pad 17 Plating area 18 Insulator 22 Semiconductor element 23 Metal fine wire

Claims (3)

半導体素子を搭載するためのリードフレームであって、
複数の内部リードを有し、該内部リードの先端によって囲まれるとともに該内部リードの先端とは離間した位置に、前記半導体素子を搭載するためのダイパッドを配設したフレーム本体と、
前記複数の内部リード上でかつその先端側に、該複数の内部リードの全てに跨がった状態で前記ダイパッドの周方向に沿って連続して設けられた枠状の絶縁体とを備え、
前記ダイパッドは、前記半導体素子の外形より小さい外形に形成されるとともに、前記枠状の絶縁体に囲まれた中空部の中央に位置するように配置されており、
前記複数の内部リードは、少なくとも前記絶縁体より後端側が導電性材料でメッキされてなるメッキ領域を有し、
前記絶縁体は、前記メッキ領域におけるメッキの厚みよりも厚く形成されてなる
ことを特徴とするリードフレーム。A lead frame for mounting a semiconductor element,
A frame main body having a plurality of internal leads, surrounded by a tip of the internal lead and spaced from the tip of the internal lead, and a die pad for mounting the semiconductor element;
On the plurality of internal leads and on the tip side thereof, a frame-like insulator provided continuously along the circumferential direction of the die pad in a state straddling all of the plurality of internal leads,
The die pad is formed to have an outer shape smaller than the outer shape of the semiconductor element, and is disposed so as to be positioned at the center of the hollow portion surrounded by the frame-shaped insulator ,
The plurality of internal leads have a plated region in which at least a rear end side of the insulator is plated with a conductive material,
The lead frame according to claim 1, wherein the insulator is formed thicker than a plating thickness in the plating region . ダイパッドと、
各々の先端部が前記ダイパッドの周縁近傍に離間して位置し、該ダイパッドの周縁近傍から離れる方向に延在するように設けられた複数のリードと、
前記複数のリード上に絶縁体を介して配置され、前記ダイパッドよりサイズの大きい半導体素子と、
前記ダイパッド、前記複数のリードそれぞれの一部、前記半導体素子をそれぞれ封止する樹脂とを有する半導体装置であって、
前記絶縁体は枠の形状をしており、前記ダイパッドが、該枠に囲まれた中空部の中央に位置するように配置される
ことを特徴とする半導体装置。Die pad,
A plurality of leads provided so that each tip portion is spaced apart in the vicinity of the periphery of the die pad and extends in a direction away from the vicinity of the periphery of the die pad;
A semiconductor element disposed on the plurality of leads via an insulator and having a size larger than that of the die pad;
A semiconductor device having the die pad, a part of each of the plurality of leads, and a resin for sealing the semiconductor element,
The insulator has a frame shape, and the die pad is disposed so as to be positioned at the center of a hollow portion surrounded by the frame. 前記樹脂にて封止される前記複数のリードそれぞれの一部にはメッキ層が設けられ、前記絶縁体の厚さは該メッキ層の厚さより厚い
ことを特徴とする請求項２記載の半導体装置。The semiconductor device according to claim 2 , wherein a plating layer is provided on a part of each of the plurality of leads sealed with the resin, and the thickness of the insulator is larger than the thickness of the plating layer. .
JP02881596A 1996-02-16 1996-02-16 Lead frame and semiconductor device Expired - Fee Related JP3644555B2 (en)

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JP3644555B2 true JP3644555B2 (en) 2005-04-27

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