JP2513044Y2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2513044Y2
JP2513044Y2 JP1991009777U JP977791U JP2513044Y2 JP 2513044 Y2 JP2513044 Y2 JP 2513044Y2 JP 1991009777 U JP1991009777 U JP 1991009777U JP 977791 U JP977791 U JP 977791U JP 2513044 Y2 JP2513044 Y2 JP 2513044Y2
Authority
JP
Japan
Prior art keywords
lead
external connection
island
semiconductor chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1991009777U
Other languages
Japanese (ja)
Other versions
JPH04107832U (en
Inventor
守 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1991009777U priority Critical patent/JP2513044Y2/en
Publication of JPH04107832U publication Critical patent/JPH04107832U/en
Application granted granted Critical
Publication of JP2513044Y2 publication Critical patent/JP2513044Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/37666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】[Detailed description of the device]

【０００１】[0001]

【産業上の利用分野】本考案は外形寸法を小さくできる
表面実装型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface-mounting type semiconductor device whose external dimensions can be reduced.

【０００２】[0002]

【従来の技術】従来より軽薄短小化を実現する１つの手
段として、プリント基板の導電パターン上にリードを対
向接着する所謂ＣＰ、ＭＣＰと称される表面実装型のミ
ニモールドパッケージがある（例えば、特開平０２−１
８４０５９号）。図５にその例を示す。同図において、
（１）は半導体チップ、（２）はチップ（１）を搭載す
るアイランド、（３）はチップ（１）上の電極パッドに
ワイヤ（４）で接続された外部接続リード、（５）は主
要部を封止する樹脂である。2. Description of the Related Art Conventionally, as one means for realizing lightness, thinness, shortness and miniaturization, there is a surface mount type mini mold package called CP or MCP in which leads are oppositely bonded on a conductive pattern of a printed circuit board (for example, Japanese Patent Laid-Open No. 02-1
84059). FIG. 5 shows an example thereof. In the figure,
(1) is a semiconductor chip, (2) is an island on which the chip (1) is mounted, (3) is an external connection lead connected to an electrode pad on the chip (1) by a wire (4), and (5) is a main It is a resin that seals the part.

【０００３】上記ミニモールドパッケージは、微細化が
押し進められた結果、外形寸法が１．６×０．８mm程度
まで小型化されている。As a result of further miniaturization, the mini-mold package has been reduced in size to an external dimension of about 1.6 × 0.8 mm.

【０００４】[0004]

【考案が解決しようとする課題】しかしながら、従来の
半導体装置はワイヤ（４）の位置精度を保つため、リー
ドフレームの打ち抜き加工に要する抜きしろ寸法
（ａ）、ワイヤ（４）のセカンドボンドエリアに要する
外部接続リード（３）の寸法（ｂ）、ワイヤ（４）のル
ープ高さに要する寸法（ｃ）、およびワイヤ（４）ルー
プ高さからの樹脂（５）の余裕に要する寸法（ｄ）が必
要になる。そのため外形寸法の更なる縮小が困難である
欠点があった。However, in the conventional semiconductor device, in order to maintain the positional accuracy of the wire (4), the clearance (a) required for punching the lead frame and the second bond area of the wire (4) are required. Required dimension (b) of the external connection lead (3), dimension (c) required for the loop height of the wire (4), and dimension (d) required for the margin of the resin (5) from the loop height of the wire (4). Will be required. Therefore, there is a drawback that it is difficult to further reduce the external dimensions.

【０００５】[0005]

【課題を解決するための手段】本考案は上記従来の欠点
に鑑み成されたもので、半導体チップ（１１）を搭載す
るアイランド（１２）と、アイランド（１２）に一体化
した外部接続リード（１４）と、チップ（１１）の表面
に形成した電極パッド（１５）と、電極パッド（１５）
に異方性導電接着剤（１７）にて対向接着された外部接
続リード（１６）と、主要部を封止する樹脂（１８）と
を具備することにより、外形寸法を縮小できるミニモー
ルド型の半導体装置を提供するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and includes an island (12) on which a semiconductor chip (11) is mounted, and an external connection lead () connected to the island (12). 14), electrode pads (15) formed on the surface of the chip (11), and electrode pads (15)
Of the mini-mold type, which is capable of reducing the external dimensions, by including external connection leads (16) that are oppositely bonded with an anisotropic conductive adhesive (17) and a resin (18) that seals the main part. A semiconductor device is provided.

【０００６】[0006]

【作用】本考案によれば、ワイヤ（４）を使用せず外部
接続リード（１６）を電極パッド（１５）に直付けする
ので、ワイヤボンドに要する寸法を無くすことができ
る。そのため、樹脂（１８）の外形寸法を縮小できる。According to the present invention, since the external connection lead (16) is directly attached to the electrode pad (15) without using the wire (4), the dimension required for wire bonding can be eliminated. Therefore, the outer dimensions of the resin (18) can be reduced.

【０００７】[0007]

【実施例】以下に本考案の一実施例を図面を参照しなが
ら詳細に説明する。図１と図２は夫々本考案の半導体装
置を示す断面図と平面図である。同図において、（１
１）は表面に通常のプレーナ技術によってトランジスタ
等の回路素子を形成した半導体チップ、（１２）は半導
体チップ（１１）を共晶半田（１３）等で固着するアイ
ランド、（１４）はアイランド（１２）と一体化されて
外部に延在し、前記トランジスタのコレクタ取出しとな
る外部接続リード、（１５）は半導体チップ（１１）の
表面にＡｌのホトエッチで形成された電極取出し用の接
続パッド、（１６）は接続パッド（１５）に対向接着さ
れて外部に延在し、前記トランジスタのベースおよびエ
ミッタの取出しとなる外部接続リード、（１７）は接続
パッド（１５）と外部接続リード（１６）とを電気的機
械的に接続するための異方性導電接着剤、（１８）は主
要部を封止するエポキシ系熱硬化性樹脂である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1 and 2 are a sectional view and a plan view, respectively, showing a semiconductor device of the present invention. In the figure, (1
1) is a semiconductor chip on the surface of which circuit elements such as transistors are formed by a normal planar technique, (12) is an island for fixing the semiconductor chip (11) with eutectic solder (13), etc., and (14) is an island (12). ), Which is integrated with the above and extends to the outside to serve as a collector extraction of the transistor, (15) is a connection pad for extracting an electrode formed by Al photoetching on the surface of the semiconductor chip (11), Reference numeral 16) is an external connection lead that is bonded to the connection pad (15) so as to face it and extends to the outside to take out the base and emitter of the transistor, and (17) is a connection pad (15) and an external connection lead (16). Anisotropic conductive adhesive for electrically and mechanically connecting the two, and (18) is an epoxy thermosetting resin that seals the main part.

【０００８】アイランド（１２）と外部接続リード（１
４）（１６）とは、肉厚０．１〜０．３mmの銅系板状素
材から打ち抜き加工したリードフレームにより形成さ
れ、その表面にはＡｇ、Ｎｉ等の金属メッキが処され
る。アイランド（１２）上への半導体チップ（１１）の
固着は、Ａｕ−Ｓｉ共晶等で行われている。異方性導電
接着剤（１７）は、母材としての絶縁材である厚さ０．
３mmのシリコーンゴムに導電繊維を縦に配向して埋め込
んだものか、又は厚さ２０〜３０μｍの絶縁性接着剤中
に直径７μｍ、長さ５０〜１００μｍのカーボン繊維を
並列配列したものである。カーボン繊維の代わりにハン
ダ粒子やＮｉ粒子等の導電粒子を用いたものもある。両
者共、接続パッド（１５）と外部接続リード（１６）と
の間に挟み込み、加圧又は加圧加熱することにより、接
続パッド（１５）と外部接続リード（１６）との電気的
機械的な接続を果たす外部接続リード（１６）の接着部
付近には、リードフレームのコイニング加工によって段
差（１９）が付けられている。この段差（１９）は、異
方性導電接着剤（１７）が流出するのを防止する役割を
果たす段差（１９）以降はやや上方に折り曲げられ、樹
脂（１８）外部に露出してから表面実装用にリードフォ
ーミングされる。尚、アイランド（１２）に一体化した
外部接続リード（１４）も同様にリードフォーミングさ
れる。The island (12) and the external connection lead (1
4) (16) is formed by a lead frame stamped from a copper-based plate material having a thickness of 0.1 to 0.3 mm, and the surface thereof is plated with a metal such as Ag or Ni. The semiconductor chip (11) is fixed onto the island (12) by Au-Si eutectic or the like. The anisotropic conductive adhesive (17) has a thickness of 0.
Conductive fibers are vertically oriented and embedded in 3 mm silicone rubber, or carbon fibers having a diameter of 7 μm and a length of 50 to 100 μm are arranged in parallel in an insulating adhesive having a thickness of 20 to 30 μm. There is also one in which conductive particles such as solder particles and Ni particles are used instead of carbon fibers. Both of them are sandwiched between the connection pad (15) and the external connection lead (16) and subjected to pressure or pressure heating so that the connection pad (15) and the external connection lead (16) are electromechanical. A step (19) is formed in the vicinity of the bonding portion of the external connection lead (16) for connection by coining the lead frame. The step (19) is bent slightly upward after the step (19) which plays a role of preventing the anisotropic conductive adhesive (17) from flowing out, and is exposed to the outside of the resin (18) and then surface-mounted. Is lead formed for. The external connection lead (14) integrated with the island (12) is also lead formed.

【０００９】上記半導体装置は、図３に示すリードフレ
ームＡ（２０）と、図４に示すリードフレームＢ（２
１）とに分離されたリードフレームで製造される。先ず
アイランド（１２）を形成したリードフレームＡ（２
０）に半導体チップ（１１）をダイボンドし、外部接続
リード（１６）を形成したリードフレームＢ（２１）の
接続部にあらかじめ異方性導電接着剤（１７）を塗布
し、そしてリードフレームＡ（２０）とリードフレーム
Ｂ（２１）とを重ね合わせるようにして接続パッド（１
５）と外部接続リード（１６）を接続し、樹脂モール
ド、リードフォーミングという工程で完成する。The above semiconductor device has a lead frame A (20) shown in FIG. 3 and a lead frame B (2) shown in FIG.
It is manufactured with the lead frame separated into 1) and. First, the lead frame A (2
0) is die-bonded with the semiconductor chip (11), and the anisotropic conductive adhesive (17) is applied in advance to the connection portion of the lead frame B (21) on which the external connection leads (16) are formed, and then the lead frame A ( 20) and the lead frame B (21) are overlapped with each other so that the connection pad (1
5) and the external connection lead (16) are connected, and the process of resin molding and lead forming is completed.

【００１０】斯る本願の半導体装置は、従来のＡｕワイ
ヤを使用しないので、セカンドボンドエリアに要する寸
法ｂとループ高さに要する寸法ｃが不要となる。さら
に、リードフレームを２体に分離するので、抜きしろａ
も不要となる。従って従来の半導体装置に比べて大幅に
小型化できる。Since the semiconductor device of the present application does not use the conventional Au wire, the dimension b required for the second bond area and the dimension c required for the loop height are unnecessary. In addition, the lead frame is separated into two parts,
Becomes unnecessary. Therefore, the size can be significantly reduced as compared with the conventional semiconductor device.

【００１１】[0011]

【考案の効果】このように、本発明によれば、ワイヤを
用いたことによる寸法の制限が無いので、従来の半導体
装置より一層小型化を押し進めることができる利点を有
する。さらに、外部接続リード（１６）に段差（１９）
を設けておけば、接着剤（１７）の流出による短絡事故
を未然に防止できる利点をも有する。さらに、Ａｕバン
プ技術と比較して、チップ（１１）の設計変更が不要で
あり、且つ製造が容易である利点をも有する。As described above, according to the present invention, since the size is not limited by using the wire, there is an advantage that the miniaturization can be further promoted as compared with the conventional semiconductor device. Furthermore, a step (19) is formed on the external connection lead (16).
If it is provided, there is also an advantage that a short circuit accident due to the outflow of the adhesive (17) can be prevented. Further, compared with the Au bump technique, there is an advantage that the design change of the chip (11) is unnecessary and the manufacturing is easy.

【図面の簡単な説明】[Brief description of drawings]

【図１】本考案を説明するための断面図である。FIG. 1 is a sectional view for explaining the present invention.

【図２】本考案を説明するための断面図である。FIG. 2 is a sectional view for explaining the present invention.

【図３】リードフレームＡ（２０）を示す平面図であ
る。FIG. 3 is a plan view showing a lead frame A (20).

【図４】リードフレームＢ（２１）を示す平面図であ
る。FIG. 4 is a plan view showing a lead frame B (21).

【図５】従来例を説明する断面図である。FIG. 5 is a cross-sectional view illustrating a conventional example.

Claims (2)

(57)【実用新案登録請求の範囲】(57) [Scope of utility model registration request] 【請求項１】 回路素子を形成した半導体チップと、 前記半導体チップを固着するアイランドと、 前記アイランドに連続して延在する外部接続リードと、 前記半導体チップの表面に形成した電極取り出し用の電
極パッドと、 前記前記電極パッドに先端が異方性導電接着剤にて固着
され延在する外部接続リードと、 前記半導体チップを含む主要部をモールドする樹脂とを
具備し、 前記アイランドとリードが金属板材料から成り、前記異
方性導電接着剤が前記リードの先端部分に選択的に設け
られ、 前記アイランドから延在する外部接続リードと前記電極
パッドに接続するリードとが前記樹脂の側面から導出さ
れて、表面実装用に折り曲げられていることを 特徴とす
る半導体装置。1. A semiconductor chip on which a circuit element is formed, an island for fixing the semiconductor chip, an external connection lead extending continuously to the island, and an electrode for electrode extraction formed on the surface of the semiconductor chip. A pad, an external connection lead having a tip fixed to the electrode pad with an anisotropic conductive adhesive and extending, and a resin for molding a main part including the semiconductor chip.
And the island and the lead are made of a metal plate material.
Directional conductive adhesive is selectively applied to the tip of the lead.
Is, the external connection leads extending from the island electrode
The lead connecting to the pad is led out from the side of the resin.
And a semiconductor device which is bent for surface mounting . 【請求項２】 前記外部接続リードの表面に前記異方性
導電接着剤の流動を停止するためのコイニング加工を施
したことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the surface of the external connection lead is subjected to coining processing for stopping the flow of the anisotropic conductive adhesive.
JP1991009777U 1991-02-27 1991-02-27 Semiconductor device Expired - Lifetime JP2513044Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991009777U JP2513044Y2 (en) 1991-02-27 1991-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991009777U JP2513044Y2 (en) 1991-02-27 1991-02-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04107832U JPH04107832U (en) 1992-09-17
JP2513044Y2 true JP2513044Y2 (en) 1996-10-02

Family

ID=31899996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991009777U Expired - Lifetime JP2513044Y2 (en) 1991-02-27 1991-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2513044Y2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511188B (en) * 2018-05-15 2024-02-27 山东晶导微电子股份有限公司 Patch capacitor packaging structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5271177A (en) * 1975-12-10 1977-06-14 Seiko Epson Corp Semiconductor device
JPS59128934A (en) * 1983-01-13 1984-07-25 Diesel Kiki Co Ltd Method of controlling fuel
JPS63152160A (en) * 1986-12-17 1988-06-24 Sumitomo Electric Ind Ltd Laed frame for semiconductor device

Also Published As

Publication number Publication date
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