JPH11260972A - Thin semiconductor device - Google Patents

Thin semiconductor device

Info

Publication number
JPH11260972A
JPH11260972A JP6183398A JP6183398A JPH11260972A JP H11260972 A JPH11260972 A JP H11260972A JP 6183398 A JP6183398 A JP 6183398A JP 6183398 A JP6183398 A JP 6183398A JP H11260972 A JPH11260972 A JP H11260972A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
lead
thinned
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6183398A
Other languages
Japanese (ja)
Inventor
Katsutoki Kasai
克時 笠井
Original Assignee
Sumitomo Metal Mining Co Ltd
住友金属鉱山株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd, 住友金属鉱山株式会社 filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP6183398A priority Critical patent/JPH11260972A/en
Publication of JPH11260972A publication Critical patent/JPH11260972A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using an inexpensive lead frame which can cope with the thinning and downsizing of the semiconductor device. SOLUTION: This is a thin semiconductor device using a lead frame not having a die pad as a semiconductor chip mount. In this case, the inner lead tip 2 whose chip mounting face side is thinned by etching or press processing is made a semiconductor chip 3 mount, and a semiconductor chip 3 is mounted on this mount through an insulating adhesive or a tape fitted with an insulating adhesive, and the electrode pad at the surface of the semiconductor chip 3 and the inner lead part 2 not thinned are bonded with each other by wire 7, and these are sealed with resin to get a complete semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a thin semiconductor device using a lead frame.

[0002]

2. Description of the Related Art There are many conventional resin-sealed semiconductor devices using a lead frame. The reason is said to be that it can be manufactured at low cost. In a conventional surface mount type package, a semiconductor chip is mounted on the die pad of a lead frame, and the electrode pads on the semiconductor chip and the inner leads are wire-bonded, resin-sealed, and the outer leads are bent and the printed wiring board is bent. And so on. For this reason, the package size increases.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device using an inexpensive lead frame that can cope with thinning and miniaturization of a semiconductor device.

[0004]

SUMMARY OF THE INVENTION The present invention, which solves the above-mentioned problems, is a thin semiconductor device using a lead frame having no die pad as a semiconductor chip mounting portion, wherein the chip mounting surface is thinned by etching or pressing. The tip of the inner lead is used as the semiconductor chip mounting part, and the semiconductor chip is mounted on this mounting part via an insulating adhesive or a tape with insulating adhesive, and the inner pad that is not thinned with the electrode pads on the semiconductor chip surface It is obtained by wire bonding with a lead portion and resin sealing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a semiconductor chip is mounted on a thinned inner lead, so that the semiconductor device can be made thinner and the whole can be made smaller.

In order to obtain the semiconductor device of the present invention, for example,
The inner lead portion is obtained by etching a lead frame as shown in FIG. Next, an insulating tape 1 having an adhesive applied to both surfaces is attached to the inner lead portion 2 having a reduced thickness as shown in FIG. Then, as shown in FIG. 3, the center of the tape was punched out using a punching die.
As shown in FIG.
Then, the electrode pads 5 on the surface of the semiconductor chip are bonded to the non-thinned portions 6 of the inner leads by wire bonding 7. Thereafter, as shown in FIG. 5, resin sealing 9 is performed to obtain a semiconductor device.

For mounting the semiconductor device of the present invention on a printed wiring board, outer leads 8 may be used. The outer leads are cut off as shown in FIG. The electrodes of the plate may be bump-bonded.

[0008]

According to the semiconductor device of the present invention, a lead frame having no inner pad and having an inner lead with a thinner semiconductor chip mounting portion is used, so that the semiconductor device can be made thinner.

Further, since a lead frame is used, the manufacturing cost of the semiconductor device of the present invention is low.

[Brief description of the drawings]

FIG. 1 is a view showing an inner lead portion of a lead frame for obtaining a semiconductor device of the present invention.

FIG. 2 is a diagram showing a position where an insulating tape is attached to a thinned portion of an inner lead portion.

FIG. 3 is a diagram in which a center portion of a tape of a thinned inner lead portion is punched using a punching die.

FIG. 4 is a diagram in which a semiconductor chip is attached to a tape portion of an inner lead.

FIG. 5 is a diagram in which an electrode pad on the surface of a semiconductor chip is wire-bonded to an unreduced portion of an inner lead.

FIG. 6 is a diagram in which an outer lead is cut.

[Explanation of symbols]

 1 ---- Insulating tape 2--Inner lead portion 3--Semiconductor chip 4--Tape portion 5--Electrode pad 6 ---- Un-thinned portion 7 ---- Wire bonding 8-- -Outer lead 9 ---- Resin sealing 10 ---- Lower part of inner lead

Claims (1)

[Claims]
1. A thin semiconductor device using a lead frame having no die pad as a semiconductor chip mounting portion, wherein a tip portion of an inner lead whose chip mounting surface is thinned by etching or press working is used as a semiconductor chip mounting portion. A semiconductor chip is mounted on this mounting portion via an insulating adhesive or a tape with an insulating adhesive, and the electrode pads on the surface of the semiconductor chip and the unreduced inner lead portions are wire-bonded and resin-sealed. A thin semiconductor chip obtained.
JP6183398A 1998-03-13 1998-03-13 Thin semiconductor device Pending JPH11260972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6183398A JPH11260972A (en) 1998-03-13 1998-03-13 Thin semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6183398A JPH11260972A (en) 1998-03-13 1998-03-13 Thin semiconductor device

Publications (1)

Publication Number Publication Date
JPH11260972A true JPH11260972A (en) 1999-09-24

Family

ID=13182504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6183398A Pending JPH11260972A (en) 1998-03-13 1998-03-13 Thin semiconductor device

Country Status (1)

Country Link
JP (1) JPH11260972A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237565A (en) * 2001-02-08 2002-08-23 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
US7161232B1 (en) * 2004-09-14 2007-01-09 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages
KR100729028B1 (en) 2002-05-14 2007-06-14 앰코 테크놀로지 코리아 주식회사 Lead frame of tape formation and semiconduct package using it

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237565A (en) * 2001-02-08 2002-08-23 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same
JP4637380B2 (en) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 Semiconductor device
KR100729028B1 (en) 2002-05-14 2007-06-14 앰코 테크놀로지 코리아 주식회사 Lead frame of tape formation and semiconduct package using it
US7161232B1 (en) * 2004-09-14 2007-01-09 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages
US7419855B1 (en) 2004-09-14 2008-09-02 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages

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