JPH11260972A - Thin semiconductor device - Google Patents
Thin semiconductor deviceInfo
- Publication number
- JPH11260972A JPH11260972A JP6183398A JP6183398A JPH11260972A JP H11260972 A JPH11260972 A JP H11260972A JP 6183398 A JP6183398 A JP 6183398A JP 6183398 A JP6183398 A JP 6183398A JP H11260972 A JPH11260972 A JP H11260972A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor chip
- inner lead
- thinned
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置、特にリ
ードフレームを用いた薄型の半導体装置に関する。The present invention relates to a semiconductor device, and more particularly, to a thin semiconductor device using a lead frame.
【０００２】[0002]
【従来の技術】従来より用いられている樹脂封止型の半
導体装置にはリードフレームを用いたものが多い。その
理由は低コストで製造できることといわれている。ま
た、従来の表面実装型のパッケージではリードフレーム
のダイパット部に半導体チップを搭載し、半導体チップ
上の電極パッドとインナーリードとをワイヤーボンディ
ングし、樹脂封止し、アウターリードを折り曲げてプリ
ント配線板などに接続できるようにしている。このた
め、パッケージサイズが大きくなってしまう。2. Description of the Related Art There are many conventional resin-sealed semiconductor devices using a lead frame. The reason is said to be that it can be manufactured at low cost. In a conventional surface mount type package, a semiconductor chip is mounted on the die pad of a lead frame, and the electrode pads on the semiconductor chip and the inner leads are wire-bonded, resin-sealed, and the outer leads are bent and the printed wiring board is bent. And so on. For this reason, the package size increases.
【０００３】[0003]
【発明が解決しようとする課題】本発明は上記状況に鑑
みてなされたものであり、半導体装置の薄型化、小型化
に対応できる安価なリードフレームを用いた半導体装置
の提供を課題とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device using an inexpensive lead frame that can cope with thinning and miniaturization of a semiconductor device.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決する本発
明は、半導体チップ搭載部としてダイパットを有さない
リードフレームを用いる薄型半導体装置であり、チップ
搭載面側をエッチング、あるいはプレス加工により薄肉
化したインナーリード先端部を半導体チップ搭載部と
し、この搭載部に絶縁性接着剤あるいは絶縁性接着剤つ
きテープを介して半導体チップを搭載し、半導体チップ
表面の電極パッドと薄肉化されていないインナーリード
部とをワイヤボンデイングし、樹脂封止して得たもので
ある。SUMMARY OF THE INVENTION The present invention, which solves the above-mentioned problems, is a thin semiconductor device using a lead frame having no die pad as a semiconductor chip mounting portion, wherein the chip mounting surface is thinned by etching or pressing. The tip of the inner lead is used as the semiconductor chip mounting part, and the semiconductor chip is mounted on this mounting part via an insulating adhesive or a tape with insulating adhesive, and the inner pad that is not thinned with the electrode pads on the semiconductor chip surface It is obtained by wire bonding with a lead portion and resin sealing.
【０００５】[0005]
【発明の実施の形態】本発明の半導体装置は薄肉化した
インナーリードの上に半導体チップを搭載するため、半
導体装置を薄肉化でき、かつ全体を小さくすることが可
能である。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a semiconductor chip is mounted on a thinned inner lead, so that the semiconductor device can be made thinner and the whole can be made smaller.
【０００６】本発明の半導体装置を得るには、例えば、
インナーリード部が図１に示されるようなリードフレー
ムをエッチングにより得る。次いで、両面に接着剤が塗
布された絶縁性テープ１を図２のように薄肉化されたイ
ンナーリード部２に張り付ける。そして、図３のように
テープの中央部を打ち抜き金型を用いて打ち抜き、図４
のように半導体チップ３をインナーリードのテープ部４
に張り付け、半導体チップ表面の電極パッド５とインナ
ーリードの薄肉化していない部分６とをワイヤボンディ
ング７する。その後、図５のように樹脂封止９して半導
体装置を得る。In order to obtain the semiconductor device of the present invention, for example,
The inner lead portion is obtained by etching a lead frame as shown in FIG. Next, an insulating tape 1 having an adhesive applied to both surfaces is attached to the inner lead portion 2 having a reduced thickness as shown in FIG. Then, as shown in FIG. 3, the center of the tape was punched out using a punching die.
As shown in FIG.
Then, the electrode pads 5 on the surface of the semiconductor chip are bonded to the non-thinned portions 6 of the inner leads by wire bonding 7. Thereafter, as shown in FIG. 5, resin sealing 9 is performed to obtain a semiconductor device.
【０００７】本発明の半導体装置をプリント配線板に搭
載するにはアウターリード８を用いても良く、図６のよ
うにアウターリードを切断し、外部に突出したインナー
リード部の下部１０とプリント配線板の電極とをバンプ
接合しても良い。For mounting the semiconductor device of the present invention on a printed wiring board, outer leads 8 may be used. The outer leads are cut off as shown in FIG. The electrodes of the plate may be bump-bonded.
【０００８】[0008]
【発明の効果】本発明の半導体装置では、ダイパットの
ない、かつ半導体チップ搭載部を薄肉化したインナーリ
ードを有するリードフレームを使用するため、半導体装
置を薄肉化できる。According to the semiconductor device of the present invention, a lead frame having no inner pad and having an inner lead with a thinner semiconductor chip mounting portion is used, so that the semiconductor device can be made thinner.
【０００９】また、リードフレームを利用するため、本
発明の半導体装置の製造コストは安価なものとなる。Further, since a lead frame is used, the manufacturing cost of the semiconductor device of the present invention is low.
【図１】本発明の半導体装置を得るためのリードフレー
ムのインナーリード部を示した図である。FIG. 1 is a view showing an inner lead portion of a lead frame for obtaining a semiconductor device of the present invention.
【図２】インナーリード部の薄肉化された部分に絶縁テ
ープを貼り付ける位置を示した図である。FIG. 2 is a diagram showing a position where an insulating tape is attached to a thinned portion of an inner lead portion.
【図３】薄肉化されたインナーリード部のテープの中央
部を打ち抜き金型を用いて打ち抜いた図である。FIG. 3 is a diagram in which a center portion of a tape of a thinned inner lead portion is punched using a punching die.
【図４】半導体チップをインナーリードのテープ部に張
り付けた図である。FIG. 4 is a diagram in which a semiconductor chip is attached to a tape portion of an inner lead.
【図５】半導体チップ表面の電極パッドとインナーリー
ドの薄肉化していない部分とをワイヤボンディングした
図である。FIG. 5 is a diagram in which an electrode pad on the surface of a semiconductor chip is wire-bonded to an unreduced portion of an inner lead.
【図６】アウターリードを切断した図である。FIG. 6 is a diagram in which an outer lead is cut.
１−−−絶縁性テープ ２−−−インナーリード部 ３−−−半導体チップ ４−−−テープ部 ５−−−電極パッド ６−−−薄肉化していない部分 ７−−−ワイヤボンディング ８−−−アウターリード ９−−−樹脂封止 10−−−インナーリード部の下部 1 ---- Insulating tape 2--Inner lead portion 3--Semiconductor chip 4--Tape portion 5--Electrode pad 6 ---- Un-thinned portion 7 ---- Wire bonding 8-- -Outer lead 9 ---- Resin sealing 10 ---- Lower part of inner lead
Claims (1)
を有さないリードフレームを用いる薄型半導体装置であ
り、チップ搭載面側をエッチング、あるいはプレス加工
により薄肉化したインナーリード先端部を半導体チップ
搭載部とし、この搭載部に絶縁性接着剤あるいは絶縁性
接着剤つきテープを介して半導体チップを搭載し、半導
体チップ表面の電極パッドと薄肉化されていないインナ
ーリード部とをワイヤボンデイングし、樹脂封止して得
たことを特徴とする薄型半導体チップ。1. A thin semiconductor device using a lead frame having no die pad as a semiconductor chip mounting portion, wherein a tip portion of an inner lead whose chip mounting surface is thinned by etching or press working is used as a semiconductor chip mounting portion. A semiconductor chip is mounted on this mounting portion via an insulating adhesive or a tape with an insulating adhesive, and the electrode pads on the surface of the semiconductor chip and the unreduced inner lead portions are wire-bonded and resin-sealed. A thin semiconductor chip obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6183398A JPH11260972A (en) | 1998-03-13 | 1998-03-13 | Thin semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6183398A JPH11260972A (en) | 1998-03-13 | 1998-03-13 | Thin semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11260972A true JPH11260972A (en) | 1999-09-24 |
Family
ID=13182504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6183398A Pending JPH11260972A (en) | 1998-03-13 | 1998-03-13 | Thin semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11260972A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237565A (en) * | 2001-02-08 | 2002-08-23 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2005191158A (en) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US7161232B1 (en) * | 2004-09-14 | 2007-01-09 | National Semiconductor Corporation | Apparatus and method for miniature semiconductor packages |
| KR100729028B1 (en) * | 2002-05-14 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Lead frame of tape formation and semiconduct package using it |
-
1998
- 1998-03-13 JP JP6183398A patent/JPH11260972A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002237565A (en) * | 2001-02-08 | 2002-08-23 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP4637380B2 (en) * | 2001-02-08 | 2011-02-23 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| KR100729028B1 (en) * | 2002-05-14 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Lead frame of tape formation and semiconduct package using it |
| JP2005191158A (en) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US7161232B1 (en) * | 2004-09-14 | 2007-01-09 | National Semiconductor Corporation | Apparatus and method for miniature semiconductor packages |
| US7419855B1 (en) | 2004-09-14 | 2008-09-02 | National Semiconductor Corporation | Apparatus and method for miniature semiconductor packages |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3007023B2 (en) | Semiconductor integrated circuit and method of manufacturing the same | |
| JP3230348B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| JP3243116B2 (en) | Semiconductor device | |
| US7338838B2 (en) | Resin-encapsulation semiconductor device and method for fabricating the same | |
| JP2569939B2 (en) | Resin-sealed semiconductor device | |
| KR19990083550A (en) | Molded semiconductor device and method for manufacturing the same, lead frame | |
| JP2001015668A (en) | Resin-sealed semiconductor package | |
| JPH11260972A (en) | Thin semiconductor device | |
| JP3427492B2 (en) | Semiconductor device with convex heat sink and method of manufacturing the convex heat sink | |
| JPH09307051A (en) | Semiconductor device sealed by resin and method of manufacturing it | |
| JP2908350B2 (en) | Semiconductor device | |
| JP2716405B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2533012B2 (en) | Surface mount semiconductor device | |
| JP3317010B2 (en) | Electronic equipment | |
| JP2533011B2 (en) | Surface mount semiconductor device | |
| JP2006269719A (en) | Electronic device | |
| JP2788011B2 (en) | Semiconductor integrated circuit device | |
| JP4961636B2 (en) | Non-contact type IC card and manufacturing method thereof | |
| JP2002353395A (en) | Manufacturing method of lead frame, the lead frame and semiconductor device | |
| JP2513044Y2 (en) | Semiconductor device | |
| JPS61241954A (en) | Semiconductor device | |
| JPH11219969A (en) | Semiconductor device | |
| JP3082507U (en) | Double side chip package | |
| KR20030083561A (en) | Resin-sealed semiconductor device | |
| JP3013611B2 (en) | Method for manufacturing semiconductor device |