JP3082507U - Double side chip package - Google Patents
Double side chip packageInfo
- Publication number
- JP3082507U JP3082507U JP2001003678U JP2001003678U JP3082507U JP 3082507 U JP3082507 U JP 3082507U JP 2001003678 U JP2001003678 U JP 2001003678U JP 2001003678 U JP2001003678 U JP 2001003678U JP 3082507 U JP3082507 U JP 3082507U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead
- mounting portion
- lead frame
- double side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 実装コストを押さえ折曲ダウンセットの不要
なダブルサイドチップパッケージを提供する。
【解決手段】 ＬＯＣ形のリードフレームは所定数のリ
ード２３を有し、各リードは内より外へ搭載部２３１、
インナーリード部２３２とアウトリード部２３３に分け
られる。上チップ２１の上表面にははんだパッドを有
し、上チップ２１の下表面はリード搭載部２３１の上方
に固定され、下チップ２２の下表面には所定数のはんだ
パッドを有し、下チップ２２の上表面はリード搭載部２
３１の下方に固定される。導電ワイヤ２６で上チップ２
１のはんだパッドおよび対応するリードのインナーリー
ド部２３２と、下チップ２２のはんだパッドおよび対応
するリードのインナーリード部２３２とを電気的に連結
し、上チップ２１、下チップ２２、導電ワイヤ２６とリ
ードフレームのリードの搭載部２３１およびインナーリ
ード部２３２はパッケージ胴体２７により封止される。
(57) [Summary] [PROBLEMS] To provide a double-sided chip package which suppresses mounting cost and does not require a folded downset. SOLUTION: The LOC type lead frame has a predetermined number of leads 23, and each lead is mounted from inside to outside on a mounting portion 231.
It is divided into an inner lead part 232 and an out lead part 233. The upper surface of the upper chip 21 has solder pads, the lower surface of the upper chip 21 is fixed above the lead mounting portion 231, the lower surface of the lower chip 22 has a predetermined number of solder pads, 22 is the lead mounting part 2
31 is fixed below. Upper chip 2 with conductive wire 26
1 and the inner lead portion 232 of the corresponding lead and the solder pad of the lower chip 22 and the inner lead portion 232 of the corresponding lead are electrically connected to each other, and the upper chip 21, the lower chip 22, the conductive wire 26 and The lead mounting portion 231 and the inner lead portion 232 of the lead frame are sealed by the package body 27.
Description
【０００１】[0001]
本考案はダブルサイドチップパッケージに関する。 The present invention relates to a double side chip package.
【０００２】[0002]
従来の半導体装置は１つの熱硬化性合成物（ｔｈｅｒｍｏｓｅｔｔｉｎｇ ｌ ｉｑｕｉｄ ｃｏｍｐｏｕｎｄ）で半導体チップを覆うのでチップの防塵性と防 湿性を高める。チップのＩ／Ｏ端子はリードフレームに対応するリードより引出 されて回路基板に表面結合（ｓｕｒｆａｃｅ ｍｏｕｎｔｉｎｇ）することに使 われている。 A conventional semiconductor device covers a semiconductor chip with one thermosetting liquid compound, thereby improving the dustproof and moistureproof properties of the chip. The I / O terminals of the chip are drawn out from leads corresponding to the lead frame and are used for surface mounting to a circuit board.
【０００３】 ＬＯＣ形リードフレームと言うのはリードーオンーチップ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）形リードフレームの略語である。即ち、このリードフレームのリード をチップ上に延ばせることよりチップを固着と電気的に連結し、リードフレーム のダイパッド（ｄｉｅ ｐａｄ）を使用せずにチップをも粘着することができる 。[0003] The LOC type lead frame is an abbreviation for a lead-on-chip type lead frame. That is, by extending the leads of the lead frame onto the chip, the chip is electrically connected to the fixation, and the chip can be adhered without using the die pad of the lead frame.
【０００４】 米国特許Ｎｏ６，１１８，１７６に一種のダブルチップパッケージ構造１０が 提出されている。図１に示すように、このダブルチップパッケージ１０は１つの ＬＯＣ形リードフレームを有し、接着剤１４（ａｄｈｅｓｉｖｅ ｆｉｌｍ）で 上チップ１１と下チップ１２を背向きして粘着する。このＬＯＣ形リードフレー ムのリード１３は下チップ１２の下表面に延びて他の種の接着剤１５で固定され ることよって、導電ワイヤ１６で下チップ１２のはんだパッドとリード１３は連 結する用になり、そして，上チップ１１の上表面に１つのホールがある回路基板 １８を粘着することによって、導電ワイヤ１６で上チップ１１のはんだパッドと 回路基板１８を、および回路基板１８とリード１３を夫々連結して、再び１つの パッケージ胴体１７を用いて上記のダブルチップ結合構造を封止する。A type of double chip package structure 10 is proposed in US Pat. No. 6,118,176. As shown in FIG. 1, the double chip package 10 has one LOC type lead frame, and the upper chip 11 and the lower chip 12 are adhered to each other with an adhesive 14 (adhesive film). The lead 13 of the LOC-type lead frame extends to the lower surface of the lower chip 12 and is fixed with another kind of adhesive 15, so that the conductive pad 16 connects the solder pad of the lower chip 12 with the lead 13. By bonding the circuit board 18 having one hole on the upper surface of the upper chip 11, the conductive pads 16 are used to connect the solder pads of the upper chip 11 and the circuit board 18, and the circuit board 18 and the leads 13. Are connected to each other, and the above-mentioned double-chip connection structure is sealed again using one package body 17.
【０００５】[0005]
従来の構造では、上チップ１１の上表面に回路基板１８を置き、且つ間接的に 多数の点をワイヤーボンディングする必要があるので、（上チップ１１より回路 基板１８に、又は回路基板１８よりリードフレームのリード１３に）実装するコ ストが増える。尚、樹脂を入れる時に均衡な上下モールディングフロウ（ｍｏｌ ｄｉｎｇ ｆｌｏｗ）を得るため、このＬＯＣ形リードフレームのリード１３を 適当な折曲ダウンセット（ｄｏｗｎｓｅｔ）にしなければならないので、このダ ブルチップパッケージ１０は特殊形のＬＯＣリードフレームを必要とする。 したがって本考案の目的は、実装コストを押さえ折曲ダウンセットの不要なダ ブルサイドチップパッケージ（ｄｏｕｂｌｅ ｓｉｄｅ ｃｈｉｐ ｐａｃｋａ ｇｅ）を提供することにある。 In the conventional structure, it is necessary to place the circuit board 18 on the upper surface of the upper chip 11 and indirectly wire-bond a large number of points. The cost to mount (on the lead 13 of the frame) increases. In order to obtain a balanced molding flow when the resin is charged, the leads 13 of the LOC type lead frame must be appropriately bent downsets. Require a specially shaped LOC lead frame. Accordingly, an object of the present invention is to provide a double-sided chip package that requires no bending downset while keeping the mounting cost low.
【０００６】[0006]
上述の目的を達成するために、本考案の請求項に記載のダブルサイドチップパ ッケージは、ＬＯＣ形リードフレーム、上チップ、下チップ、所定数の導電ワイ ヤとパッケージ胴体を含む。ＬＯＣ形リードフレームは所定数のリードを有し、 各リードは内より外へ搭載部、インナーリード部とアウトリード部に分けられる 。上チップの上表面には複数のはんだパッド（ｂｏｎｄｉｎｇ ｐａｄ）を有し 、上チップの下表面はリードフレームのリード搭載部の上方に固定されている。 下チップの下表面には所定数のはんだパッドを有し、下チップの上表面はリード フレームのリード搭載部の下方に固定されている。次に、複数の導電ワイヤで上 チップのはんだパッドおよびこのはんだパッドに対応するリードのインナーリー ド部と、下チップのはんだパッドおよびこのはんだパッドに対応するリードのイ ンナーリード部とをそれぞれ電気的に連結した後、上チップ、下チップ、導電ワ イヤとリードフレームのリードの搭載部およびインナーリード部はパッケージ胴 体により封止される。 To achieve the above object, a double side chip package according to the present invention includes a LOC type lead frame, an upper chip, a lower chip, a predetermined number of conductive wires and a package body. The LOC type lead frame has a predetermined number of leads, and each lead is divided into a mounting part, an inner lead part, and an out lead part from inside to outside. The upper surface of the upper chip has a plurality of bonding pads, and the lower surface of the upper chip is fixed above the lead mounting portion of the lead frame. The lower surface of the lower chip has a predetermined number of solder pads, and the upper surface of the lower chip is fixed below the lead mounting portion of the lead frame. Next, a plurality of conductive wires electrically connect the upper chip solder pad and the inner lead portion of the lead corresponding to the solder pad, and the lower chip solder pad and the inner lead portion of the lead corresponding to the solder pad, respectively. Then, the upper chip, the lower chip, the conductive wire and the mounting portion of the lead of the lead frame, and the inner lead portion are sealed with the package body.
【０００７】[0007]
以下、本考案の実施例を図面に基づいて説明する。 図２、図３に示すように本考案の第一実施例によるダブルサイドチップパッケ ージ２０は主にＬＯＣ形リードフレーム、上チップ２１、下チップ２２とパッケ ージ胴体２７を含む。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 2 and 3, the double side chip package 20 according to the first embodiment of the present invention mainly includes a LOC type lead frame, an upper chip 21, a lower chip 22, and a package body 27.
【０００８】 ＬＯＣ形リードフレームは、リードオンチップ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ） 形のリードフレームであり、現在よく利用されているスタムピング(ｓｔａｍｐ ｉｎｇ)或いはエッチング（ｅｔｃｈｉｎｇ）の方法で１つの薄鋼板や薄銅版よ り作出され、複数のリード２３を有する。各リード２３は内より外へ搭載部２３ １、インナーリード部２３２とアウトリード部２３３に分けられる。搭載部２３ １は上チップ２１と下チップ２２の間に位置して上チップ２１と下チップ２２を 搭載する用になり、インナーリード部２３２はワイヤボンディング区２８の内に 位置し、導電ワイヤ２６と連結するリード２３の接続所である。アウトリード部 ２３３は樹脂封止区２９の外に位置してこのダブルサイドチップパッケージ２０ の電気的な外接端子として使われている。リード２３の搭載部２３１は内へ上チ ップ２１と下チップ２２との間まで延びるので、このＬＯＣ形リードフレームは リードが両チップの間におる（ｌｅａｄ ｂｅｔｗｅｅｎ ｄｏｕｂｌｅ ｃｈ ｉｐｓ）と見られる一種のリードフレームである。リード２３は同時に上チツプ ２１と下チップ２２とを搭載し、上チップ２１と下チップ２２に挟められること より、良好な固着性を持つ。従って図２に示すように、各リード２３の搭載部２ ３１とインナーリード部２３２は同一平面に形成され、リード２３を折曲げなく ても良い固着性を持つことが可能となる。搭載部２３１とインナーリード部２３ ２は上チップ２１と下チップ２２との間の所定幅平面Ｐ１に形成され、１対１の 比率で上下鋳型の内に封止合成物（ｍｏｌｄｉｎｇ ｃｏｍｐｏｕｎｄ）を注入 し、これは焼く前のパッケージ胴体２７であり、リード２３を折曲げなくもモー ルディングフロウバランス（ｍｏｌｄｉｎｇ ｆｌｏｗ ｂａｌａｎｃｅ）の効 果を持つ。封止した後、リード２３のアウトリード部２３３は鴎翼形或いは他の 形（ＩかＪの形）になる。The LOC-type lead frame is a lead-on-chip type lead frame, and is manufactured by using a thin steel plate or a thin copper plate by a stamping method or an etching method which is widely used at present. And has a plurality of leads 23. Each lead 23 is divided into a mounting part 231, an inner lead part 232, and an out lead part 233 from inside to outside. The mounting portion 231 is located between the upper chip 21 and the lower chip 22 for mounting the upper chip 21 and the lower chip 22, and the inner lead portion 232 is located in the wire bonding section 28 and the conductive wire 26 This is a connection point of the lead 23 to be connected. The outlead portion 233 is located outside the resin sealing section 29 and is used as an electrical external terminal of the double side chip package 20. Since the mounting portion 231 of the lead 23 extends inward between the upper chip 21 and the lower chip 22, this LOC-type lead frame is a kind in which the lead is considered to be between the two chips (lead between chips). Is a lead frame. The lead 23 has an upper chip 21 and a lower chip 22 mounted thereon at the same time, and has good adhesion because it is sandwiched between the upper chip 21 and the lower chip 22. Therefore, as shown in FIG. 2, the mounting portion 231 and the inner lead portion 232 of each lead 23 are formed on the same plane, and it is possible to have a fixing property that does not require the lead 23 to be bent. The mounting portion 231 and the inner lead portion 232 are formed on a predetermined width plane P1 between the upper chip 21 and the lower chip 22, and a molding compound is injected into the upper and lower molds at a ratio of 1: 1. However, this is the package body 27 before baking, and has the effect of a molding flow balance without bending the lead 23. After sealing, the outlead portion 233 of the lead 23 has a gull-wing shape or another shape (I or J shape).
【０００９】 上チップ２１は上記リード２３の搭載部２３１の上に固着されて、１つの絶縁 性第一テープ２４（ポリイミド材質，ｐｏｌｙｉｍｉｄｅ）を用いて上チップ２ １の下表面をリード２３の搭載部２３１に粘着させる。上チップ２１の上表面に は複数のはんだパッド（ｂｏｎｄｉｎｇ ｐａｄ）と集積回路素子（ｉｎｔｅｇ ｒａｔｅｄ ｃｉｒｃｕｉｔ ｅｌｅｍｅｎｔ）を持つ。上チップ１１０はDRAM 、SRAMとフラッシュ（ｆｌａｓｈ）などのメモリチップ、マイクロプロセサ或い はロジック性（ｌｏｇｉｃ）機能のチップとして使用されている。他に、上チッ プ２１とリードフレームとを電気的に連結することに関しては、複数の金材や銅 材の導電ワイヤ２６（ｂｏｎｄｉｎｇ ｗｉｒｅ）を用いてワイヤーボンディン グ方法で上チップ２１のはんだパッドとリードフレームに対応するリード２３の インナーリード部２３２とを連結する。The upper chip 21 is fixed on the mounting portion 231 of the lead 23, and the lower surface of the upper chip 21 is mounted on the lead 23 using one insulating first tape 24 (polyimide). Attach to the part 231. The upper surface of the upper chip 21 has a plurality of bonding pads and integrated circuit elements. The upper chip 110 is used as a memory chip such as a DRAM, an SRAM and a flash, a microprocessor or a chip having a logic function. In addition, regarding the electrical connection between the upper chip 21 and the lead frame, soldering of the upper chip 21 by a wire bonding method using a plurality of conductive wires 26 of gold or copper is used. The pad and the inner lead portion 232 of the lead 23 corresponding to the lead frame are connected.
【００１０】 下チップ２２は上チップ２１と同じ或いは別な機能を持つチップであり、上記 リード２３の搭載部２３１下方に固着されて、絶縁性第二テープ２５（ポリイミ ド材質）を用いて下チップ２２の上表面をリード２３の搭載部２３１に粘着され ている。下チップ２２の下表面には所定数のはんだパッドと集積回路素子を有し 、複数の導電ワイヤ２６を用いてワイヤーボンディング方法で下チップ２２のは んだパッドとリードフレームに対応するリード２３のインナーリード部２３２と を連結する。そしてダブルサイドチップパッケージ２０に含まれているパッケー ジ胴体２７（ｐａｃｋａｇｅ ｂｏｄｙ）によりこれらの上チップ２１、下チッ プ２２、第一テープ２４、第二テープ２５、導電ワイヤ２６とリードフレームの リード２３の搭載部２３１およびインナーリード部２３２を封止されている。但 しリード２３のアウトリード部２３３はパッケージ胴体２７より露出され、従っ て上記の２つのチップ組立構造は保護することが可能である。The lower chip 22 is a chip having the same or another function as the upper chip 21, and is fixed below the mounting portion 231 of the lead 23, and is formed by using an insulating second tape 25 (polyimide material). The upper surface of the chip 22 is adhered to the mounting portion 231 of the lead 23. A predetermined number of solder pads and integrated circuit elements are provided on the lower surface of the lower chip 22. Solder pads of the lower chip 22 and leads 23 corresponding to a lead frame are formed by a wire bonding method using a plurality of conductive wires 26. The inner lead portion 232 and are connected. The upper body 21, the lower chip 22, the first tape 24, the second tape 25, the conductive wires 26, and the leads 23 of the lead frame are formed by a package body 27 included in the double side chip package 20. The mounting portion 231 and the inner lead portion 232 are sealed. However, the out-lead portion 233 of the lead 23 is exposed from the package body 27, so that the above-mentioned two chip assembly structures can be protected.
【００１１】 本考案の実施例によるダブルサイドチップパッケージ２０は、２つのチップを 封止可能で、且つ小さい折曲変形（熱膨張による上下位置が変わらないこと）と 応力（リードの搭載部は細長く応力を吸収できること）、良い保護性(上下両チ ップはパッケージ胴体中に封止されること)とリード固着性(上下両チップはリー ドを挟めること)およびモールディングフロウバランス（ｍｏｌｄｉｎｇ ｆｌ ｏｗ ｂａｌａｎｃｅ）等の機能を備える。The double-sided chip package 20 according to the embodiment of the present invention can seal two chips and has small bending deformation (the vertical position does not change due to thermal expansion) and stress (the mounting portion of the lead is elongated). Stress can be absorbed), good protection (both upper and lower chips must be sealed in the package body), lead fixation (both upper and lower chips must have leads), and molding flow balance (moulding flow balance) ).
【００１２】 図４、図５に示すように本考案の第二実施例によるダブルサイドチップパッケ ージ３０は主にＬＯＣ形リードフレーム、上チップ３１、下チップ３２とパッケ ージ胴体３７を含む。上チップ３１、下チップ３２、およびパッケージ胴体３７ は第一具体例の上チップ２１、下チップ２２およびパッケージ胴体２７とそれぞ れ同様である。As shown in FIGS. 4 and 5, a double side chip package 30 according to a second embodiment of the present invention mainly includes a LOC type lead frame, an upper chip 31, a lower chip 32, and a package body 37. . The upper chip 31, the lower chip 32, and the package body 37 are the same as the upper chip 21, the lower chip 22, and the package body 27 of the first specific example, respectively.
【００１３】 図５に示すように、ＬＯＣ形リードフレームは、別のリードオンチップ（Ｌｅ ａｄ Ｏｎ Ｃｈｉｐ）形リードフレームであり、複数のリード３３と２つの電 源リード３５を有する。リード３３は上チップ３１と下チップ３２の信号を伝達 するために使用され、内より外へ搭載部３３１、インナーリード部３３２とアウ トリード部３３３に分けられる。中に搭載部３３１は上チップ３１と下チップ３ ２との間に位置し、チップ３１、チップ３２を搭載する役目になる。インナーリ ード部３３２は枠形のワイヤーボンディング区３８内に配置され、導電ワイヤ３ ６と連結するリード３３の接続所である。アウトリード部３３３は樹脂封止区３ ９の外に配置され、ダブルサイドチップパッケージ３０の電気的な外接端子とし て使用される。電源リード３５はバスバーと言われ、ハンドル状の形で、樹脂封 止区３９の内の搭載部３５１と両外側へ延びるインナーリード部３５２とに分け られる。電源リード３５の搭載部３５１はリード３３の搭載部３３１の間に、搭 載部331と垂直に配置され、上チップ３１および下チップ３２を搭載することに 使用される。インナーリード部３５２は枠形のワイヤーボンディング区３８内に 配置され、導電ワイヤ３６と連結する電源リード３５の接続所であり、上チップ ２１および下チップ２２の電源を輸送する。上記のＬＯＣ形リードフレームのリ ード３３、リード３５は両チップの間に配置されているので、リード３３が同時 に上チップ３１および下チップ３２を搭載し、且つチツプ３１、チップ３２に挟 まれるのて゛良好な固着性を得ることが可能である。従って図４のように、各リ ード３３の搭載部３３１とインナーリード部３３２は同一平面に形成され、折曲 げなくても良い固着性を得ることが可能となる。搭載部３３１とインナーリード 部３３２は上チップ３１と下チップ３２との間の所定幅平面Ｐ１に形成されてリ ード３３を折曲げなくてもモールディングフロウバランスの機能を持つことが可 能である。As shown in FIG. 5, the LOC type lead frame is another lead-on-chip (Lead On Chip) type lead frame, and has a plurality of leads 33 and two power supply leads 35. The leads 33 are used to transmit signals of the upper chip 31 and the lower chip 32, and are divided into a mounting portion 331, an inner lead portion 332, and an outer lead portion 333 from inside to outside. The mounting portion 331 is located between the upper chip 31 and the lower chip 32 and serves to mount the chips 31 and 32. The inner lead portion 332 is arranged in the frame-shaped wire bonding section 38 and is a connection point of the lead 33 connected to the conductive wire 36. The outlead portion 333 is disposed outside the resin sealing section 39 and is used as an electrical external terminal of the double side chip package 30. The power supply lead 35 is called a bus bar, and has a handle shape, and is divided into a mounting portion 351 in the resin sealing section 39 and an inner lead portion 352 extending to both outer sides. The mounting portion 351 of the power supply lead 35 is disposed between the mounting portion 331 of the lead 33 and perpendicular to the mounting portion 331, and is used for mounting the upper chip 31 and the lower chip 32. The inner lead portion 352 is disposed in the frame-shaped wire bonding section 38, is a connection point of the power supply lead 35 connected to the conductive wire 36, and transports power of the upper chip 21 and the lower chip 22. Since the leads 33 and 35 of the LOC type lead frame are arranged between both chips, the leads 33 simultaneously mount the upper chip 31 and the lower chip 32 and sandwich the chips between the chips 31 and 32. It is possible to obtain good fixability. Therefore, as shown in FIG. 4, the mounting portion 331 of each lead 33 and the inner lead portion 332 are formed on the same plane, and it is possible to obtain a fixing property that does not require bending. The mounting portion 331 and the inner lead portion 332 are formed on a plane P1 having a predetermined width between the upper chip 31 and the lower chip 32, and can have a function of molding flow balance without bending the lead 33. is there.
【００１４】 本実施例において、ダブルサイドチップパッケージ３０は他に熱硬化性（ｔｈ ｅｒｍｏｓｅｔｔｉｎｇ）および絶縁性を持つエポキシ合成物３４（ｅｐｏｘｙ ｃｏｍｐｏｕｎｄ）を含む。このエポキシ合成物３４は液体の時に上チップ３ １と下チップ３２間に塗布され、焼いた後、同時に上チップ３１、下チップ３２ とリードフレームのリード３３、リード３５が固定され、導電ワイヤ３６により ワイヤーボンディングされ、パッケージ胴体３７をモールドして硬化した後、小 さい折曲変形と応力、良好な保護性と固着性およびモールディングフロウバラン ス等の多重機能を持つダブルサイドチップパッケージ３０を得ることができる。 本考案の保護範囲は後付の実用新案登録請求の範囲で限定されて、この保護範 囲に基準して、この技術をよく知っている誰でも、本創作の精神と範囲内に触れ るどんな変更や修正は本創作の保護範囲に属する。In this embodiment, the double-sided chip package 30 further includes an epoxy compound 34 having thermosetting and insulating properties. The epoxy compound 34 is applied between the upper chip 31 and the lower chip 32 when it is in a liquid state, and after baking, the upper chip 31, the lower chip 32 and the leads 33 and 35 of the lead frame are simultaneously fixed, and the conductive wires 36 After the package body 37 is molded and cured by hardening, a double side chip package 30 having multiple functions such as small bending deformation and stress, good protection and adhesion, and molding flow balance is obtained. Can be. The scope of protection of the present invention is limited by the claims for registration of a utility model registered later, and based on this scope of protection, anyone familiar with this technology should be aware of any matter within the spirit and scope of the invention. Changes and modifications are within the scope of protection of this work.
【００１５】[0015]
ＬＯＣ形リードフレームを基準平面として利用してリードフレームのリード内 面の上下にそれぞれチップを固定することより、リードを折れ曲げなくてもモー ルディングフロウバランス（ｍｏｌｄｉｎｇ ｆｌｏｗ ｂａｌａｎｃｅ）の効 果を得ることが可能となり、且つリードフレームのリードは上下チップに挟めら れるので良好な固着性を持つ。他には、上下両チツプを使うのでこのダブルサイ ドチップパッケージは記憶容量を倍にすること、最小の変形、小さい応力、と良 い保護性などのメリットかある。 By using the LOC type lead frame as a reference plane and fixing the chips above and below the inner surface of the lead of the lead frame, it is possible to obtain the effect of molding flow balance without bending the lead. And the lead of the lead frame is sandwiched between the upper and lower chips, so that it has good fixation. In addition, since both upper and lower chips are used, this double-sided chip package has the advantages of doubling the storage capacity, minimal deformation, low stress, and good protection.
【図１】米国特許NO．６，１１８，１７６のダブルチッ
プパッケージを示す断面図である。FIG. It is sectional drawing which shows 6,118,176 double chip packages.
【図２】本考案の第一実施例によるダブルサイドチップ
パッケージを示す断面図である。FIG. 2 is a sectional view showing a double side chip package according to a first embodiment of the present invention;
【図３】図２の３−３線により切断された断面を示す図
である。FIG. 3 is a view showing a cross section taken along line 3-3 in FIG. 2;
【図４】本考案の第二実施例によるダブルサイドチップ
パッケージを示す断面図である。FIG. 4 is a sectional view showing a double side chip package according to a second embodiment of the present invention.
【図５】図４の５−５線により切断された断面を示す図
である。FIG. 5 is a view showing a cross section taken along line 5-5 in FIG. 4;
２０ ダブルサイドチップパッケージ ２１ 上チップ ２２ 下チップ ２３ リード ２４ 上テープ ２５ 下テープ ２６ 導電ワイヤ ２７ パッケージ胴体 ２８ ワイヤーボンディング区 ２９ 樹脂封止区 ３０ ダブルサイドチップパッケージ ３１ 上チップ ３２ 下チップ ３３ 信号伝達用リード ３４ エポキシ合成物 ３５ 電源用リード ３６ 導電ワイヤ ３７ パッケージ胴体 ３８ ワイヤーボンディング区 ２３１ 搭載部 ２３２ インナーリード部 ２３３ アウトリード部 Reference Signs List 20 double side chip package 21 upper chip 22 lower chip 23 lead 24 upper tape 25 lower tape 26 conductive wire 27 package body 28 wire bonding section 29 resin sealing section 30 double side chip package 31 upper chip 32 lower chip 33 signal transmission lead 34 epoxy composite 35 power supply lead 36 conductive wire 37 package body 38 wire bonding section 231 mounting section 232 inner lead section 233 out lead section
Claims (6)
下チップ、所定数の導電ワイヤおよびパッケージ胴体を
含み、 前記リードフレームは所定数のリードを有し、前記リー
ドは内から外へ搭載部、インナーリード部およびアウト
リード部に分けられ、 前記上チップの下表面を前記リードフレームの前記搭載
部の上方に固着させるため、前記上チップの上表面は所
定数のはんだパッドを有し、 前記下チップの上表面を前記リードフレームの前記搭載
部の下方に固着させるため、前記下チップの下表面は所
定数のはんだパッドを有し、 前記導電ワイヤは、前記上チップのはんだパッドならび
に前記上チップのはんだパッドに対応する前記インナー
リード部と、前記下チップのはんだパッドならびに前記
下チップのはんだパッドに対応する前記インナーリード
部と、それぞれ電気的に連結され、 前記パッケージ胴体により前記上チップ、前記下チッ
プ、前記導電ワイヤ、前記リードフレ―ムの前記搭載部
ならびに前記インナーリード部は封止されていることを
特徴とするダブルサイドチップパッケージ。1. A LOC-type lead frame, an upper chip,
A lower chip, a predetermined number of conductive wires and a package body, wherein the lead frame has a predetermined number of leads, and the leads are divided into a mounting part, an inner lead part, and an out lead part from inside to outside; The upper surface of the upper chip has a predetermined number of solder pads so that the lower surface of the lower chip is fixed above the mounting portion of the lead frame, and the upper surface of the lower chip is positioned below the mounting portion of the lead frame. The lower surface of the lower chip has a predetermined number of solder pads, and the conductive wires are connected to the solder pads of the upper chip and the inner leads corresponding to the solder pads of the upper chip. The chip solder pads and the inner lead portions corresponding to the solder pads of the lower chip are electrically connected to each other, The upper chip by a package body, the lower tip, the conductive wire, the Ridofure - Double-sided chip package the mounting portion and the inner lead portion of the arm are characterized by being sealed.
搭載部に固着させるためにテープを備えていることを特
徴とする請求項１記載のダブルサイドチップパッケー
ジ。2. The double side chip package according to claim 1, further comprising a tape for fixing the upper chip and the lower chip to the mounting portion.
搭載部に固着させるためにエポキシ合成物を備えること
を特徴とする請求項１記載のダブルサイドチップパッケ
ージ。3. The double side chip package according to claim 1, further comprising an epoxy compound for fixing the upper chip and the lower chip to the mounting portion.
同一平面に形成されていることを特徴とする請求項１記
載のダブルサイドチップパッケージ。4. The double side chip package according to claim 1, wherein said mounting portion and said inner lead portion are formed on the same plane.
は前記上チップと前記下チップとの間の所定幅平面に形
成されていることを特徴とする請求項４記載のダブルサ
イドチップパッケージ。5. The double side chip package according to claim 4, wherein said mounting portion and said inner lead portion are formed on a plane having a predetermined width between said upper chip and said lower chip.
１つの電源リードが設けられ、 前記電源リードは搭載部を有し、前記電源リードの搭載
部は前記上チップと前記下チップとの間に、前記リード
の搭載部と垂直になるように配置されていることを特徴
とする請求項１記載のダブルサイドチップパッケージ。6. The lead frame further includes at least one other power supply lead, the power supply lead has a mounting portion, and the mounting portion of the power supply lead is provided between the upper chip and the lower chip. 2. The double side chip package according to claim 1, wherein the double side chip package is arranged so as to be perpendicular to a mounting portion of the lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001003678U JP3082507U (en) | 2001-06-07 | 2001-06-07 | Double side chip package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001003678U JP3082507U (en) | 2001-06-07 | 2001-06-07 | Double side chip package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP3082507U true JP3082507U (en) | 2001-12-14 |
Family
ID=43215212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001003678U Expired - Lifetime JP3082507U (en) | 2001-06-07 | 2001-06-07 | Double side chip package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3082507U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0672284U (en) * | 1993-03-19 | 1994-10-07 | 沖電気工業株式会社 | Waterproof gasket |
| US10199300B2 (en) | 2007-10-16 | 2019-02-05 | Toshiba Memory Corporation | Semiconductor package including a device and lead frame used for the same |
-
2001
- 2001-06-07 JP JP2001003678U patent/JP3082507U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0672284U (en) * | 1993-03-19 | 1994-10-07 | 沖電気工業株式会社 | Waterproof gasket |
| US10199300B2 (en) | 2007-10-16 | 2019-02-05 | Toshiba Memory Corporation | Semiconductor package including a device and lead frame used for the same |
| US10777479B2 (en) | 2007-10-16 | 2020-09-15 | Toshiba Memory Corporation | Semiconductor memory device |
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