JPH0214558A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0214558A JPH0214558A JP63165638A JP16563888A JPH0214558A JP H0214558 A JPH0214558 A JP H0214558A JP 63165638 A JP63165638 A JP 63165638A JP 16563888 A JP16563888 A JP 16563888A JP H0214558 A JPH0214558 A JP H0214558A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- integrated circuit
- semiconductor integrated
- free end
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 238000005476 soldering Methods 0.000 abstract description 12
- 238000007789 sealing Methods 0.000 abstract description 7
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000007747 plating Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 230000005499 meniscus Effects 0.000 description 3
- 238000009736 wetting Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、プリント基板に表面実装される半導体集積回
路装置に関し、さらに詳しくは、その外部リードの形状
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device that is surface-mounted on a printed circuit board, and more particularly to the shape of its external leads.
［従来の技術］
第３図は、従来例のフラットバック形の半導体集積回路
装置１０の斜視図であり、同図において、２ｏは外部リ
ード、２゜ｂは外部リード２゜の先端の切断面、３は封
止樹脂である。[Prior Art] FIG. 3 is a perspective view of a conventional flat-back type semiconductor integrated circuit device 10, in which 2o is an external lead and 2°b is a cut surface of the tip of the external lead 2°. , 3 is a sealing resin.
このような半導体集積回路装置１゜は、一般に、次のよ
うな手順で製造される。Such a semiconductor integrated circuit device 1° is generally manufactured by the following procedure.
すなわち、先ず、シリコン結晶上に回路が構成されてな
る半導体集積回路チップを、リードフレームのチップ載
置部に接着し、その後、チップ上の電極と、リードフレ
ームの内部電極とを金属細線で接続し、それを封止用樹
脂によって成形する。That is, first, a semiconductor integrated circuit chip with a circuit configured on a silicon crystal is adhered to the chip mounting part of a lead frame, and then the electrodes on the chip and the internal electrodes of the lead frame are connected with thin metal wires. Then, it is molded with a sealing resin.
この後、プリント基板への半田付性を向上させるために
、樹脂封止後のリードフレーム上に、半田メツキを施し
、さらに、外部リードを成形するための加工、すなわち
、各集積回路装置に対応するようにリードフレームを切
断し、このリードフレームを所定の寸法に折曲して第３
図のような外部リード２゜を形成する。After this, in order to improve solderability to the printed circuit board, solder plating is applied to the resin-sealed lead frame, and further processing to form external leads, that is, compatible with each integrated circuit device. Cut the lead frame so that the
Form external leads 2° as shown in the figure.
このような手順によって製造されるので、リードフレー
ムの切断面、すなわち、外部リード２゜の先端の切断面
２゜ｂには、半田メツキが施されていないことになる。Since the lead frame is manufactured by such a procedure, solder plating is not applied to the cut surface of the lead frame, that is, the cut surface 2°b at the tip of the external lead 2°.
第４図は、この第３図の半導体集積回路装置ＩＯをプリ
ント基板５に半田によって実装した状態を示す斜視図で
ある。半導体集積回路装置１゜の外部リード２゜が、プ
リント基板５の導体パターンのマウントパッド６に半田
によって取り付けられる。FIG. 4 is a perspective view showing the semiconductor integrated circuit device IO of FIG. 3 mounted on the printed circuit board 5 by soldering. External leads 2° of a semiconductor integrated circuit device 1° are attached to mounting pads 6 of a conductor pattern on a printed circuit board 5 by soldering.
［発明が解決しようとする課題］
第５図は、第４図における外部リード部分の一部拡大断
面図であり、同図において、４は外部リード２゜に施さ
れた半田メツキ、７は半田である。[Problems to be Solved by the Invention] FIG. 5 is a partially enlarged sectional view of the external lead portion in FIG. It is.
半導体集積回路装置ｌ。の外部リード２゜の先端の切断
面２゜ｂには、上述のように半田メツキ４が施されてい
ないために、第５図に示されるように、先端においては
、充分なメニスカス、いわゆる半田の濡れが形成されず
、半田付強度が充分に確保できないという問題がある。Semiconductor integrated circuit device l. Since the cut surface 2°b of the tip of the external lead 2° is not solder plated 4 as described above, there is a sufficient meniscus, so-called solder, at the tip, as shown in FIG. There is a problem that wetting is not formed and sufficient soldering strength cannot be ensured.
本発明は、上述の点に鑑みてなされたものであって、外
部リードの先端においても、充分な半田付強度を得られ
るようにすることを目的とする。The present invention has been made in view of the above points, and it is an object of the present invention to make it possible to obtain sufficient soldering strength even at the tips of external leads.
［課題を解決するための手段］
本発明では、上述の目的を達成するために、プリント基
板の導体パターンに、外部リードが半田によって平面付
けされて前記プリント基板に実装される半導体集積回路
装置において、前記外部リードの遊端部が、前記プリン
ト基板への実装状態における前記プリント基板から離反
する方向に湾曲されている。[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a semiconductor integrated circuit device in which external leads are flattened to a conductor pattern of a printed circuit board by solder and mounted on the printed circuit board. , the free end portion of the external lead is curved in a direction away from the printed circuit board when it is mounted on the printed circuit board.
［作用コ
上記構成によれば、外部リードの遊端部、すなわち、切
断面を含む先端部がプリント基板から離反する方向に湾
曲されるので、外部リードの遊端部の半田メツキが施さ
れている部分で充分なメニスカス、いわゆる半田濡れが
得られ、半田付強度が確保されることになる。[Operation] According to the above configuration, the free ends of the external leads, that is, the tips including the cut surfaces, are bent in the direction away from the printed circuit board, so the free ends of the external leads are not soldered. Sufficient meniscus, so-called solder wetting, is obtained in the area where the solder is applied, and soldering strength is ensured.
［実施例］
以下、図面によって本発明の実施例について、詳細に説
明する。[Examples] Examples of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明の一実施例の半導体集積回路装置の斜
視図であり、第３図の従来例に対応する部分には、同一
の参照符を付す。FIG. 1 is a perspective view of a semiconductor integrated circuit device according to an embodiment of the present invention, and parts corresponding to the conventional example in FIG. 3 are given the same reference numerals.
この実施例の半導体集積回路装置１は、いわゆる、フラ
ットパック形であり、後述のように、プリント基板の導
体パターンに、外部リード２が半田によって平面付けさ
れて実装される。The semiconductor integrated circuit device 1 of this embodiment is of a so-called flat pack type, and as will be described later, external leads 2 are mounted on a conductor pattern of a printed circuit board by being flattened with solder.
この半導体集積回路装置ｌでは、封止樹脂３から延出す
る複数の外部リード２の遊端部２ａにおいて、充分な半
田付強度を得ることができるように、次のようにしてい
る。In this semiconductor integrated circuit device 1, the following steps are taken to obtain sufficient soldering strength at the free ends 2a of the plurality of external leads 2 extending from the sealing resin 3.
すなわち、外部リード２の遊端部２ａが、プリント基板
への実装状態における前記プリント基板から離反する方
向、すなわち、パッケージの上面方向に湾曲されている
。That is, the free end portion 2a of the external lead 2 is curved in a direction away from the printed circuit board when it is mounted on the printed circuit board, that is, toward the top surface of the package.
この半導体集積回路装置ｌは、基本的に従来と同様の手
順で製造される。This semiconductor integrated circuit device 1 is basically manufactured using the same procedure as the conventional method.
すなわち、先ず、シリコン結晶上に回路が構成されてな
る半導体集積回路チップを、リードフレームのチップ載
置部に接着し、その後、チップ上の電極と、リードフレ
ームの内部電極とを金属細線で接続し、それを封止用樹
脂によって成形する。That is, first, a semiconductor integrated circuit chip with a circuit configured on a silicon crystal is adhered to the chip mounting part of a lead frame, and then the electrodes on the chip and the internal electrodes of the lead frame are connected with thin metal wires. Then, it is molded with a sealing resin.
この後、プリント基板への半田付性を向上させるために
、樹脂封止後のリードフレーム上に、半田メツキを施し
、さらに、外部リードを成形するための加工、すなわち
、各集積回路装置に対応するようにリードフレームを切
断し、このリードフレームを所定の寸法に折曲して第３
図の従来例と同様の外部リードとし、さらに、その遊端
部２ａを上方に湾曲させることにより本発明の半導体集
積回路装置ｌを得るものである。After this, in order to improve solderability to the printed circuit board, solder plating is applied to the resin-sealed lead frame, and further processing to form external leads, that is, compatible with each integrated circuit device. Cut the lead frame so that the
The semiconductor integrated circuit device 1 of the present invention is obtained by using the same external lead as in the conventional example shown in the figure and further curving the free end portion 2a upward.
このような手順によって製造されるので、従来と同様に
、外部リードの遊端部２ａの切断面２ｂには、半田メツ
キが施されていないことになる。Since the device is manufactured by such a procedure, solder plating is not applied to the cut surface 2b of the free end portion 2a of the external lead, as in the conventional case.
第２図は、この第１図の半導体集積回路装置ｌをプリン
ト基板に半田によって実装した状態を示す一部拡大断面
図であり、第５図の従来例に対応する図である。FIG. 2 is a partially enlarged sectional view showing the semiconductor integrated circuit device l of FIG. 1 mounted on a printed circuit board by soldering, and corresponds to the conventional example of FIG. 5.
同図において、４は外部リード２に上述のようにして施
された半田メツキ、５はプリント基板、６はマウントパ
ッド、７は半田である。In the figure, 4 is the solder plating applied to the external lead 2 as described above, 5 is a printed circuit board, 6 is a mounting pad, and 7 is solder.
この第２図に示されるように、外部リード２の遊端部２
ａをプリント基板５から離反する方向、すなわち、第２
図の上方へ湾曲させているので、遊端部２ａの半田メツ
キが施された部分４ａとプリント基板５のマウントパッ
ド６との間に、充分なメニスカスが得られることになり
、半田付強度を従来例に比べて高めることが可能となる
。As shown in FIG. 2, the free end 2 of the external lead 2
a in the direction away from the printed circuit board 5, that is, the second
Since it is curved upward in the figure, a sufficient meniscus is obtained between the solder-plated portion 4a of the free end 2a and the mounting pad 6 of the printed circuit board 5, which increases the soldering strength. It is possible to increase this compared to the conventional example.
［発明の効果コ
以上のように本発明によれば、外部リードの遊端部が、
プリント基板への実装状態における前記プリント基板か
ら離反する方向に湾曲されているので、外部リードの遊
端部の半田メツキが施されている部分で半田付けが行わ
れることになり、従来例に比べて半田付強度が向上する
。[Effects of the Invention] As described above, according to the present invention, the free end of the external lead is
Since it is curved in the direction away from the printed circuit board when mounted on the printed circuit board, soldering is performed at the solder-plated part of the free end of the external lead, compared to the conventional example. This improves soldering strength.
第１図は本発明の一実施例の斜視図、第２図は第１図の
半導体集積回路装置をプリント基板に実装した状態を示
す一部拡大断面図、第３図は従来例の斜視図、第４図は
第３図の従来例をプリント基板に実装した状態を示す斜
視図、第５図は第４図の一部拡大断面図である。
１．１゜・・・半導体集積回路装置、
２．２゜・・・外部リード、
２ａ、・・・遊端部
・・封止樹脂。FIG. 1 is a perspective view of an embodiment of the present invention, FIG. 2 is a partially enlarged sectional view showing the semiconductor integrated circuit device of FIG. 1 mounted on a printed circuit board, and FIG. 3 is a perspective view of a conventional example. 4 is a perspective view showing the conventional example shown in FIG. 3 mounted on a printed circuit board, and FIG. 5 is a partially enlarged sectional view of FIG. 4. 1.1°...Semiconductor integrated circuit device, 2.2°...External lead, 2a,...Free end...Sealing resin.
Claims (1)
田によって平面付けされて前記プリント１板に実装され
る半導体集積回路装置において、前記外部リードの遊端
部が、前記プリント基板への実装状態における前記プリ
ント基板から離反する方向に湾曲されてなる半導体集積
回路装置。(1) In a semiconductor integrated circuit device in which external leads are plane-bonded to a conductive pattern of a printed circuit board by solder and mounted on the printed circuit board, the free ends of the external leads are in a state of being mounted on the printed circuit board. A semiconductor integrated circuit device that is curved in a direction away from the printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63165638A JPH0214558A (en) | 1988-06-30 | 1988-06-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63165638A JPH0214558A (en) | 1988-06-30 | 1988-06-30 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214558A true JPH0214558A (en) | 1990-01-18 |
Family
ID=15816163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63165638A Pending JPH0214558A (en) | 1988-06-30 | 1988-06-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214558A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0518043U (en) * | 1991-08-09 | 1993-03-05 | ケル株式会社 | Lead for surface mount electronic components |
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
| JP2017118137A (en) * | 2014-09-11 | 2017-06-29 | 日本精工株式会社 | Multipolar lead component and connection device of substrate |
-
1988
- 1988-06-30 JP JP63165638A patent/JPH0214558A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0518043U (en) * | 1991-08-09 | 1993-03-05 | ケル株式会社 | Lead for surface mount electronic components |
| US6114759A (en) * | 1998-04-23 | 2000-09-05 | Nec Corporation | Semiconductor package |
| JP2017118137A (en) * | 2014-09-11 | 2017-06-29 | 日本精工株式会社 | Multipolar lead component and connection device of substrate |
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