KR200153438Y1 - Chip scale package using a tab tape - Google Patents
Chip scale package using a tab tape Download PDFInfo
- Publication number
- KR200153438Y1 KR200153438Y1 KR2019950053223U KR19950053223U KR200153438Y1 KR 200153438 Y1 KR200153438 Y1 KR 200153438Y1 KR 2019950053223 U KR2019950053223 U KR 2019950053223U KR 19950053223 U KR19950053223 U KR 19950053223U KR 200153438 Y1 KR200153438 Y1 KR 200153438Y1
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- South Korea
- Prior art keywords
- chip
- lead
- inner lead
- tape
- scale package
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Abstract
본 고안은 업셋된 내부리드가 패턴화된 탭테이프와, 내부리드의 범프 본딩되는 칩과, 내부리드와 칩의 본딩 주위를 실링하는 실링수지로 이루어지며, 내부리드와 연결된 외부리드가 바닥면에 수평으로 노출된 것을 특징으로 하는 탭테이프를 이용한 칩스케일 패키지이며, 탭테이프 기술을 칩스테일 패키지 기술에 접목시켰기에 제조공수가 줄어들고, 탭테이프의 외부리드가 저면에 수평을 이루도록 노출되어 기판과 표면실장을 가능케 한다.The present invention consists of a tab tape patterned with an inner lead with an upset, a chip bonded with bumps of the inner lead, and a sealing resin sealing around the bonding between the inner lead and the chip, and an outer lead connected to the inner lead on the bottom surface. Chip scale package using the tap tape, which is horizontally exposed, and manufacturing process is reduced because the tap tape technology is combined with the chip tail package technology, and the outer lead of the tap tape is exposed to be horizontal to the bottom to expose the substrate and the surface mount. Makes it possible.
Description
제1도는 본 고안에 사용되는 칩의 개략도.1 is a schematic view of a chip used in the present invention.
제2(a)도는 본 고안을 제조하기 위해 칩을 정렬시킨 상태의 단면도.Figure 2 (a) is a cross-sectional view of the state in which the chip is aligned to manufacture the present invention.
제2(b)도는 본 고안을 제조하기 위해 칩을 정렬시킨 상태의 평면도.Figure 2 (b) is a plan view of the state in which the chip is aligned to manufacture the present invention.
제3도는 본 고안의 칩본딩 공정도.3 is a chip bonding process of the present invention.
제4(a)도는 본 고안의 칩본딩후 실링한 상태의 단면도.Figure 4 (a) is a cross-sectional view of the sealed state after chip bonding of the present invention.
제4(b)도는 본 고안의 칩본딩후 실링한 상태의 평면도.Figure 4 (b) is a plan view of the sealed state after chip bonding of the present invention.
제5(a)도는 본 고안의 칩본딩후 트리밍을 보여주는 단면도.Figure 5 (a) is a cross-sectional view showing the trimming after chip bonding of the present invention.
제5(b)도는 본 고안의 칩본딩후 트리밍을 보여주는 평면도.Figure 5 (b) is a plan view showing the trimming after chip bonding of the present invention.
제6(a)도는 본 고안의 트리밍후 단위 유니트로 절단전의 부분 평면도.Figure 6 (a) is a partial plan view before cutting into a unit unit after trimming of the present invention.
제6(b)도는 본 고안의 트리밍후 단위 유니트로 절단한 상태의 단면도.Figure 6 (b) is a cross-sectional view of the cut state in the unit unit after trimming of the present invention.
제6(c)도는 본 고안의 트리밍후 단위 유니트로 절단한 상태의 부분평면도.Figure 6 (c) is a partial plan view of a state cut in the unit unit after trimming of the present invention.
제7도는 본 고안의 패키지를 사용하는 상태를 보인 단면도이다.7 is a cross-sectional view showing a state using the package of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 내부리드 2 : 탭테이프1: Internal lead 2: Tap tape
3 : 칩 4 : 실링수지3: chip 4: sealing resin
5 : 외부리드5: External lead
본 고안은 탭테이프를 이용한 칩스케일 패키지에 관한 것으로, 탭테이프의 금속패턴을 리드프레임으로 사용하여 탭본딩하고 본딩부위를 실링시킨 다음 단위유니트로 절단하여 수득되는 구조의 칩스케일 패키지에 관한 것이다.The present invention relates to a chip scale package using a tap tape. The present invention relates to a chip scale package having a structure obtained by tap bonding using a metal pattern of a tap tape as a lead frame, sealing the bonding portion, and cutting the unit unit.
일반적으로 칩스케일 패키지는 완성된 패키지의 크기가 칩사이즈와 동일하거나 칩사이즈보다 최대 1㎜정도 큰 패키지를 칩스케일 패키지(Chip Scale Package)라 분류한다.In general, a chip scale package is classified as a chip scale package as a package having a size equal to the chip size or a maximum size of about 1 mm.
이러한 칩스케일 패키지는 리드프레임에 칩온리드 형태로 칩을 어태치 시켜 칩표면이 외부로 노출되도록 몰딩시켜 수득하는 것으로 다량생산에 문제가 있다. 또한 탭테이프를 상요하여 패키지를 제조하는 기술도 개발되었는바, 테이프에 리드프레임과 같은 패턴을 형성시켜 패턴 대응부위에 칩을 어태치시키고, 테이프패턴을 통하여 별도의 리드 연결부에서 외부리드역할을 하도록 이루어진다. 그러나 이때의 탭테이프는 리드프레임 자체가 잔류하여 칩어태치 부위와는 다른위치에서 별도의 외부단자를 통하여 전기적으로 연결사용하는 구조이므로 이의 구현에 따른 별도의 공정이 필요하고, 외부단자가 필요하기에 그 자체를 표면실장용 디바이스로 사용할수 없는 단점이 있다.Such a chip scale package is obtained by molding the chip surface to be exposed to the outside by attaching the chip to the lead frame in the form of a chip on lead, which causes a problem in mass production. In addition, a technology for manufacturing a package using tap tape has been developed.A pattern such as a lead frame is formed on a tape to attach a chip to a pattern corresponding part, and an external lead role is performed at a separate lead connection part through a tape pattern. Is done. However, the tap tape at this time has a structure in which the lead frame itself remains and is electrically connected and used through a separate external terminal at a different position from the chip attach region, so a separate process is required according to the implementation thereof, and an external terminal is required. There is a disadvantage that can not be used as a surface mounting device itself.
본 고안은 이를 해결코자 하는것으로, 탭테이프에 칩을 본딩시키고, 탭테이프의 외부리드가 실링수지 바닥면에 노출되도록 하여 표면실장을 가능케함을 특징으로 한다.The present invention is to solve this problem, by bonding the chip to the tab tape, it is characterized in that the outer lead of the tap tape is exposed to the sealing resin bottom surface to enable the surface mounting.
즉, 본 고안은 업셋된 내부리드가 패턴화된 탭테이프와, 내부리드와 범프본딩되는 칩과, 내부리드와 칩의 본딩부위를 실링하는 실링수지로 이루어지며, 내부리드와 연결된 외부리드가 바닥을 향해 노출되도록 수평하게 성형되어 있는 것을 특징으로 하는 탭테이프를 이용한 칩스케일 패키지를 제공하려는 것이다.That is, the present invention consists of a tab tape patterned with an inner lead with an upset, a chip bonded with an inner lead and a bump bonding, and a sealing resin sealing the bonding portion between the inner lead and the chip, and the outer lead connected to the inner lead is bottomed. It is to provide a chip-scale package using a tab tape characterized in that it is formed horizontally to be exposed toward.
이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.
즉, 본 고안은 업셋된 내부리드가 패턴화된 탭테이프와, 내부리드와 범프본딩되는 칩과, 내부리드와 칩의 본딩부위를 실링하는 실링수지로 이루어지며, 내부리드와 연결된 외부리드가 바닥을 향해 노출되도록 수평하게 성형되어 있는 것을 특징으로 하는 탭테이프를 이용한 칩스케일 패키지를 제공하려는 것이다.That is, the present invention consists of a tab tape patterned with an inner lead with an upset, a chip bonded with an inner lead and a bump bonding, and a sealing resin sealing the bonding portion between the inner lead and the chip, and the outer lead connected to the inner lead is bottomed. It is to provide a chip-scale package using a tab tape characterized in that it is formed horizontally to be exposed toward.
이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.
업셋된 내부리드(1)가 패턴화된 탭테이프(2)와, 내부리드(1)와 범프 본딩되는 칩(3)과, 내부리드(1)와 칩(3)의 본딩 주위를 실링하는 실링수지(4)로 이루어진다.Sealing sealing up around the bonding of the inner tape (1) with the taped tab (2), the chip (3) bump-bonded with the inner lead (1), and the inner lead (1) and the chip (3). It consists of resin (4).
내부리드(1)와 연결된 외부리드(5)는 바닥면에 수평으로 노출된다.The outer lead 5 connected to the inner lead 1 is horizontally exposed on the bottom surface.
이와같이 구성되는 본 고안의 제조과정을 설명한다.The manufacturing process of the present invention configured as described above will be described.
웨이퍼로 칩을 제조할때 단위칩 부분에 전도패드로 범프(3-1)를 형성하여 쏘잉함으로써 제1도와 같은 칩(3)을 수득한다.When manufacturing a chip from a wafer, a bump 3-1 is formed on the unit chip portion with a conductive pad and sawed to obtain a chip 3 as shown in FIG.
한편 탭테이프(2)는 폴리이미드등의 기재로된 테이프층(2-1)에 내, 외부리드(1,5) 형태의 금속패턴(2-2)을 형성하고, 내부리드(1)를 제2(a)도 및 (b)도와 같이 수직 정렬시킨다.On the other hand, the tab tape (2) forms a metal pattern (2-2) in the form of inner and outer leads (1, 5) on a tape layer (2-1) made of a substrate such as polyimide, and forms the inner lead (1). Vertical alignment is performed as shown in FIGS. 2 (a) and (b).
이경우 내부리드(1) 부분은 Ni+Au등으로 도금함이 바람직하다. 또한 상기 내부리드(1)와 일체로 되어 금속패턴(2-2)을 이루는 외부리드(5) 부분에는 예비시험용 패드(5-1)를 일체로 형성함이 바람직하다.In this case, the inner lead 1 is preferably plated with Ni + Au or the like. In addition, it is preferable that the preliminary test pad 5-1 is integrally formed on the outer lead part 5 which is integral with the inner lead 1 and forms the metal pattern 2-2.
상기 제2(a)(b)도와 같이 정렬된 상태에서 제3도와 같이 탭본딩툴(10)을 하강시켜 프레싱함으로써 범프(3-1)와 내부리드(1)를 어태치 시킨다.The bump 3-1 and the inner lead 1 are attached by lowering and pressing the tab bonding tool 10 as shown in FIG. 3 while being aligned as shown in FIG. 2 (a) (b).
이경우 바람직한 가열조건은 300∼400℃, 프레싱 압력은 15∼50kgf를 예시할 수 있다.In this case, preferable heating conditions are 300-400 degreeC, and a pressing pressure can illustrate 15-50 kgf.
이렇게 탭본딩(칩어태치)이 완료된후 에폭시 실링 수지(4)등으로 칩(3)과 내부리드(1) 부위를 실링시킨다.After the tap bonding is completed, the chip 3 and the inner lead 1 are sealed with an epoxy sealing resin 4 or the like.
이때 에폭시 수지(6)는 모세관 현상에 의하여 내부리드(1)와 칩(3) 주위의 계면을 긴밀히 실링되게 하여 경화시킴으로써 제4(a)도의 정면도 및 제4(b)도의 평면도(실제로는 저면도)상태를 이룰수 있게 된다.At this time, the epoxy resin 6 is hardened by tightly sealing the interface between the inner lead 1 and the chip 3 by a capillary phenomenon (the front view of FIG. 4 (a) and the plan view of FIG. 4 (b) (actually, Bottom view).
이어 연속반복 구성한 탭테이프(2)의 단위패키지용 외부리드(5) 단부에 있는 예비시험용 패드(5-1) 사이에 제5(a)도 및 제5(b)도와 같이 트림홀(2-4)를 형성하여 트림 공정을 수행하고, 이시점에서 칩(3)과 내외부리드간의 접속여부등을 테스팅함이 바람직하다. 제5(b)도에는 탭테이프(2) 뒷면에 있는 실링에폭시 실링수지(6)의 도포 부위를 점선으로 표시하였는바, 이선상이 실제의 단위패키지로 절단하는 부위가 된다.Subsequently, the trim hole 2 is formed between the preliminary test pads 5-1 at the end of the unit package outer lead 5 of the tab tape 2, which is continuously formed, as shown in Figs. 5 (a) and 5 (b). 4) it is desirable to perform a trim process and to test the connection between the chip 3 and the inner and outer leads at this point. In FIG. 5 (b), the application portion of the sealing epoxy sealing resin 6 on the back side of the tab tape 2 is indicated by a dotted line, and this line is a portion to be cut into the actual unit package.
이는 예비시험용 패드(5-1)를 통과한 단위패키지만 선택하여 이후의 마킹공정을 수행하기 위함이다.This is to select only the unit package passed through the preliminary test pad 5-1 to perform the subsequent marking process.
이렇게 트림시킨 다음 칩(3)의 표면에 마킹을 한 다음 점선부위를 절단시켜 제6(b)도와 같이 단위 패키지를 수득할수 있고 이때의 평면도(실제로는 저면도) 상태는 제6(c)도와 같이 나타낼수 있다. 즉, 외부리드(5)가 칩 하면에 노출되는 형태를 이룬다. 이는 제7도와 같이 별도의 인쇄회로기판(20)등에 형성한 패턴(21)에 표면실장시켜 사용할수 있다.After trimming like this, the surface of the chip 3 is marked, and the dotted portion is cut to obtain a unit package as shown in FIG. 6 (b), and the plan view (actually the bottom view) of the chip is shown in FIG. 6 (c). Can be represented as: That is, the external lead 5 is exposed to the bottom surface of the chip. This may be used by surface-mounting the pattern 21 formed on a separate printed circuit board 20 or the like as shown in FIG.
사실 도면에서는 확대도시 하였으나, 칩(3) 실제크기보다 외부리드(5)까지 합한 크기는 1㎜를 넘지않도록 할수 있어, 본 고안은 칩스케일 패키지를 탭테이프(2)를 사용하여 구현시킬수 있게 된다.In fact, although enlarged in the drawings, the combined size of the external lead 5 than the actual size of the chip 3 can be no more than 1 mm, the present invention can implement the chip scale package using the tap tape (2). .
이상과 같이 본고안은 탭테이프 기술을 칩스케일 패키지 기술에 접목시켰기에 제조공수가 줄어들고, 탭테이프의 외부리드가 저면에 수평을 이루도록 노출되어 기판과 표면실장을 가능케 한다.As described above, this paper combines tap tape technology with chip-scale package technology, thereby reducing manufacturing man-hours and exposing the outer tape of the tap tape to be horizontal to the bottom, thereby enabling substrate and surface mounting.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950053223U KR200153438Y1 (en) | 1995-12-29 | 1995-12-29 | Chip scale package using a tab tape |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019950053223U KR200153438Y1 (en) | 1995-12-29 | 1995-12-29 | Chip scale package using a tab tape |
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| Publication Number | Publication Date |
|---|---|
| KR970046899U KR970046899U (en) | 1997-07-31 |
| KR200153438Y1 true KR200153438Y1 (en) | 1999-08-02 |
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| KR2019950053223U KR200153438Y1 (en) | 1995-12-29 | 1995-12-29 | Chip scale package using a tab tape |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100648509B1 (en) * | 2000-12-06 | 2006-11-24 | 삼성전자주식회사 | Tape type lead-frame strip and structure and manufacturing method of lead exposed semiconductor chip package using it |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100470144B1 (en) * | 1997-08-12 | 2005-05-27 | 삼성전자주식회사 | Semiconductor chip package with tape circuit board and chip size using it |
| KR100523914B1 (en) * | 1999-03-03 | 2005-10-25 | 주식회사 하이닉스반도체 | gold ribbon pre-designed wirc bonding tape tape for bonding wire and method for bonding wire with such wire bonding tape |
-
1995
- 1995-12-29 KR KR2019950053223U patent/KR200153438Y1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100648509B1 (en) * | 2000-12-06 | 2006-11-24 | 삼성전자주식회사 | Tape type lead-frame strip and structure and manufacturing method of lead exposed semiconductor chip package using it |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970046899U (en) | 1997-07-31 |
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