JPH0310670Y2 - - Google Patents
Info
- Publication number
- JPH0310670Y2 JPH0310670Y2 JP10481086U JP10481086U JPH0310670Y2 JP H0310670 Y2 JPH0310670 Y2 JP H0310670Y2 JP 10481086 U JP10481086 U JP 10481086U JP 10481086 U JP10481086 U JP 10481086U JP H0310670 Y2 JPH0310670 Y2 JP H0310670Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- resin plate
- bonding
- metal wire
- thin metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011347 resin Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
産業上の利用分野
本考案は、半導体素子、集積回路素子等の素子
を、集積するようにした電子回路装置に関するも
のである。[Detailed Description of the Invention] Industrial Application Field The present invention relates to an electronic circuit device in which elements such as semiconductor elements and integrated circuit elements are integrated.
従来の技術
従来、この種装置は、第２図に示すような構成
となつている。すなわち、図において、１は、そ
の表裏両面にメツキして形成した導電層２と、裏
面導電層２を貫通孔３を介して表面に導出した導
電層２′と、その表面に形成した素子取付部４と
を有する樹脂板、５は、素子取付部４上にロー材
６を介して固着した半導体素子又は集積回路素子
等の素子、７は、素子５の電極と導電層２，２′
とをボンデイング結線した金属細線、８は、ラン
ド部８1と、このランド部８1より放射状に外方に
延びる複数本のリード部８2とからなるリードフ
レームで、このランド部８1に、樹脂板１に素子
５を取付け、素子５の電極と導電層２，２′とを
ボンデイング結線したものを、表裏両面に接着剤
９を付着した樹脂製の絶縁板１０を介して固着
し、しかる後、樹脂板１の端部迄導出した導電層
２と、リード部８2とを、金属細線１１を介して
ボンデイング結線してある。BACKGROUND ART Conventionally, this type of device has a configuration as shown in FIG. That is, in the figure, 1 indicates a conductive layer 2 formed by plating both the front and back surfaces, a conductive layer 2' that leads the back conductive layer 2 to the front surface through a through hole 3, and an element mounting layer formed on the surface. 5 is an element such as a semiconductor element or an integrated circuit element fixed on the element mounting part 4 via a brazing material 6, and 7 is an electrode of the element 5 and a conductive layer 2, 2'.
The thin metal wire 8 is a lead frame consisting of a land portion 8 1 and a plurality of lead portions 8 2 extending radially outward from the land portion 8 1 . The element 5 is attached to the resin plate 1, and the electrodes of the element 5 and the conductive layers 2, 2' are bonded and fixed via a resin insulating plate 10 with adhesive 9 adhered to both the front and back sides. Thereafter, the conductive layer 2 extended to the end of the resin plate 1 and the lead portion 8 2 are bonded together via a thin metal wire 11 .
考案が解決しようとする問題点
しかし、上記構成の場合、素子５の電極と導電
層２′とをボンデイング結線する際、通常、金属
細線７の先端を加熱し、その先端をボール状にし
て、素子５の電極にボンデイングし、金属細線７
を繰出しながらボンダーを導電層２′を上に移動
させ、導電層２′にボンデイングするようにして
いるが、この導電層２′が、軟弱な樹脂板１に形
成されたきわめて薄いものであるため、ボンダー
を押圧した時に、ボンダー先端のキヤピラリによ
る押圧で導電層２′が傾き、細線７の導電層２′へ
の押圧が弱くなつて、十分なボンデイング強度が
得られないことがあり、後にこのボンデイング部
が外れてオープン不良を起こすことがあつた。Problems to be Solved by the Invention However, in the case of the above structure, when bonding the electrode of the element 5 and the conductive layer 2', the tip of the thin metal wire 7 is usually heated and the tip is made into a ball shape. Bonded to the electrode of element 5, thin metal wire 7
While feeding out the bonder, the conductive layer 2' is moved upward and bonded to the conductive layer 2'. However, since this conductive layer 2' is formed on the soft resin plate 1 and is extremely thin. When the bonder is pressed, the conductive layer 2' is tilted due to the pressure from the capillary at the tip of the bonder, and the pressure of the thin wire 7 on the conductive layer 2' becomes weak, which may result in insufficient bonding strength. There were cases where the bonding part came off and caused an open failure.
問題点を解決するための手段
本考案は、上記点を改良するために提案された
もので、導電層のボンデイング位置に金線をボン
デイングしてプレスすることにより形成したバン
プ部を設けたことを特徴とする。Means for Solving the Problems The present invention was proposed in order to improve the above-mentioned points, and includes providing a bump portion formed by bonding and pressing a gold wire at the bonding position of the conductive layer. Features.
実施例
以下、本考案の一実施例を図面により説明する
と、第１図において、２１は、その表裏両面にメ
ツキして形成した導電層２２と、裏面導電層２２
を貫通孔２３を介して表面に導出した導電層２
２′と、その表面に形成した素子取付部２４とを
有する樹脂板、２５は、素子取付部４上にロー材
２６を介して固着した素子、２７は、素子２５の
電極と導電層２２，２２′とをボンデイング結線
した金属細線、２８は、リードフレームのランド
部で、その上に、表裏両面に接着剤２９を付着し
た絶縁板３０を介して、前述した樹脂板２１に素
子２５を取付け、素子２５の電極と導電層２２，
２２′とをボンデイング結線したものを固着し、
しかる後、図示省略したが、樹脂板２１の端部迄
導出した導電層２２と、リードフレームのリード
部とをボンデイング結線してある。Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG.
The conductive layer 2 is led out to the surface through the through hole 23.
2' is a resin plate having an element mounting part 24 formed on its surface; 25 is an element fixed on the element mounting part 4 via a brazing material 26; 27 is an electrode of the element 25 and a conductive layer 22; The thin metal wire 28, which is bonded to the lead frame 22', is a land portion of the lead frame, and the element 25 is attached to the resin plate 21 described above via an insulating plate 30 with adhesive 29 adhered to both the front and back sides. , the electrode of the element 25 and the conductive layer 22,
22' and fixed by bonding,
Thereafter, although not shown, the conductive layer 22 extended to the end of the resin plate 21 and the lead portion of the lead frame are connected by bonding.
ここまでは、第２図に示す従来例と同一で、本
考案では、導電層２２′上に、バンプ部３１を設
けたことに特徴があり、このバンプ部３１上に、
金属細線２７をボンデイング結線するようにして
ある。 The steps up to this point are the same as the conventional example shown in FIG.
The thin metal wires 27 are connected by bonding.
すなわち、このバンプ部３１は、金線の先端を
加熱してボール状となつたものを、導電層２２′
上に、ボンデイングして固着し切断した後、その
上より、プレスして平担とすることにより形成さ
れる。 That is, this bump portion 31 is made by heating the tip of a gold wire to form a ball shape, and then attaching it to the conductive layer 22'.
It is formed by bonding and fixing it on top, cutting it, and then pressing it from above to make it flat.
尚、上記実施例は、リードフレームに取付けた
場合を説明したが、これに限定されるものではな
く、ステムあるいはパツケージに取付けるものに
も適用できる。 Incidentally, in the above embodiment, the case where the device is attached to a lead frame has been described, but the present invention is not limited to this, and the device can also be applied to a case where the device is attached to a stem or a package.
考案の効果
本考案は、以上のような構成であるから、裏面
導電層を貫通孔を介して表面に導出した導電層
に、金属細線をボンデイング結線した場合、ボン
ダー先端のキヤピラリによる押圧は、比較的柔ら
かい金製のバンプ部で吸収することができ、細線
のバンプ部への押圧が十分となつて、飛躍的にボ
ンデイング強度を上げることができ、ボンデイン
グ部が外れて、オープン不良になるという事故が
一掃された。Effects of the invention Since the present invention has the above-mentioned configuration, when a fine metal wire is bonded to the conductive layer led from the back conductive layer to the front surface through the through hole, the pressure exerted by the capillary at the tip of the bonder is This can be absorbed by the soft gold bump part, and the pressure on the thin wire bump part is sufficient, dramatically increasing the bonding strength, and preventing accidents such as the bonding part coming off and causing an open failure. was wiped out.
第１図は、本考案に係る電子回路装置の要部の
み示す縦断面図、第２図は、従来の電子回路装置
の縦断面図である。
２１……樹脂板、２２，２２′……導電層、２
３……貫通孔、２４……素子取付部、２５……素
子、２７……金属細線、３１……バンプ部。
FIG. 1 is a vertical cross-sectional view showing only the essential parts of an electronic circuit device according to the present invention, and FIG. 2 is a vertical cross-sectional view of a conventional electronic circuit device. 21... Resin plate, 22, 22'... Conductive layer, 2
3...Through hole, 24...Element mounting portion, 25...Element, 27...Thin metal wire, 31...Bump portion.
Claims (1)
に、裏面導電層を樹脂板に穿設した貫通孔を介し
て表面に導出し、これら導電層と樹脂板表面の素
子取付部に固着した素子の電極とをボンデイング
結線するようにした電子回路装置において、前記
導電層のボンデイング位置に金線をボンデイング
してプレスすることにより形成したバンプ部を設
けたことを特徴とする電子回路装置。 Conductive layers are formed on both the front and back sides of the resin plate, and the back conductive layer is led to the front surface through a through hole drilled in the resin plate, and these conductive layers and the element electrodes are fixed to the element mounting portion on the resin plate surface. What is claimed is: 1. An electronic circuit device, characterized in that a bump portion formed by bonding and pressing a gold wire is provided at a bonding position of the conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10481086U JPH0310670Y2 (en) | 1986-07-08 | 1986-07-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10481086U JPH0310670Y2 (en) | 1986-07-08 | 1986-07-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6310552U JPS6310552U (en) | 1988-01-23 |
| JPH0310670Y2 true JPH0310670Y2 (en) | 1991-03-15 |
Family
ID=30978646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10481086U Expired JPH0310670Y2 (en) | 1986-07-08 | 1986-07-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0310670Y2 (en) |
-
1986
- 1986-07-08 JP JP10481086U patent/JPH0310670Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6310552U (en) | 1988-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900005587A (en) | Semiconductor device and manufacturing method | |
| JP2569939B2 (en) | Resin-sealed semiconductor device | |
| US6291269B1 (en) | Semiconductor bare chip, method of manufacturing semiconductor bare chip and mounting structure of semiconductor bare chip | |
| US5533664A (en) | Method of manufacturing a semiconductor device | |
| JPH0310670Y2 (en) | ||
| JPH10335368A (en) | Wire-bonding structure and semiconductor device | |
| KR940027134A (en) | Manufacturing method of semiconductor integrated circuit device | |
| JPH0754841B2 (en) | Insulator-sealed circuit device | |
| KR200153438Y1 (en) | Chip scale package using a tab tape | |
| JP2743157B2 (en) | Resin-sealed semiconductor device | |
| JPS63152161A (en) | Semiconductor device | |
| JP2589520B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JP2513044Y2 (en) | Semiconductor device | |
| JPS6334281Y2 (en) | ||
| JP2785441B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS635253Y2 (en) | ||
| JPS63187330U (en) | ||
| JPS6032769Y2 (en) | semiconductor element | |
| JPH04240751A (en) | Chip carrier | |
| JP2622988B2 (en) | Semiconductor device | |
| JPH0392038U (en) | ||
| JPS5915504Y2 (en) | Resin-encapsulated semiconductor device | |
| JPH04239160A (en) | Manufacture of resin-sealed type electronic component | |
| JPH09306953A (en) | Bare chip-mounted semiconductor device and manufacture thereof | |
| JPS61287136A (en) | Semiconductor device |