JPH04239160A - Manufacture of resin-sealed type electronic component - Google Patents
Manufacture of resin-sealed type electronic componentInfo
- Publication number
- JPH04239160A JPH04239160A JP3013693A JP1369391A JPH04239160A JP H04239160 A JPH04239160 A JP H04239160A JP 3013693 A JP3013693 A JP 3013693A JP 1369391 A JP1369391 A JP 1369391A JP H04239160 A JPH04239160 A JP H04239160A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- chip
- resin
- groove
- recessed part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 238000005219 brazing Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005201 scrubbing Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 12
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 3
- 230000035515 penetration Effects 0.000 abstract 2
- 230000001681 protective effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はダイオード、トランジス
タ、ＩＣ等の樹脂封止型電子部品の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing resin-sealed electronic components such as diodes, transistors, and ICs.
【０００２】0002
【従来の技術及び発明が解決しようとする課題】半導体
素子をこの支持板と共に樹脂封止体で封止した樹脂封止
型半導体装置は周知である。この種の半導体装置におい
て、樹脂封止体と支持板の界面を通じて半導体素子の載
置された領域に水分等の不純物（異物）が侵入すると、
半導体装置の特性が低下する。そこで、本願発明者は、
半導体素子の載置された領域を囲む溝を支持板に設ける
試みをした。これにより、不純物の侵入を溝によって抑
制することができ、半導体装置の特性低下をそれなりに
防止することができた。しかしながら、今日、半導体装
置の高機能化等のためにチップ（半導体素子）の大型化
が進んでいる。このため、チップを支持板に固着する半
田が溝に流れ込むことがあり、溝の不純物侵入防止効果
が低減することがあった。2. Description of the Related Art A resin-sealed semiconductor device in which a semiconductor element and a support plate are encapsulated with a resin molding body is well known. In this type of semiconductor device, if impurities (foreign substances) such as moisture enter the area where the semiconductor element is mounted through the interface between the resin molding body and the support plate,
The characteristics of the semiconductor device deteriorate. Therefore, the inventor of the present application,
An attempt was made to provide the support plate with a groove surrounding the area where the semiconductor element was placed. As a result, it was possible to suppress the intrusion of impurities by the groove, and it was possible to prevent the characteristics of the semiconductor device from deteriorating to a certain extent. However, today, chips (semiconductor elements) are becoming larger due to higher functionality of semiconductor devices. For this reason, the solder that fixes the chip to the support plate may flow into the groove, reducing the effect of the groove in preventing impurity intrusion.
【０００３】そこで、本発明はろう材の不要な流れを防
ぐことができる電子部品の製造方法を提供することを目
的とする。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for manufacturing electronic components that can prevent unnecessary flow of brazing filler metal.
【０００４】0004
【課題を解決するための手段】上記目的を達成するため
の本発明は、凹部と該凹部を実質的に包囲する溝とを有
し、前記凹部の底面に電子素子をスクラブしてろう接す
るためのスクラブ領域を有し、前記凹部の底面は前記ス
クラブ領域よりも大きい面積を有している導電性支持板
を用意する工程と、前記凹部の底面にろう材を供給し、
前記ろう材の上に前記電子素子を載置し、前記スクラブ
領域内において前記電子素子を前記ろう材を介してスク
ラブすることによって前記電子素子を前記スクラブ領域
内にろう付けする工程と、前記電子素子、前記凹部及び
前記溝を含むように前記支持板を被覆する樹脂封止体を
設ける工程とを有することを特徴とする樹脂封止型電子
部品の製造方法に係わるものである。[Means for Solving the Problems] The present invention has a recess and a groove that substantially surrounds the recess, and an electronic element is scrubbed and soldered to the bottom of the recess. providing a conductive support plate having a scrub region, the bottom surface of the recess having a larger area than the scrub region, and supplying a brazing material to the bottom surface of the recess,
placing the electronic device on the brazing material and scrubbing the electronic device through the brazing material in the scrub region to braze the electronic device in the scrub region; The present invention relates to a method of manufacturing a resin-sealed electronic component, comprising a step of providing a resin-sealed body covering the support plate so as to include an element, the recess, and the groove.
【０００５】[0005]
【作用】本発明によれば、電子素子が支持板の凹部底面
に配設されたスクラブ領域内にろう付けされる。スクラ
ブ領域は凹部の底面積よりも小さく設定されており、電
子素子は凹部の壁面に当接しないスクラブ運動（スクラ
ブ運動）を伴ってこの領域にろう付けされる。したがっ
て、ろう材が凹部の外側に流れ出すことが有効に抑制さ
れる。このため、凹部の外側に形成された溝にろう材が
流れ込み難く、溝は異物侵入防止の効果を有効に発揮す
る。According to the present invention, an electronic device is brazed in a scrub region provided at the bottom of a recess in a support plate. The scrub area is set to be smaller than the bottom area of the recess, and the electronic device is brazed to this area with a scrubbing motion that does not contact the wall surface of the recess. Therefore, the brazing material is effectively prevented from flowing out of the recess. Therefore, it is difficult for the brazing material to flow into the groove formed on the outside of the recess, and the groove effectively exhibits the effect of preventing foreign matter from entering.
【０００６】[0006]
【実施例】次に、図１〜図４を参照して本発明の一実施
例に係わる樹脂封止型半導体装置の製造方法を説明する
。Embodiment Next, a method for manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.
【０００７】まず、図２に示すリードフレーム１１を用
意する。このリードフレーム１１は放熱板を兼ねる比較
的厚い金属製支持板１２と、この支持板１２の一方の端
部側に配置された比較的薄い板状外部リード１３と、支
持板１２の他方の端部側に配置された比較的薄い板状支
持リード１４と、外部リード１３及び支持リード１４を
連結する比較的薄い細条１５、１６、１７から構成され
ている。実際のリードフレームでは、細条１５、１６、
１７の延びる方向（横方向）に複数の支持板１２が並設
されて全体として梯子形状となっている。しかしながら
、図２では図面を簡略化して支持板１２を１個のみ示す
。First, a lead frame 11 shown in FIG. 2 is prepared. This lead frame 11 includes a relatively thick metal support plate 12 that also serves as a heat dissipation plate, a relatively thin plate-shaped external lead 13 disposed at one end of the support plate 12, and the other end of the support plate 12. It consists of a relatively thin plate-shaped support lead 14 disposed on the side, and relatively thin strips 15, 16, and 17 that connect the external lead 13 and the support lead 14. In the actual lead frame, strips 15, 16,
A plurality of support plates 12 are arranged in parallel in the direction in which the support plates 17 extend (horizontal direction), forming a ladder shape as a whole. However, in FIG. 2, the drawing is simplified and only one support plate 12 is shown.
【０００８】支持板１２の一方の主面の中央側には図２
に示すように略正方形の平面形状を有する凹部１８が形
成されている。凹部１８の底面は、チップが載置される
チップ載置予定領域（スクラブ領域）１９を凹部１８の
壁面から離間した底面中央に有する。凹部１８の底面積
はチップ載置予定領域１９の面積よりも十分に大きい。
即ち凹部１８の一辺はチップのスクラブされる距離より
も大きく設計されている。また、凹部１８の深さはチッ
プ載置予定領域１９に半田付けされるチップの厚みより
も小さい。[0008] On the center side of one main surface of the support plate 12, there is a mark shown in FIG.
As shown in FIG. 2, a recess 18 having a substantially square planar shape is formed. The bottom surface of the recess 18 has a chip placement area (scrub area) 19 in the center of the bottom surface spaced apart from the wall surface of the recess 18 . The bottom area of the recess 18 is sufficiently larger than the area of the intended chip mounting area 19. That is, one side of the recess 18 is designed to be larger than the distance over which the chip is scrubbed. Further, the depth of the recess 18 is smaller than the thickness of the chip to be soldered to the intended chip mounting area 19.
【０００９】支持板１２の一方の主面には凹部１８を包
囲する２本の環状溝２０ａ、２０ｂが互いに離間して配
設されている。図１に示すように、環状溝２０ａ、２０
ｂはＶ字状の断面形状を有する。また、凹部１８の底面
の外周端にもＶ字状の環状溝２１が形成されている。凹
部１８及び環状溝２０ａ、２０ｂ、２１はリードフレー
ム１１を形成するための一連のプレス加工において形成
される。Two annular grooves 20a and 20b surrounding the recess 18 are provided on one main surface of the support plate 12 at a distance from each other. As shown in FIG. 1, annular grooves 20a, 20
b has a V-shaped cross section. Further, a V-shaped annular groove 21 is also formed at the outer peripheral end of the bottom surface of the recess 18 . The recess 18 and the annular grooves 20a, 20b, 21 are formed in a series of press operations for forming the lead frame 11.
【００１０】次に、支持板１２にチップを半田付けする
ために、支持板１２のチップ載置予定領域１９にろう材
としての半田２２を加熱溶融状態且つ膜状に広げる。続
いて、図１に示すチップ吸着保持体（以下、コレットと
称する）２３を用意して、固着すべき電子素子としての
半導体チップ２４をコレット２３の空間に対応する壁面
２３ａに吸着させる。このとき、チップ２４の底面はコ
レット２３の下面よりも下側に突出する。続いて、図示
のようにチップ載置予定領域１９のほぼ中央位置におい
て半田２２の上にチップ２４を押し付けた後、矢印２５
に示す左右方向にチップ２４をコレット２３と共に直線
往復運動（スクラブ運動）させてチップ２４を半田２２
で固着する。チップ２４のスクラブされる距離即ちコレ
ット２３を凹部１８の一方の壁面側に移動させたときの
チップ２４の一方の側縁の位置Ａとコレット２３を凹部
１８の他方の壁面側に移動させたときのチップ２４の他
方の側縁の位置Ｂとの間隔Ｌ１ は、凹部１８の一辺の
長さＬ２よりも小さくなっている。また、チップ２４の
下方にある半田２２の厚みとコレット２３の底面から突
出したチップ２４の突出量は、凹部１８の深さよりも大
きくなっている。したがって、チップ２４をスクラブし
た際に、コレット２３及びチップ２４が凹部１８の壁面
に当接することが確実に防止されている。また、半田２
２の流れは凹部１８の側壁で阻止され且つ溝２１に収容
される。[0010] Next, in order to solder the chip to the support plate 12, solder 22 as a brazing material is heated and melted and spread in the form of a film in the area 19 of the support plate 12 where the chip is to be placed. Subsequently, a chip adsorption holder (hereinafter referred to as a collet) 23 shown in FIG. At this time, the bottom surface of the chip 24 protrudes below the bottom surface of the collet 23. Next, as shown in the figure, after pressing the chip 24 onto the solder 22 at approximately the center of the intended chip mounting area 19, the arrow 25
The chip 24 is moved along with the collet 23 in a straight line reciprocating motion (scrubbing motion) in the left-right direction shown in FIG.
It will stick. The scrubbing distance of the chip 24, that is, the position A of one side edge of the chip 24 when the collet 23 is moved to one wall side of the recess 18, and the position A of one side edge of the chip 24 when the collet 23 is moved to the other wall side of the recess 18. The distance L1 between the other side edge of the chip 24 and the position B is smaller than the length L2 of one side of the recess 18. Further, the thickness of the solder 22 below the chip 24 and the amount of protrusion of the chip 24 from the bottom surface of the collet 23 are larger than the depth of the recess 18 . Therefore, when the chip 24 is scrubbed, the collet 23 and the chip 24 are reliably prevented from coming into contact with the wall surface of the recess 18. Also, solder 2
2 flow is blocked by the side wall of the recess 18 and accommodated in the groove 21.
【００１１】図３のように、チップ２４が半田２２を介
して凹部１８のチップ載置予定領域１９に固着されたら
、周知のワイヤボンディング法によってチップ２４と外
部リード１３との間にリード細線２６を図２に示すよう
に接続する。続いて、シリコン樹脂等から成る保護樹脂
２７をチップ２４の上面に滴下して、図３に示すように
チップ２４とリード細線２６のチップ２４への接続部分
側を被覆する。保護樹脂２７は凹部１８を充填し、その
一部は凹部１８よりも外側まで広がるが、溝２０ａが保
護樹脂２７の流れ留めとして機能するから、保護樹脂２
７は溝２０ａよりも外側には広がらない。As shown in FIG. 3, once the chip 24 is fixed to the intended chip mounting area 19 of the recess 18 via the solder 22, thin lead wires 26 are bonded between the chip 24 and the external leads 13 by a well-known wire bonding method. Connect as shown in Figure 2. Subsequently, a protective resin 27 made of silicone resin or the like is dropped onto the upper surface of the chip 24 to cover the chip 24 and the connecting portions of the thin lead wires 26 to the chip 24, as shown in FIG. The protective resin 27 fills the recess 18 and a part of it spreads to the outside of the recess 18, but since the groove 20a functions as a stop for the protective resin 27 to flow, the protective resin 2
7 does not extend outward beyond the groove 20a.
【００１２】次に、リードフレーム１１とチップ２４と
リード細線２６から成る組立体を成形用型に配置して、
周知のトランスファモールドを行うことによって、樹脂
封止体２８を樹脂成形する。樹脂封止体２８は支持板１
２の全面と外部リード１３及び支持リード１４の一部を
被覆する。最後に、細条１５、１６、１７と支持リード
１４を除去することによって、図４に示す樹脂封止型半
導体装置を完成させる。なお、支持リード１４の引抜き
破断によって、樹脂封止体２８に孔２８ａが生じるが、
極めて小さいので、ほとんど問題にならない。この孔２
８ａは必要に応じて樹脂で埋められる。Next, the assembly consisting of the lead frame 11, chip 24, and thin lead wire 26 is placed in a mold, and
The resin sealing body 28 is resin-molded by performing well-known transfer molding. The resin sealing body 28 is the support plate 1
2 and a portion of the external leads 13 and support leads 14. Finally, by removing the strips 15, 16, 17 and the support lead 14, the resin-sealed semiconductor device shown in FIG. 4 is completed. Note that a hole 28a is created in the resin sealing body 28 by pulling out and breaking the support lead 14.
It's so small that it's hardly a problem. This hole 2
8a is filled with resin as necessary.
【００１３】本実施例で製作された樹脂封止型半導体装
置によれば、チップ２４が凹部１８の底面に半田付けさ
れ且つスクラブの距離Ｌ１ が凹部１８のスクラブ方向
に延びる一辺の長さＬ２ よりも小さく設定されている
。しかも、スクラブ中にチップ２４を凹部１８の壁面に
当接させないから、チップ２４を支持板１２に固着する
ための半田２２の凹部１８からの流れ出しが有効に防止
されている。また、溝２１は半田２２の一部を収容する
働きを有するので、チップ２４の側面及びコレット２３
の側面に対する半田２２の付着を有効に防止する。According to the resin-sealed semiconductor device manufactured in this embodiment, the chip 24 is soldered to the bottom surface of the recess 18, and the scrub distance L1 is longer than the length L2 of one side of the recess 18 extending in the scrub direction. is also set small. Moreover, since the chip 24 is not brought into contact with the wall surface of the recess 18 during scrubbing, the solder 22 for fixing the chip 24 to the support plate 12 is effectively prevented from flowing out from the recess 18. Further, since the groove 21 has the function of accommodating a part of the solder 22, the side surface of the chip 24 and the collet 23
This effectively prevents the solder 22 from adhering to the side surfaces.
【００１４】また、保護樹脂２７の外側への流れ出しも
環状溝２０ａによって留められている。結果として、異
物侵入防止用の溝２０ｂに半田２２や保護樹脂２７が入
り込むことが防止され、溝２０ｂによる異物侵入防止効
果が強力に得られる。本実施例で製作された樹脂封止型
半導体装置によれば、長期間使用しても特性低下が許容
されるレベル以下に収まることが確認されている。[0014] Further, the outflow of the protective resin 27 to the outside is also stopped by the annular groove 20a. As a result, the solder 22 and the protective resin 27 are prevented from entering the groove 20b for preventing foreign matter from entering, and the groove 20b has a strong effect of preventing foreign matter from entering. According to the resin-sealed semiconductor device manufactured in this example, it has been confirmed that the deterioration in characteristics is kept below an allowable level even after long-term use.
【００１５】[0015]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。
（１） 溝２０ａを省くことができる。また溝２１を
省くこともできる。
（２） 溝２０ｂを凹部１８を完全に包囲するように
形成せずに、非連続部分を有するように形成することが
できる。
（３） スクラブの運動方向は実施例に限られない。
例えば、チップ２４の中心点を軸として円運動させても
よい。この場合、凹部１８の底面積は少なくともチップ
２４の対角線を直径とする円の面積よりも大きくし、且
つスクラブ領域を凹部１８の壁面から離間させた中央側
に配設する。[Modifications] The present invention is not limited to the above-described embodiments, but can be modified as follows, for example. (1) The groove 20a can be omitted. Moreover, the groove 21 can also be omitted. (2) The groove 20b may not be formed to completely surround the recess 18, but may be formed to have a discontinuous portion. (3) The direction of movement of the scrub is not limited to the example. For example, the tip 24 may be moved in a circular motion about the center point of the tip 24 as an axis. In this case, the bottom area of the recess 18 is at least larger than the area of a circle whose diameter is the diagonal of the chip 24, and the scrub area is arranged in the center of the recess 18, spaced apart from the wall surface.
【００１６】[0016]
【発明の効果】以上のように、本発明によれば、ろう材
の不要な流れが防止され、支持板に形成された溝が電子
素子載置領域側への異物侵入を有効に阻止する。従って
長期間にわたって特性低下が生じない樹脂封止型電子部
品を提供することができる。As described above, according to the present invention, unnecessary flow of the brazing material is prevented, and the groove formed in the support plate effectively prevents foreign matter from entering the electronic element mounting area. Therefore, it is possible to provide a resin-sealed electronic component whose characteristics do not deteriorate over a long period of time.
【図１】本発明の実施例におけるスクラブ状態を図２の
１−１線に相当する部分によって示す断面図である。FIG. 1 is a sectional view showing a scrubbing state in an embodiment of the present invention, taken along the line 1-1 in FIG. 2;
【図２】リードフレームを示す平面図である。FIG. 2 is a plan view showing a lead frame.
【図３】保護樹脂による被覆を示す断面図である。FIG. 3 is a sectional view showing coating with a protective resin.
【図４】完成した半導体装置を示す断面図である。FIG. 4 is a cross-sectional view showing a completed semiconductor device.
１１ リードフレーム １２ 支持板 １３ 外部リード １８ 凹部 １９ チップ載置予定領域 ２０ａ，２０ｂ，２１ 溝 11 Lead frame 12 Support plate 13 External lead 18 Recess 19 Planned area for chip placement 20a, 20b, 21 groove
Claims (1)
を有し、前記凹部の底面に電子素子をスクラブしてろう
接するためのスクラブ領域を有し、前記凹部の底面は前
記スクラブ領域よりも大きい面積を有している導電性支
持板を用意する工程と、前記凹部の底面にろう材を供給
し、前記ろう材の上に前記電子素子を載置し、前記スク
ラブ領域内において前記電子素子を前記ろう材を介して
スクラブすることによって前記電子素子を前記スクラブ
領域内にろう付けする工程と、前記電子素子、前記凹部
及び前記溝を含むように前記支持板を被覆する樹脂封止
体を設ける工程とを有することを特徴とする樹脂封止型
電子部品の製造方法。1. A semiconductor device comprising a recess and a groove substantially surrounding the recess, a scrub region for scrubbing and soldering an electronic element on a bottom surface of the recess, and a bottom surface of the recess that is connected to the scrub region. providing a conductive support plate having an area larger than Brazing the electronic element in the scrub area by scrubbing the electronic element through the brazing material, and resin sealing to cover the support plate to include the electronic element, the recess, and the groove. 1. A method for manufacturing a resin-sealed electronic component, comprising the step of providing a body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3013693A JP2861417B2 (en) | 1991-01-11 | 1991-01-11 | Method for manufacturing resin-encapsulated electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3013693A JP2861417B2 (en) | 1991-01-11 | 1991-01-11 | Method for manufacturing resin-encapsulated electronic component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04239160A true JPH04239160A (en) | 1992-08-27 |
| JP2861417B2 JP2861417B2 (en) | 1999-02-24 |
Family
ID=11840274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3013693A Expired - Fee Related JP2861417B2 (en) | 1991-01-11 | 1991-01-11 | Method for manufacturing resin-encapsulated electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2861417B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156606A (en) * | 2004-11-29 | 2006-06-15 | Nippon Inter Electronics Corp | Method for manufacturing semiconductor device |
| JP2008053478A (en) * | 2006-08-25 | 2008-03-06 | Matsushita Electric Ind Co Ltd | Lead frame, package component, manufacturing method thereof, and semiconductor device |
-
1991
- 1991-01-11 JP JP3013693A patent/JP2861417B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156606A (en) * | 2004-11-29 | 2006-06-15 | Nippon Inter Electronics Corp | Method for manufacturing semiconductor device |
| JP2008053478A (en) * | 2006-08-25 | 2008-03-06 | Matsushita Electric Ind Co Ltd | Lead frame, package component, manufacturing method thereof, and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2861417B2 (en) | 1999-02-24 |
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