KR100351926B1 - Ball Grid Array package - Google Patents
Ball Grid Array package Download PDFInfo
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- KR100351926B1 KR100351926B1 KR1020000066041A KR20000066041A KR100351926B1 KR 100351926 B1 KR100351926 B1 KR 100351926B1 KR 1020000066041 A KR1020000066041 A KR 1020000066041A KR 20000066041 A KR20000066041 A KR 20000066041A KR 100351926 B1 KR100351926 B1 KR 100351926B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 비·지·에이 패키지(BGA package ; Ball Grid Array package)의 구조 개선을 통해 제1번 와이어에도 와이어 본딩 모니터링 시스템의 적용이 가능하도록 하는 한편, 다이 어태치 공정을 위한 접착제 도포량의 조절이 용이하게 이루어지고 패키지의 열소산 능력이 향상되도록 한 것이다.The present invention enables the wire bonding monitoring system to be applied to the first wire through the structural improvement of the ball grid array package (BGA package), while controlling the amount of adhesive applied for the die attach process. This is done easily and improves the heat dissipation capacity of the package.
이를 위해, 본 발명은 상면에 복수개의 핑거부(110)가 구비되고 내부에는 상기 각 핑거부(110)에 연결된 비어홀(100)이 구비되는 회로기판(1)과, 상기 회로기판(1) 상면에 부착되는 반도체칩(2)과, 상기 반도체칩(2)과 회로기판(1) 사이에 개재되는 비도전성 접착제(4)와, 상기 회로기판(1)의 반도체칩(2) 부착 영역 내측에 위치하며 하단부가 상기 회로기판(1)상의 비어홀(100)에 연결되며 상단부가 칩 하면에 접촉하게 되는 칩 커넥션 핀(7)과, 상기 반도체칩(2)의 본딩패드(200)와 상기 회로기판(1)의 상부기층에 구비된 핑거부(110)를 전기적으로 연결하는 전도성연결부재와, 상기 반도체칩(2)의 본딩패드(200)와 전도성연결부재 및 핑거부(110)가 외부로부터 보호되도록 감싸는 몰드바디(6)와, 상기 회로기판(1)의 저면에 부착되는 솔더볼(5)을 포함하여서 되는 비·지·에이 패키지가 제공된다.To this end, in the present invention, a plurality of finger parts 110 are provided on an upper surface thereof, and a circuit board 1 having a via hole 100 connected to each finger part 110 therein, and an upper surface of the circuit board 1. A semiconductor chip 2 adhered to the semiconductor chip 2, a non-conductive adhesive 4 interposed between the semiconductor chip 2 and the circuit board 1, and a region inside the semiconductor chip 2 attachment region of the circuit board 1. A chip connection pin 7 having a lower end connected to the via hole 100 on the circuit board 1 and having an upper end contacting the bottom surface of the chip, a bonding pad 200 of the semiconductor chip 2, and the circuit board The conductive connecting member for electrically connecting the finger portion 110 provided in the upper base layer of (1), the bonding pad 200, the conductive connecting member and the finger portion 110 of the semiconductor chip 2 is protected from the outside B, G, A which includes a mold body 6 wrapped as much as possible and a solder ball 5 attached to the bottom surface of the circuit board 1. Package is provided.
Description
본 발명은 비·지·에이 패키지 구조에 관한 것으로서, 더욱 상세하게는 비·지·에이 패키지(BGA package ; Ball Grid Array package)의 구조 개선을 통해 제1번 와이어에도 와이어 본딩 모니터링 시스템(Wire Bonding Monitoring System)의 적용이 가능하도록 함과 더불어 다이 어태치 공정을 위한 접착제 도포량의 조절이 용이하게 이루어질 수 있도록 한 것이다.The present invention relates to a BG package structure, and more particularly, to a wire bonding monitoring system (Wire Bonding) for wire No. 1 through a structure improvement of a BGA package (BGA package). In addition to the monitoring system, it is possible to easily control the amount of adhesive applied for the die attach process.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따른 다핀화, 실장형태의 다양화에 따른 패키지의 다종류화 등으로 인해 미세 조립기술등 조립공정과 관련된 기술도각각 세분된 분야에 따라 크게 변화하고 있다.In addition, recently, due to the high integration of integrated circuits and the multi-package of packages due to the diversification of the mounting type, the technology related to the assembly process, such as micro-assembly technology has been changed greatly in the subdivided fields.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지(Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and the lead type.A representative example of the package is a quad flat package (QFP), thin small outline package (TSOP), and ball grid array (BGA), in addition to the dual inline package (DIP). packages, BLP (Bottom Leaded Package), and the like, and continue to be multi-pin or light and thin.
상기한 패키지 타입중, 비·지·에이 패키지(Ball Grid Array package)는 반도체칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 비·지·에이 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 하는데 유리하며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the package types described above, a B, G, and B package is used in place of an outer lead by arranging a spherical solder ball in a predetermined state on the back side of a substrate on which a semiconductor chip is attached. In addition, the B, G, and A packages are advantageous in making a package body area smaller than a Quad Flat Package (QFP) type, and unlike the QFP, there is an advantage in that there is no deformation of a lead.
한편, 이하에서는 비·지·에이 패키지중 칩 어레이 타입 비·지·에이 패키지를 예로 들어 설명하고자 한다.In the following description, a chip array type BG package among BG packages will be described as an example.
도 1은 비·지·에이 패키지중 칩 어레이 타입 비·지·에이 패키지 구조를 나타낸 종단면도이고, 도 2는 도 1의 Ⅰ-Ⅰ선을 따른 횡단면도로서, 칩 어레이 타입 비·지·에이 패키지는 회로기판 내에 복수개의 개별 윈도우(또는 서브-페이지)가 구비되고, 개별 윈도우 내에 복수개의 반도체소자가 행열(예;5행 3열)을 이루며 탑재되는 구조이다.1 is a vertical cross-sectional view showing a chip array type B / G package structure of a BG package, and FIG. 2 is a cross-sectional view along the line I-I of FIG. 1, and shows a chip array type BG package. Is a structure in which a plurality of individual windows (or sub-pages) are provided in a circuit board, and a plurality of semiconductor elements are arranged in rows (eg, 5 rows and 3 columns) in the individual windows.
기존의 칩 어레이 타입 비·지·에이 패키지 구조 및 제조 과정을 도 1 내지 도 3을 참조하여 개략적으로 설명하면 다음과 같다.A conventional chip array type B, G, and A package structure and manufacturing process will be described with reference to FIGS. 1 to 3 as follows.
먼저, 웨이퍼 상면에 집적회로를 형성하는 FAB(Fabrication) 공정이 끝난 상태에서 웨이퍼에 형성된 반도체칩을 개별적으로 분리하기 위한 소잉(sawing)을 실시한다.First, sawing is performed to individually separate semiconductor chips formed on a wafer in a state where an FAB (fabrication) process for forming an integrated circuit on the upper surface of the wafer is completed.
그 다음, 내부에 회로패턴이 형성된 회로기판(1)이 공정에 투입됨에 따라 회로기판(1)의 상면에 각 윈도우(8)별로 비도전성 에폭시등의 접착제(4)를 도포하여 소잉된 개별 반도체칩(2)을 부착시키는 다이 어태치(die attach) 공정을 수행하게 되며, 다이 어태치 공정이 끝난 후에는 반도체칩(2)에 형성된 본딩패드(200)와 회로기판(1)에 형성된 회로패턴의 핑거부(110)를 골드와이어(3)를 이용하여 서로 전기적으로 연결시키는 와이어 본딩을 실시하게 된다.Then, as the circuit board 1 having the circuit pattern formed therein is introduced into the process, the individual semiconductors are baked by applying an adhesive 4 such as a non-conductive epoxy to each window 8 on the upper surface of the circuit board 1. A die attach process for attaching the chip 2 is performed, and after the die attach process is completed, a bonding pad 200 formed on the semiconductor chip 2 and a circuit pattern formed on the circuit board 1 are performed. The wire portion 110 is electrically connected to each other by using the gold wire (3).
그리고, 와이어 본딩이 완료된 후에는 반도체칩(2) 및 골드와이어(3)를 봉지수지인 EMC(15)(Epoxy Molding Compound)로 몰딩하는 몰딩 공정을 수행하게 되며, 이에 따라 도 1과 같은 형태로 된다.After the wire bonding is completed, a molding process of molding the semiconductor chip 2 and the gold wire 3 into an epoxy molding compound (EMC) 15, which is an encapsulation resin, is performed. do.
이어, 몰딩이 완료된 다음에는 스크린 프린팅(Screen Printing)을 통해 회로기판(1) 저면에 일정 패턴의 솔더 페이스트(Solder paste)를 전사하여 플럭스(Flux)를 코팅시키는 플럭스 코팅(Flux Coating) 공정을 수행하게 된다.Subsequently, after molding is completed, a flux coating process of transferring a solder paste of a predetermined pattern onto the bottom of the circuit board 1 through screen printing to coat the flux is performed. Done.
또한, 플럭스 코팅 공정이 끝난 다음에는 회로기판(1) 저면에 일정 패턴으로 코팅된 플럭스에 솔더볼(5)을 부착시킨 다음, 열처리 공정인 리플로우(Reflow)를 수행하여 솔더볼(5)을 회로기판(1)에 견고히 고정시키게 된다.In addition, after the flux coating process, the solder ball 5 is attached to the flux coated on the bottom surface of the circuit board 1 in a predetermined pattern, and then the solder ball 5 is formed by performing a reflow process. It is fixed firmly in (1).
그 후, 솔더볼(5) 위치를 고려하여 단위 패키지 별로 절단하므로써 도 2에 나타낸 바와 같은 형태의 칩 어레이 타입 비·지·에이 패키지 단품을 완성하게 된다.Subsequently, the chip array type B, G, and A package of the form as shown in FIG. 2 is completed by cutting each unit package in consideration of the solder ball 5 position.
한편, 이와 같은 칩 어레이 타입 비·지·에이 패키지 제조 공정중, 와이어 본딩 공정 진행시에는 와이어 본딩 모니터링 시스템(이하, "WBMS"라고 한다.)에 의해 와이어의 단락여부가 검출된다.On the other hand, during such a chip array type B-A package manufacturing process, the wire bonding monitoring system (henceforth "WBMS") detects a short circuit of the wire at the time of a wire bonding process progressing.
참고적으로, WBMS에 대해 설명하면 다음과 같다.For reference, a description of WBMS is as follows.
WBMS는 본딩시 와이어의 단락 여부를 검출하는 기능으로 와이어 본딩되는 와이어로 반도체칩(2)에 손상을 주지 않을 정도의 전기적인 레벨인 약 0.75V(0.75Micro A)의 전기를 흘려 본딩패드(200)와 히터블록(heat block)(도시는 생략함) 사이의 저항이 요구수준 보다 큰 값으로 나타나면 단락으로 판단하고, 그것의 저항이 요구수준 이하로 나타나면 연결된 것으로 판단하므로써, 이에 대해 조치를 취하여 와이어 본딩 불량이 대량으로 발생하는 현상을 방지하는 것이다.WBMS is a function of detecting whether a wire is shorted during bonding. The WBMS is a wire-bonded wire, and flows electricity of about 0.75 V (0.75 Micro A), which is an electrical level that does not damage the semiconductor chip 2. ) And the heater block (not shown) if the resistance is greater than the required level is judged to be a short circuit, and if its resistance is below the required level, it is judged to be connected, so take action on this. This is to prevent a large amount of bad bonding.
즉, 제1본딩(즉, 볼 본딩)을 위해 캐필러리(capillary)가 와이어를 끌고 제일 위로 올라간 시점에서 와이어 클램프를 닫고 전류를 흘려 저항이 요구 수준 이상으로 높으면 제1본딩이 불량인 것으로 판단하고, 와이어 본딩 장비가 정지된다.That is, when the capillary drags the wire for the first bonding (ie, ball bonding) and closes the wire clamp at the point when the wire is raised to the top, and the current flows, the first bonding is determined to be bad. And the wire bonding equipment is stopped.
또한, 제2본딩(스티치 본딩)후 테일을 끊은 상태에서 전류를 흘려 저항이 요구수준 이하로 낮으면 테일이 끊어지지 않은 것으로 판단하고, 와이어 본딩 장비가 정지된다.In addition, if the resistance is lower than the required level by flowing a current while the tail is cut after the second bonding (stitch bonding), it is determined that the tail is not broken, and the wire bonding equipment is stopped.
한편, 와이어 스풀(wire spool)의 엔드 와이어(end wire)에서 히트블록까지가 WBMS의 작동 범위에 속하며, 와이어 본딩동작에서 WBMS의 역할을 살펴보면 WBMS 보드(도시는 생략함)가 제1본딩시 와이어 스풀의 엔드 와이어에 플러스(+) 전류를흐르게 하고, 히트블록에는 마이너스(-) 전류를 흐르게 하여 와이어 스풀의 엔드 와이어에 흐르는 플러스 전류가 와이어를 타고 반도체칩의 제1본딩된 지점을 통해 회로기판을 거쳐 히트블록까지 전달됨으로써 와이어의 저항이 작아지는 것을 WBMS 보드가 감지하여 와이어가 연결되어 있는 것을 알게 되는 것이다.On the other hand, from the end wire of the wire spool to the heat block belongs to the operation range of the WBMS, and the role of the WBMS in the wire bonding operation, the WBMS board (not shown) is the wire during the first bonding A positive current flows through the end wire of the spool and a negative current flows through the heat block so that a positive current flowing through the end wire of the wire spool rides through the wire and passes through the first bonded point of the semiconductor chip. The WBMS board detects that the resistance of the wire is reduced by being transmitted to the heat block, and the wire is connected.
한편, 제2본딩시에는 제1본딩시와 마찬가지 원리로 WBMS가 실행되며 캐필러리가 테일을 끊고 올라간 다음 전류를 흘려 저항이 크면 WBMS 보드(WBMS board)가 와이어가 끊어진 상태임을 검출하게 되는 것이다.On the other hand, in the second bonding, WBMS is executed on the same principle as in the first bonding, and the capillary breaks up the tail and then flows a current, and if the resistance is large, the WBMS board detects that the wire is broken.
그러므로, WBMS의 보드에는 플러스, 마이너스 전류의 두선이 연결되어 있으며, 또한 EFO 방전때는 순간적으로 와이어를 그라운드(ground) 상태로 만들어 볼을 형성한다.Therefore, two wires of positive and negative current are connected to the board of the WBMS, and during the EFO discharge, the wire is grounded instantaneously to form a ball.
여기서, 와이어 선이 장비와 결합되는 부분, 즉, 엔드 와이어(또는 와이어 스풀)과 와이어 스풀 홀더, 반도체칩과 회로기판 사이와, 회로기판과 히터블록 사이가, 도전(導電)가능한 상태여야만 WBMS는 정상적으로 작동될 수 있다.In this case, the WBMS must be connected to the equipment, that is, between the end wire (or wire spool) and the wire spool holder, between the semiconductor chip and the circuit board, and between the circuit board and the heater block. Can be operated normally.
그러나, 칩 어레이 타입 비·지·에이 패키지는 반도체칩과 회로기판 사이에 비도전성 에폭시가 접착제로서 개재되므로 인해 칩과 회로기판 사이의 전기적 연결이 불가능하여 제1번 와이어(3a)의 와이어 본딩 후에 제2번 와이어부터 WBMS를 적용하게 된다.However, in the chip array type B, G, and A packages, since the non-conductive epoxy is interposed between the semiconductor chip and the circuit board as an adhesive, electrical connection between the chip and the circuit board is impossible, so that after the wire bonding of the first wire 3a WBMS is applied from the second wire.
이에 따라, 종래에는 제1번 와이어(3a)에 대해서는 WBMS를 적용할 수 없어, 제1번 와이어의 단락 여부 검출이 불가능한 문제점이 있었다.Accordingly, in the related art, WBMS cannot be applied to the first wire 3a, and therefore, there is a problem that it is impossible to detect whether the first wire is shorted.
또한, 종래의 칩 어레이 타입 비·지·에이 패키지는 칩부착부에 다이 어태치를 위한 접착제 도포시, 접착제의 도포 면적 및 도포량 조절을 위한 기준이 없어 적정량의 도포가 곤란하여 과다 도포로 인해 에폭시가 핑거부까지 침범하게 되는 단점이 있었으며, 도포된 접착제의 두께 차로 인해 다이 틸트 현상이 발생하게 되는 등의 문제점이 있었다.In addition, the conventional chip array type B, G, A package does not have a standard for adjusting the coating area and coating amount of the adhesive when the adhesive is applied to the die attach portion, and thus it is difficult to apply an appropriate amount of epoxy. There was a disadvantage of invading the finger portion, and there was a problem such that a die tilt phenomenon occurred due to the difference in thickness of the applied adhesive.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 비·지·에이 패키지(BGA package ; Ball Grid Array package)의 구조 개선을 통해 제1번 와이어에도 와이어 본딩 모니터링 시스템의 적용이 가능하도록 하는 한편, 다이 어태치 공정을 위한 접착제 도포량의 조절이 용이하게 이루어지고 패키지의 열소산 능력이 향상되도록 하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, while the wire bonding monitoring system can be applied to the first wire by improving the structure of the ball grid array package (BGA package), The purpose is to facilitate the control of the amount of adhesive applied for the die attach process and to improve the heat dissipation capacity of the package.
도 1은 종래의 비·지·에이 패키지를 칩어레이 타입을 예로 들어 나타낸 것으로서, 몰딩후의 상태를 나타낸 평면도1 is a plan view showing a state after molding, showing a conventional B, G, A package as a chip array type as an example
도 2는 도 1의 칩 어레이 타입 비·지·에이 패키지의 구조를 보여주는 것으로서, 단위 패키지의 내부 구조를 보여주는 종단면도FIG. 2 is a cross-sectional view illustrating a structure of a chip array type BG-A package of FIG. 1 and illustrating an internal structure of a unit package.
도 3은 도 2의 Ⅰ-Ⅰ선을 따른 횡단면도3 is a cross-sectional view along the line I-I of FIG.
도 4는 본 발명에 따른 비·지·에이 패키지를 칩 어레이 타입을 예로 들어 나타낸 것으로서, 단위 패키지의 내부 구조를 보여주는 종단면도4 is a B, G, and A package according to the present invention using a chip array type as an example, a longitudinal cross-sectional view showing the internal structure of the unit package
도 5는 도 4의 Ⅱ-Ⅱ선을 따른 횡단면도5 is a cross-sectional view along the line II-II of FIG.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:회로기판 100:비어홀(via hole)1: Circuit board 100: Via hole
110:핑거부 2:반도체 칩110: finger 2: semiconductor chip
200:본딩패드 3a:제1번 와이어200: bonding pad 3a: first wire
3:와이어 4:접착제3: wire 4: adhesive
5:솔더볼 6:몰드바디5: Solder Ball 6: Molded Body
7:칩 커넥션 핀 8:윈도우7: Chip connection pin 8: Windows
상기한 목적을 달성하기 위한 본 발명은, 상면에 복수개의 핑거부가 구비되고 내부에는 상기 각 핑거부에 연결된 비어홀이 구비되는 회로기판과, 상기 회로기판 상면에 부착되는 반도체칩과, 상기 반도체칩과 회로기판 사이에 개재되는 비도전성 접착제와, 상기 회로기판의 반도체칩 부착 영역 내측에 위치하며 하단부가 상기 회로기판상의 비어홀에 연결되며 상단부가 칩 하면에 접촉하게 되는 칩 커넥션 핀과, 상기 반도체칩의 본딩패드와 상기 회로기판의 상부기층에 구비된 핑거부를 전기적으로 연결하는 전도성연결부재와, 상기 반도체칩의 본딩패드와 전도성연결부재 및 핑거부가 외부로부터 보호되도록 감싸는 몰드바디와, 상기 회로기판의 저면에 부착되는 솔더볼을 포함하여서 됨을 특징으로 하는 비·지·에이 패키지가 제공된다.The present invention for achieving the above object is a circuit board having a plurality of finger portion is provided on the upper surface and a via hole connected to each finger portion therein, a semiconductor chip attached to the upper surface of the circuit board, and A non-conductive adhesive interposed between the circuit board, a chip connection pin positioned inside the semiconductor chip attaching region of the circuit board, the lower end of which is connected to a via hole on the circuit board, and the upper end of which is in contact with the bottom surface of the chip; A conductive connecting member electrically connecting a bonding pad and a finger portion provided on the upper substrate of the circuit board, a mold body surrounding the bonding pad, the conductive connecting member and the finger portion of the semiconductor chip to be protected from the outside, and a bottom surface of the circuit board. A B, G, and A package is provided, including a solder ball attached to the.
이하, 본 발명의 각 실시예를 첨부도면 도 4 및 도 5를 참조하여 상세히 설명하면 다음과 같다.Hereinafter, each embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.
도 4는 본 발명에 따른 비·지·에이 패키지를 칩 어레이 타입을 예로 들어 나타낸 것으로서, 단위 패키지의 내부 구조를 보여주는 종단면도이고, 도 5는 도 4의 Ⅱ-Ⅱ선을 따른 횡단면도이다.4 is a vertical cross-sectional view illustrating an internal structure of a unit package as a non-G package according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line II-II of FIG. 4.
본 발명에 따른 칩 어레이 타입 비·지·에이 패키지는, 상면에 복수개의 핑거부(110)가 구비되고 내부에는 상기 각 핑거부(110)에 연결된 비어홀(100)(via hole)이 구비되는 회로기판(1)과, 상기 회로기판(1) 상면에 부착되는 반도체칩(2)과, 상기 반도체칩(2)과 회로기판(1) 사이에 개재되는 비도전성 접착제(4)(Non-conductive adhesive )와, 상기 회로기판(1)의 반도체칩(2) 부착 영역 내측에 위치하며 하단부가 상기 회로기판(1)상의 비어홀(100)에 연결되며 상단부가 칩 하면에 접촉하게 되는 칩 커넥션 핀(7)과, 상기 반도체칩(2)의 본딩패드(200)와 상기 회로기판(1)의 상부기층에 구비된 핑거부(110)를 전기적으로 연결하는 전도성연결부재와, 상기 반도체칩(2)의 본딩패드(200)와 전도성연결부재 및 핑거부(110)가 외부로부터 보호되도록 감싸는 몰드바디(6)와, 상기 회로기판(1)의 저면에 부착되는 솔더볼(5)을 포함하여 구성된다.In the chip array type B-A package according to the present invention, a plurality of finger parts 110 are provided on an upper surface thereof, and a via hole 100 connected to each of the finger parts 110 is provided therein. A non-conductive adhesive (4) interposed between the substrate (1), the semiconductor chip (2) attached to the upper surface of the circuit board (1), and the semiconductor chip (2) and the circuit board (1) ) And a chip connection pin 7 positioned inside the attachment region of the semiconductor chip 2 of the circuit board 1 and having a lower end connected to the via hole 100 on the circuit board 1 and having an upper end contacting the bottom surface of the chip. ), A conductive connection member for electrically connecting the bonding pad 200 of the semiconductor chip 2 and the finger part 110 provided on the upper substrate of the circuit board 1, and the semiconductor chip 2. A mold body 6 surrounding the bonding pad 200, the conductive connecting member, and the finger part 110 to be protected from the outside, and the circuit board 1. Is configured to include the solder ball (5) attached to the bottom surface.
이 때, 상기 칩 커넥션 핀(7)은 회로기판(1)의 제조시 상기 회로기판(1)의 칩 부착 영역 내측에 일체로 형성됨이 바람직하다.In this case, the chip connection pin 7 may be integrally formed inside the chip attachment region of the circuit board 1 when the circuit board 1 is manufactured.
이와 같이 구성된 본 발명의 칩 어레이 타입 비·지·에이 패키지의 제조 과정 및 작용은 다음과 같다.The manufacturing process and operation of the chip array type BG package of the present invention configured as described above are as follows.
먼저, 웨이퍼 상면에 집적회로를 형성하는 FAB(Fabrication) 공정이 끝난 상태에서 웨이퍼에 형성된 반도체칩(2)을 개별적으로 분리하기 위한 소잉(sawing)을 실시한다.First, sawing is performed to individually separate the semiconductor chips 2 formed on the wafer in a state where an FAB (fabrication) process for forming an integrated circuit on the upper surface of the wafer is completed.
그 다음, 내부에 회로패턴이 형성된 회로기판(1)이 공정에 투입됨에 따라 회로기판(1) 상면에 개별 윈도우(8)별로 접착제(4)를 도포하여 절단된 반도체칩(2)을 본딩시키게 된다.Then, as the circuit board 1 having the circuit pattern formed therein is introduced into the process, the adhesive 4 is applied to each window 8 on the upper surface of the circuit board 1 to bond the cut semiconductor chip 2. do.
이 때, 본 발명의 패키지는 회로기판(1)의 칩 부착 영역의 네 모서리 부분에 칩 커넥션 핀(7)이 접착제 라이팅 가이드(adhesive writing guide) 역할을 하게 되므로써, 회로기판(1)의 칩 부착 영역에 도포되는 접착제(4)의 양이 쉽게 조절된다.At this time, in the package of the present invention, the chip connection pin 7 acts as an adhesive writing guide on the four corners of the chip attaching region of the circuit board 1, whereby the chip attaching of the circuit board 1 is performed. The amount of adhesive 4 applied to the area is easily controlled.
즉, 상기 칩 커넥션 핀(7)의 높이를 기준으로 접착제(4) 도포 높이가 설정되므로 전체 도포 용적의 조절이 쉽게 이루어진다.That is, since the coating height of the adhesive 4 is set based on the height of the chip connection pin 7, the adjustment of the entire coating volume is easily performed.
또한, 상기에서 칩 커넥션 핀(7)의 위치는 다이 어태치 공정시, 다이 크랙을 방지하기 위해 픽업 툴의 위치와 동일한 위치에 둠이 바람직하다.In addition, the chip connection pin 7 is preferably positioned at the same position as that of the pickup tool in the die attach process to prevent die cracking.
즉, 칩 커넥션 핀(7)의 위치는 다이 어태치 공정에 이용되는 픽업 툴이 반도체칩과 접하는 영역을 다시 회로기판 상으로 투영했을 때의 해당 영역에 위치하도록 함으로써, 픽업 툴의 하강시 반도체칩(2)이 받게 되는 스트레스를 최소화하여 다이 크랙(die crack)을 효과적으로 방지할 수 있게 된다.That is, the position of the chip connection pin 7 is located in the region where the pick-up tool used in the die attach process is projected onto the circuit board again to project the region contacting the semiconductor chip onto the circuit board. By minimizing the stresses (2), die cracks can be effectively prevented.
한편, 상기한 바와 같이, 다이 어태치 공정이 끝난 후에는 반도체칩(2)에 형성된 본딩패드(200)와 회로기판(1)에 형성된 회로패턴의 핑거부(110)를골드와이어(3)를 이용하여 서로 전기적으로 연결시키는 와이어 본딩 공정을 수행하게 된다.On the other hand, as described above, after the die attach process is completed, the gold wire 3 may be connected to the bonding part 200 formed on the semiconductor chip 2 and the finger portion 110 of the circuit pattern formed on the circuit board 1. By using the wire bonding process to electrically connect to each other.
이 때, 종래와는 달리, 본 발명에 따른 칩 어레이 타입 비·지·에이 패키지에서는 반도체칩(2)의 저면이 칩 커넥션 핀(7)에 직접적으로 접하게 되므로 인해, 제1번 와이어(3a)에 대한 WBMS의 적용이 가능하게 된다.At this time, unlike the prior art, in the chip array type BG-A package according to the present invention, since the bottom surface of the semiconductor chip 2 is in direct contact with the chip connection pin 7, the first wire 3a is provided. Application of WBMS to is possible.
즉, WBMS가 적용되기 위해서는, 엔드 와이어(또는 와이어 스풀)과 와이어 스풀 홀더, 반도체 칩(2)과 회로기판(1) 사이가 도전(導電) 가능한 상태여야만 하는데, 본 발명에서는 반도체칩(2)과 회로기판(1) 사이가 칩 커넥션 핀(7)에 의해 도전(導電) 상태에 가깝게 된다.That is, in order for the WBMS to be applied, the end wire (or the wire spool) and the wire spool holder, the semiconductor chip 2 and the circuit board 1 must be in a conductive state. ) Between the circuit board 1 and the circuit board 1 close to the conductive state by the chip connection pin 7.
따라서, 본 발명의 칩 어레이 타입 비·지·에이 패키지는 반도체칩(2)과 회로기판(1) 사이가 칩 커넥션 핀(7)에 의해 거의 도전(導電) 상태에 가까우므로 인해, 종래와는 달리 저항값의 변화 검출이 가능하게 된다.Therefore, in the chip array type BG-A package of the present invention, since the semiconductor chip 2 and the circuit board 1 are almost in a conductive state by the chip connection pin 7, the chip array type B-G package is different from the conventional one. Alternatively, the change of the resistance value can be detected.
이에 따라, 본 발명에서는 제1본딩(즉, 볼 본딩) 수행을 위해 캐필러리(capillary)가 와이어를 끌고 제일 위로 올라간 시점에서 와이어 클램프를 닫고 전류를 흘려, 상기 반도체칩(2)과 회로기판(1) 사이의 저항이 요구 수준 이상의 큰 값으로 나타나면 단락으로 판단하고, 그것의 저항이 요구수준 이하로 나타나면 연결된 것으로 판단하여, 제1번 와이어(3a)의 단락 여부를 검출하게 된다.Accordingly, in the present invention, the capillary pulls the wire and closes the wire clamp and flows a current to perform the first bonding (that is, the ball bonding), and the current flows through the semiconductor chip 2 and the circuit board. If the resistance between (1) is greater than the required level, it is determined as a short circuit, and if its resistance is less than or equal to the required level, it is determined to be connected, and it is detected whether the first wire 3a is shorted.
한편, 본 발명의 경우, 제1번 와이어(3a)의 단락여부를 판단하는 저항값과 제2번 와이어 이후의 와이어들에 대한 단락여부를 판단하는 저항값은 다름이 물론이다.Meanwhile, in the present invention, the resistance value for determining whether the first wire 3a is short-circuited and the resistance value for determining whether a short circuit for the wires after the second wire are different are of course different.
요컨대, 종래의 칩 어레이 타입 비·지·에이 패키지는 반도체칩과 회로기판 사이에 개재되는 비도전성 접착제(4)로 인해 반도체칩과 회로기판 사이의 저항이 너무 커서 제1번 와이어의 단락여부 검출이 불가능하지만, 본 발명의 칩 어레이 비·지·에이 패키지는 비도전성 접착제(4) 도포영역 내에 위치한 칩 커넥션 핀(7)이 반도체칩(2)의 하면에 직접 접촉하므로 인해 반도체칩과 회로기판 사이의 저항이 비교적 작아 제1번 와이어(3a)의 단락여부 검출이 가능하게 된다.In short, the conventional chip array type B, G, and A packages detect a short circuit of the first wire due to the resistance between the semiconductor chip and the circuit board being too large due to the non-conductive adhesive 4 interposed between the semiconductor chip and the circuit board. Although this is impossible, the chip array B-A package of the present invention has a semiconductor chip and a circuit board because the chip connection pin 7 located in the non-conductive adhesive 4 application region is in direct contact with the bottom surface of the semiconductor chip 2. The resistance therebetween is relatively small, and the short circuit of the first wire 3a can be detected.
한편, 와이어 본딩이 완료된 후에는 반도체칩(2) 및 와이어(3)를 봉지수지로 몰딩하는 몰딩 공정을 수행하게 되고, 몰딩이 완료된 다음에는 플럭스 코팅(Flux Coating)을 수행하게 되며, 이어 회로기판(1) 저면에 솔더볼(5)을 부착시켜 열처리 공정인 리플로우(Reflow)를 수행함은 전술한 바와 동일하다.Meanwhile, after the wire bonding is completed, a molding process of molding the semiconductor chip 2 and the wire 3 into the encapsulation resin is performed, and after the molding is completed, flux coating is performed, followed by a circuit board. (1) The solder ball 5 is attached to the bottom surface to perform reflow, which is a heat treatment process, as described above.
상기에서 칩 커넥션 핀(7)은, 회로기판(1)의 제조시에 형성됨이 바람직하나, 경우에 따라 별도로 제작되어 패키징시 회로기판(1)에 접착제(4)가 도포되기 전에 칩 부착영역에 부착될 수도 있음은 물론이다.Although the chip connection pin 7 is preferably formed at the time of manufacturing the circuit board 1, it may be separately manufactured in some cases, before the adhesive 4 is applied to the circuit board 1 at the time of packaging. Of course, it may be attached.
한편, 상기의 실시예에서는 본 발명의 적용예를 칩 어레이 타입 비·지·에이 패키지로서 설명하였으나, 칩 어레이 타입 비·지·에이 패키지가 아닌 싱글 타입의 기존 비·지·에이 패키지에도 적용 가능함은 물론이다.On the other hand, in the above embodiment, the application example of the present invention has been described as a chip array type B / A package, but the present invention can also be applied to a single type existing B / G package rather than the chip array type B / A package. Of course.
이상에서와 같이, 본 발명은 비·지·에이 패키지(BGA package ; Ball Grid Array package)의 구조를 개선한 것이다.As mentioned above, this invention improves the structure of BGA package (BGA package; Ball Grid Array package).
이에 따라, 본 발명의 비·지·에이 패키지는 제1번 와이어에도 와이어 본딩모니터링 시스템의 적용이 가능하게 되며, 칩 부착을 위한 접착제 도포량의 조절이 용이하게 이루어질 수 있게 된다.Accordingly, the B, G and A package of the present invention can be applied to the wire bonding monitoring system to the first wire, it is possible to easily adjust the amount of adhesive coating for chip attachment.
뿐만 아니라, 본 발명은 반도체칩의 하면과 칩 커넥션 핀과의 직접적인 접촉에 의해 칩에서 발생하는 열을 상기 칩 커넥션 핀으로 전도된 후, 회로기판 및 솔더볼을 통해 외부로 방출시킬 수 있으므로 인해, 패키지의 방열(放熱) 성능 및 신뢰성 향상을 도모할 수 있게 된다.In addition, since the present invention conducts heat generated in the chip by direct contact between the lower surface of the semiconductor chip and the chip connection pin to the chip connection pin, and then to the outside through the circuit board and the solder ball, the package It is possible to improve the heat dissipation performance and reliability.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000066041A KR100351926B1 (en) | 2000-11-08 | 2000-11-08 | Ball Grid Array package |
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| KR1020000066041A KR100351926B1 (en) | 2000-11-08 | 2000-11-08 | Ball Grid Array package |
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| KR100351926B1 true KR100351926B1 (en) | 2002-09-12 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100649740B1 (en) | 2005-10-18 | 2006-11-27 | 삼성전기주식회사 | A semiconductor chip package having triangle fingers |
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| KR101346223B1 (en) * | 2012-01-09 | 2014-01-06 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method thereof |
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| JPH10209317A (en) * | 1997-01-16 | 1998-08-07 | Nec Corp | Semiconductor device |
| JPH1154658A (en) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | Semiconductor device, manufacture thereof and frame structure |
| KR19990059027A (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Chip Array Ball Array Semiconductor Package |
| KR19990059030A (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Ball Grid Array Semiconductor Package Using Flexible Circuit Board |
| JP2000174160A (en) * | 1998-12-03 | 2000-06-23 | Sanyo Electric Co Ltd | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1065039A (en) * | 1996-08-13 | 1998-03-06 | Sony Corp | Semiconductor device |
| JPH10209317A (en) * | 1997-01-16 | 1998-08-07 | Nec Corp | Semiconductor device |
| JPH1154658A (en) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | Semiconductor device, manufacture thereof and frame structure |
| KR19990059027A (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Chip Array Ball Array Semiconductor Package |
| KR19990059030A (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Ball Grid Array Semiconductor Package Using Flexible Circuit Board |
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| KR100649740B1 (en) | 2005-10-18 | 2006-11-27 | 삼성전기주식회사 | A semiconductor chip package having triangle fingers |
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