KR100649740B1 - A semiconductor chip package having triangle fingers - Google Patents

A semiconductor chip package having triangle fingers Download PDF

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Publication number
KR100649740B1
KR100649740B1 KR20050098324A KR20050098324A KR100649740B1 KR 100649740 B1 KR100649740 B1 KR 100649740B1 KR 20050098324 A KR20050098324 A KR 20050098324A KR 20050098324 A KR20050098324 A KR 20050098324A KR 100649740 B1 KR100649740 B1 KR 100649740B1
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South Korea
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semiconductor chip
finger
fingers
substrate
chip package
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KR20050098324A
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Korean (ko)
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정철호
김희선
송하윤
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor chip package is provided to reduce a package size and to secure the freedom degree of a substrate design by using a triangular finger structure. A semiconductor chip package includes at least one semiconductor chip(110), a substrate(120) on the semiconductor chip, and a metallic wire. The metallic wire(130) is used for connecting electrically a plurality of bonding pads of the semiconductor chip with a plurality of fingers(125) of the substrate. Each finger is formed like a triangle type structure, so that an optimum distance between the fingers is capable of being obtained from the triangle type structures without the interference of a peripheral portion.

Description

삼각형 핑거를 갖는 반도체 칩 패키지{A Semiconductor Chip Package Having Triangle Fingers}A semiconductor chip package having a triangle finger

도 1은 종래의 반도체 칩 패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor chip package.

도 2는 종래의 반도체칩 패키지를 도시한 평면도이다.2 is a plan view illustrating a conventional semiconductor chip package.

도 3은 본 발명에 따른 삼각형 핑거를 갖는 반도체 칩 패키지의 제1 실시예를 도시한 구성도이다.3 is a configuration diagram showing a first embodiment of a semiconductor chip package having a triangular finger according to the present invention.

도 4는 본 발명에 따른 삼각형 핑거를 갖는 반도체 칩 패키지의 제2 실시예를 도시한 평면도이다. 4 is a plan view showing a second embodiment of a semiconductor chip package having a triangular finger according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *     Explanation of symbols on the main parts of the drawings

110 : 반도체 칩 115 : 본딩패드110: semiconductor chip 115: bonding pad

120 : 기판 125 : 핑거120: substrate 125: finger

130 : 금속 와이어 G : 간격130: metal wire G: spacing

본 발명은 핑거간의 간격을 주변부의 간섭을 받지 않는 최소 제한 크기로 유지하면서 패키지의 사이즈를 줄일 수 있고, 기판의 설계 자유도를 확보할 수 있는 삼각형 핑거를 갖는 반도체 칩 패키지에 관한 것이다. The present invention relates to a semiconductor chip package having a triangular finger that can reduce the size of the package while maintaining the distance between the fingers to a minimum limit size that does not interfere with the peripheral portion, and can secure the design freedom of the substrate.

최근, 반도체칩 패키지의 소형화, 고용량화 및 다기능화에 대한 요구가 증가함에 따라 그 크기가 작아지고 그 핀의 개수가 증가하는 추세에 있으며, 이러한 반도체 패키지는 실장 및 리드의 형태에 따라 여러 가지 유형으로 구분되는데, 그 대표적인 예로는 DIP, SOP, SSOP, TSOP, SOJ, QFP, PLCC-Square, PLCC-Rectangular, BGA 및 BLP 등이 있다.In recent years, as the demand for miniaturization, high capacity, and multifunction of semiconductor chip packages increases, the size thereof decreases and the number of pins increases, and such semiconductor packages have various types depending on the type of mounting and leads. The representative examples are DIP, SOP, SSOP, TSOP, SOJ, QFP, PLCC-Square, PLCC-Rectangular, BGA and BLP.

도 1은 종래의 반도체 칩 패키지를 도시한 단면도이고, 도 2는 종래의 반도체칩 패키지를 도시한 평면도이다. 1 is a cross-sectional view showing a conventional semiconductor chip package, Figure 2 is a plan view showing a conventional semiconductor chip package.

종래 반도체 칩 패키지(10)는 도 1과 도 2에 도시한 바와 같이, 웨이퍼 소잉공정(Wafer Sawing Process)에 의해 웨이퍼로부터 개별화된 반도체 칩(11)을 기판(12)상에 와이어 본딩방식으로 탑재하여 패키징하였다.  As shown in FIGS. 1 and 2, the conventional semiconductor chip package 10 mounts a semiconductor chip 11 separated from a wafer by a wafer sawing process on a substrate 12 by wire bonding. Packaged.

즉, 상기 반도체 칩(11)은 복수개의 핑거(14)가 패턴인쇄된 기판(12)의 상부면에 다이 어태치 공정(Die Attach Process)에 의해 접착되고, 상기 반도체 칩(11)의 상부면에 형성된 복수개의 본딩패드(14)는 금속 와이어(13)를 매개로 하여 상기 핑거(14)와 전기적으로 연결되도록 와이어본딩된다. That is, the semiconductor chip 11 is adhered to the upper surface of the substrate 12 on which the plurality of fingers 14 are pattern printed by a die attach process, and the upper surface of the semiconductor chip 11. The plurality of bonding pads 14 formed at the wires may be wire-bonded to be electrically connected to the fingers 14 through the metal wires 13.

상기 기판(12)상에 와이어 본딩된 반도체 칩(11)과 금속 와이어(13)는 외부환경과 충격으로부터 보호하도록 수지재로 이루어진 몰드부(16)에 의해서 몰딩되어 패키징되는 것이다. The semiconductor chip 11 and the metal wire 13 wire-bonded on the substrate 12 are molded and packaged by a mold part 16 made of a resin material to protect it from external environment and impact.

도 1에서 미설명 부호 13은 솔더볼이다.In FIG. 1, reference numeral 13 denotes a solder ball.

이러한 반도체 칩 패키지(10)는 반도체 기술발전에 따라 전자부품의 사이즈가 상당히 중요한 요소로 작용하게 되고, 상기 반도체 칩(11)은 웨이퍼 처리기술의 개선으로 물리적인 크기가 계속적으로 감소되는 반면에, 상기 반도체 칩(11)의 본딩패드(14)는 기능의 다양화에 따라 그 형성갯수가 증가하는 추세이다. In the semiconductor chip package 10, the size of the electronic component is very important as the semiconductor technology develops, and the semiconductor chip 11 is continuously reduced in physical size due to the improvement of the wafer processing technology. Bonding pads 14 of the semiconductor chip 11 have a tendency to increase in number as the functions are diversified.

그리고, 상기 본딩패드(14)가 금속 와이어어(13)를 매개로 하여 와이어 본딩되는 핑거(15)들도 상기 금속 와이어(13)의 일단이 본딩연결되는 최저 제한 면적을 유지하면서 인접하는 핑거(15)간의 간격을 좁혀 패키지를 설계하였다. In addition, the fingers 15 to which the bonding pads 14 are wire-bonded through the metal wire 13 are also adjacent to each other while maintaining a minimum limit area where one end of the metal wire 13 is bonded. The package was designed by narrowing the spacing between the parts.

그러나, 반도체 칩(11)의 패키징시 상기 핑거(15)와 인접하는 다른 핑거(15)간의 간격(G)은 최소 제한 크기인 0.1 내지 0.2mm 로 유지하지 않으면, 동작시 주변부의 전류영향을 받아 반도체 칩(11)의 오동작을 유발시키기 때문에, 패키지의 사이즈를 소형화 설계하는데 한계가 있었다. However, when the semiconductor chip 11 is packaged, the distance G between the finger 15 and another adjacent finger 15 is not maintained at the minimum limit of 0.1 to 0.2 mm, and is affected by the current influence of the peripheral portion during operation. In order to cause malfunction of the semiconductor chip 11, there is a limit in designing a smaller package size.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해소하기 위하여 제안된 것으로써, 그 목적은 핑거간의 간격을 주변부의 간섭을 받지 않는 최소 제한 크기로 유지하면서 패키지의 사이즈를 줄일 수 있고, 기판의 설계 자유도를 확보할 수 있는 삼각형 핑거를 갖는 반도체 칩 패키지를 제공하고자 한다. Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, the object of which is to reduce the size of the package while maintaining the distance between the fingers to the minimum limit size that does not interfere with the peripheral portion, the design of the substrate An object of the present invention is to provide a semiconductor chip package having a triangular finger capable of securing degrees of freedom.

상기와 같은 목적을 달성하기 위한 기술적인 구성으로써, 본 발명은,As a technical configuration for achieving the above object, the present invention,

적어도 하나의 반도체 칩 ;At least one semiconductor chip;

상기 반도체 칩이 상부면에 탑재되는 기판 ;A substrate on which the semiconductor chip is mounted;

상기 반도체 칩에 형성된 복수개의 본딩패드와 상기 기판의 상부면에 형성된 복수개의 핑거사이를 전기적으로 연결하는 금속 와이어 ; 를 포함하고, A metal wire electrically connecting a plurality of bonding pads formed on the semiconductor chip and a plurality of fingers formed on an upper surface of the substrate; Including,

상기 핑거와 인접하는 핑거와의 사이에 핑거의 정렬선에 대하여 경사진 기울기를 갖는 최소 제한 크기의 간격를 유지하면서 상기 핑거의 중심과 인접하는 핑거의 중심간의 거리를 좁힐 수 있도록 상기 핑거를 삼각형으로 구비하는 삼각형 핑거를 갖는 반도체 칩 패키지를 제공한다. The finger is provided in a triangle so as to narrow the distance between the center of the finger and the center of the adjacent finger while maintaining a minimum limiting distance having an inclined slope with respect to the alignment line of the finger between the finger and the adjacent finger. A semiconductor chip package having a triangular finger is provided.

바람직하게, 상기 핑거는 정삼각형태로 구비된다. Preferably, the fingers are provided in an equilateral triangle shape.

바람직하게, 상기 핑거는 마름모형태로 구비된다. Preferably, the fingers are provided in a rhombus shape.

바람직하게, 상기 기판상에 형성되는 복수개의 핑거는 상기 핑거의 정렬선을 따라 정삼각형 핑거와 역삼각형 핑거가 교대로 배치된다. Preferably, in the plurality of fingers formed on the substrate, an equilateral triangle finger and an inverted triangle finger are alternately disposed along an alignment line of the finger.

이하, 본 발명에 대해서 첨부된 도면에 따라 보다 상세히 설명한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3는 본 발명에 따른 삼각형 핑거를 갖는 반도체 칩 패키지의 제1 실시예를 도시한 단면도이다. 3 is a cross-sectional view showing a first embodiment of a semiconductor chip package having a triangular finger according to the present invention.

본 발명의 반도체 칩 패키지(100)는 반도체 칩(110), 기판(120), 금속 와이 어(130), 본딩패드(110) 및 핑거(125)를 포함하여 구성된다. The semiconductor chip package 100 of the present invention includes a semiconductor chip 110, a substrate 120, a metal wire 130, a bonding pad 110, and a finger 125.

상가 반도체 칩(110)은 웨이퍼 소잉공정(Wafer Sawing Process)에 의해 웨이퍼로부터 개별화되는 적어도 하나의 칩 다이(chip Die)와 같은 적어도 하나의 칩부품이다. The additive semiconductor chip 110 is at least one chip component, such as at least one chip die, which is individualized from the wafer by a wafer sawing process.

이러한 반도체 칩(110)의 상부면에는 칩설계에 따라 신호, 파워 및 그라운드용으로 사용될 수 있는 본딩패드(115)를 복수개 구비한다. The upper surface of the semiconductor chip 110 is provided with a plurality of bonding pads 115 that can be used for signals, power and ground according to the chip design.

상기 기판(120)은 상기 반도체 칩(110)이 다이 어태치 공정(Die Attach Process)에 의해 탑재되고, 상기 반도체 칩(110)이 탑재되는 상부면에는 상기 본딩패드(115)와 일대일 대응되는 핑거(125)들이 인쇄되어 있다. The substrate 120 has the semiconductor chip 110 mounted by a die attach process, and a finger corresponding to the bonding pad 115 one-to-one on an upper surface on which the semiconductor chip 110 is mounted. 125 are printed.

이와 더불어, 상기 기판(120)의 상부면에는 구리와 같은 전도체를 소재로 하여 회로패턴(미도시)이 인쇄되어 있고, 그 상부면에는 상기 회로패턴을 보호하도록 솔더 마스크(미도시)를 형성하며, 상기 기판(120)의 하부면에는 또다른 기판과의 전기적인 연결을 위해서 솔더볼(미도시)을 구비한다. In addition, a circuit pattern (not shown) is printed on the upper surface of the substrate 120 using a conductor such as copper, and a solder mask (not shown) is formed on the upper surface of the substrate 120 to protect the circuit pattern. The lower surface of the substrate 120 is provided with a solder ball (not shown) for electrical connection with another substrate.

상기 금속 와이어(130)는 상기 반도체 칩(110)의 본딩패드(115)와 상기 기판(120)의 핑거(125)를 서로 전기적으로 연결시킬 수 있도록 상기 본딩패드(115)에 일단이 와이어 본딩기(미도시)로서 와이어본딩되고 상기 핑거(125)에 타단이 와이어본딩되는 금과 같은 도전성 금속소재이다. The metal wire 130 has a wire bonder at one end of the bonding pad 115 so as to electrically connect the bonding pad 115 of the semiconductor chip 110 and the finger 125 of the substrate 120 to each other. (Not shown) is a conductive metal material such as gold wire-bonded and wire-bonded to the finger 125 at the other end.

한편, 상기 금속 와이어(130)를 매개로 하여 상기 본딩패드(115)와 전기적으로 연결되는 핑거(125)는 그 중심과 인접하는 또다른 핑거(125)의 중심간의 거리를 좁혀 최소화할 수 있도록 삼각형태로 구비된다. Meanwhile, the finger 125 electrically connected to the bonding pad 115 through the metal wire 130 has a triangle so as to minimize the distance between the center of the finger 125 and the center of another finger 125 adjacent thereto. It is provided in the form.

이때, 상기 핑거(125)와 인접하는 또다른 핑거(125)와의 사이에 형성되는 간격(G)은 반도체 칩의 동작시 주변부의 전류영향을 받지 않도록 최소 제한 크기인 0.1 내지 0.2mm를 유지하면서 상기 핑거(125)의 정렬되는 정렬선에 대하여 일정각도로 경사진 기울기를 갖도록 구비된다. In this case, the gap G formed between the finger 125 and another adjacent finger 125 may be maintained at a minimum limit of 0.1 to 0.2 mm so as not to be influenced by a current of a peripheral portion during operation of the semiconductor chip. It is provided to have an inclination inclined at a predetermined angle with respect to the alignment line of the fingers 125.

여기서, 상기 핑거(125)는 각 꼭지점의 각도가 30°인 정삼각형태로 구비되는 것이 바람직하다. Here, the fingers 125 are preferably provided in the form of an equilateral triangle with an angle of 30 ° of each vertex.

상기 기판(120)상에 상기 본딩패드(115)와 일대일 대응되도록 일정간격을 두고 구비되는 복수개의 핑거(125)가 삼각형태로 구비되는 경우, 상기 핑거(125)들 중 어느 하나는 밑변이 상기 반도체 칩(110)과 대응하는 정삼각형태로 배치되고, 인접하는 다른 하나는 꼭지점이 상기 반도체 칩(110)가 대응하는 역삼각형태로 배치되는 배치구조를 갖는 것이 바람직하다. When a plurality of fingers 125 are provided in a triangular shape at regular intervals so as to correspond one-to-one with the bonding pad 115 on the substrate 120, any one of the fingers 125 may have a bottom side. It is preferable that the semiconductor chip 110 is arranged in a corresponding triangular shape, and the other one adjacent to the semiconductor chip 110 has an arrangement structure in which a vertex is arranged in a corresponding inverted triangle shape.

이에 따라, 상기 기판(120)상에 구비되는 복수개의 핑거(125)는 상기 핑거의 정렬선을 따라 최소 제한 크기의 간격을 형성하도록 정삼각형 핑거와 역삼각형 핑거가 교대로 배치된다.Accordingly, in the plurality of fingers 125 provided on the substrate 120, an equilateral triangle finger and an inverted triangle finger are alternately disposed to form a gap having a minimum limit size along the alignment lines of the fingers.

이러한 경우, 삼각형태의 핑거(125)들은 측방에서 바라볼때 서로 중첩되고, 삼각형 핑거의 중심과 또다른 삼각형 핑거의 중심간의 거리는 원형, 타원 또는 사각형태를 갖는 핑거의 중심간의 거리보다 짧게 구비되기 때문에, 상기 반도체 칩(110)의 변을 따라서 상기 기판(120)의 상부면에 구비되는 핑거(125)의 전체 정렬폭을 줄일 수 있는 한편, 상기 본딩패드(115)의 설치갯수 확대시 이에 맞추어 핑거(125)의 형성갯수를 증대시킬 수 있는 기판의 설계변경이 가능해지는 것이다.In this case, the triangular fingers 125 overlap each other when viewed from the side, and the distance between the center of the triangular finger and the center of another triangular finger is provided to be shorter than the distance between the centers of the fingers having a circular, ellipse or square shape. The total alignment width of the fingers 125 provided on the upper surface of the substrate 120 along the sides of the semiconductor chip 110 may be reduced, and the fingers may be adjusted accordingly when the number of installation of the bonding pads 115 is increased. It is possible to change the design of the substrate which can increase the number of formation of the 125.

그리고, 상기 본딩패드(115)와 핑거(125)사이를 본딩연결하는 금속 와이어(130)는 와이어 본딩시 가상의 수직축(Y)에 대하여 45°이하의 본딩각도로 연결되는 것이 바람직하다. In addition, the metal wires 130 for bonding between the bonding pads 115 and the fingers 125 may be connected at a bonding angle of 45 ° or less with respect to the virtual vertical axis Y at the time of wire bonding.

한편, 도 4는 본 발명에 따른 삼각형 핑거를 갖는 반도체 칩 패키지의 제2 실시예를 도시한 평면도로서, 본 발명의 반도체 칩 패키지(100a)에 구비되는 핑거(125a)는 도시한 바와 같이, 마름모형태로 구비되고, 마름모형 핑거(125a)와 인접하는 또다른 핑거(125a)는 이들 사이의 간격이 핑거의 정렬선에 대하여 기울어진 기울기를 갖도록 배치되어야 한다. 4 is a plan view showing a second embodiment of a semiconductor chip package having a triangular finger according to the present invention, wherein the finger 125a provided in the semiconductor chip package 100a of the present invention is a rhombus, as shown. The other finger 125a, which is provided in the form and is adjacent to the rhombic finger 125a, should be arranged such that the gap therebetween has an inclined slope with respect to the alignment lines of the fingers.

본 발명은 특정한 실시예에 관련하여 도시하고 설명하였지만, 이하의 청구범위에 의해 마련되는 본 발명의 정신이나 분야를 벗어나지 않는 한도내에서 본 발명이 다양하게 개조 및 변화될수 있다는 것을 당업계에서 통상의 지식을 가진자는 용이하게 알 수 있음을 밝혀두고자 한다. While the invention has been shown and described with respect to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit or scope of the invention as set forth in the claims below. I would like to know that the knowledgeable person can easily know.

상술한 바와같은 본 발명에 의하면, 반도체 칩의 본딩패드와 금속 와이어를 매개로 하여 와이어 본딩되도록 기판상에 구비되는 핑거를 삼각형태로 구비함으로서, 핑거와 인접하는 핑거간의 간격을 기울기 형태로 형성하면서 핑거의 중심와 인접하는 다른 핑거의 중심간의 거리를 좁힐 수 있기 때문에, 종래 원형, 타원형 또는 사각형 핑거에 비하여 기판상에 형성되는 정렬폭을 줄여 패키지의 소형화를 도모할 수 있는 한편, 제한된 면적을 갖는 기판상에서 형성되는 갯수를 늘려 기판의 설계자유도를 높일 수 있는 효과가 얻어진다. According to the present invention as described above, by providing the fingers provided on the substrate in a triangular form so as to wire bond through the bonding pad and the metal wire of the semiconductor chip, while forming the interval between the fingers and the adjacent fingers in the form of a slope. Since the distance between the center of the finger and the center of another adjacent finger can be narrowed, the size of the package can be reduced by reducing the alignment width formed on the substrate as compared with the conventional circular, elliptical or square fingers, and the substrate having a limited area By increasing the number of the formed phases, the effect of increasing the design freedom of the substrate is obtained.

Claims (4)

적어도 하나의 반도체 칩 ;At least one semiconductor chip; 상기 반도체 칩이 상부면에 탑재되는 기판 ;A substrate on which the semiconductor chip is mounted; 상기 반도체 칩에 형성된 복수개의 본딩패드와 상기 기판의 상부면에 형성된 복수개의 핑거사이를 전기적으로 연결하는 금속 와이어 ; 를 포함하고, A metal wire electrically connecting a plurality of bonding pads formed on the semiconductor chip and a plurality of fingers formed on an upper surface of the substrate; Including, 상기 핑거와 인접하는 핑거와의 사이에 핑거의 정렬선에 대하여 경사진 기울기를 갖는 최소 제한 크기의 간격를 유지하면서 상기 핑거의 중심과 인접하는 핑거의 중심간의 거리를 좁힐 수 있도록 상기 핑거를 삼각형으로 구비하는 삼각형 핑거를 갖는 반도체 칩 패키지. The finger is provided in a triangle so as to narrow the distance between the center of the finger and the center of the adjacent finger while maintaining a minimum limiting distance having an inclined slope with respect to the alignment line of the finger between the finger and the adjacent finger. A semiconductor chip package having a triangular finger. 제1항에 있어서,The method of claim 1, 상기 핑거는 정삼각형태로 구비됨을 특징으로 하는 삼각형 핑거를 갖는 반도체 칩 패키지. The finger chip is a semiconductor chip package having a triangular finger, characterized in that provided in the form of an equilateral triangle. 제1항에 있어서,The method of claim 1, 상기 핑거는 마름모형태로 구비됨을 특징으로 하는 삼각형 핑거를 갖는 반도체 칩 패키지. The semiconductor chip package having a triangular finger, characterized in that the finger is provided in a rhombus shape. 제1항에 있어서,The method of claim 1, 상기 기판상에 형성되는 복수개의 핑거는 상기 핑거의 정렬선을 따라 정삼각형 핑거와 역삼각형 핑거가 교대로 배치됨을 특징으로 하는 삼각형 핑거를 갖는 반도체 칩 패키지. The plurality of fingers formed on the substrate is a semiconductor chip package having a triangular finger, characterized in that the regular triangle fingers and the inverted triangle fingers are alternately arranged along the alignment line of the finger.
KR20050098324A 2005-10-18 2005-10-18 A semiconductor chip package having triangle fingers KR100649740B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293909B1 (en) 1998-09-16 2001-07-12 마이클 디. 오브라이언 How to prevent shorting of wires connected between bonding pads and lead fingers
KR100351926B1 (en) 2000-11-08 2002-09-12 앰코 테크놀로지 코리아 주식회사 Ball Grid Array package
KR20030007214A (en) * 2001-07-16 2003-01-23 닛본 덴기 가부시끼가이샤 Semiconductor device and wire bonding method therefor
KR20050023442A (en) * 2002-07-26 2005-03-09 콸콤 인코포레이티드 Method for accommodating small minimum die in wire bonded area array packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100293909B1 (en) 1998-09-16 2001-07-12 마이클 디. 오브라이언 How to prevent shorting of wires connected between bonding pads and lead fingers
KR100351926B1 (en) 2000-11-08 2002-09-12 앰코 테크놀로지 코리아 주식회사 Ball Grid Array package
KR20030007214A (en) * 2001-07-16 2003-01-23 닛본 덴기 가부시끼가이샤 Semiconductor device and wire bonding method therefor
KR20050023442A (en) * 2002-07-26 2005-03-09 콸콤 인코포레이티드 Method for accommodating small minimum die in wire bonded area array packages

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