KR200169583Y1 - Ball grid array package - Google Patents
Ball grid array package Download PDFInfo
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- KR200169583Y1 KR200169583Y1 KR2019970032508U KR19970032508U KR200169583Y1 KR 200169583 Y1 KR200169583 Y1 KR 200169583Y1 KR 2019970032508 U KR2019970032508 U KR 2019970032508U KR 19970032508 U KR19970032508 U KR 19970032508U KR 200169583 Y1 KR200169583 Y1 KR 200169583Y1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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Abstract
본 고안은 볼 그리드 어레이 패키지에 관한 것으로 칩 사이즈에 구애받지 않고 범용으로 사용할 수 있도록하여 칩 사이즈가 바뀔 때마다 바뀐 칩에 맞는 금속배선을 갖는 기판을 새로 개발하지 않아도 되도록 하므로써, 제조비용을 절감하고 생산성을 향상시킬 수 있도록 한 것이다.The present invention relates to a ball grid array package, which can be used universally regardless of the chip size, thereby reducing manufacturing costs by eliminating the need to newly develop a substrate having a metal wiring for the changed chip every time the chip size is changed. It is to improve productivity.
이를 위해, 본 고안은 내부에 회로가 형성되고 상면에는 금속 배선(1)이 패터닝된 기판(2)과, 상기 기판(2) 상면에 부착되는 다이패드(3)와, 상기 다이패드(3) 상면에 부착되며 상기 기판(2) 상면에 패터닝된 양측 배선(1) 사이의 폭 내에 위치하는 사이즈 또는 양측 배선(1) 사이의 폭을 벗어나 절연테이프(6)에 가장자리면이 안착되는 사이즈의 칩(4)과, 상기 기판(2)과 다이패드(3) 사이 및, 다이패드(3)와 칩(4) 사이에 개재되어 다이패드(3) 및 칩(4)을 각각 고정시키는 접착제(5)와, 상기 기판(2)에 패터닝된 금속 배선(1)의 내측 선단 상면에 부착되며 상기 다이패드(3)에 도포된 접착제(5)와 동일평면을 이루는 두께를 갖는 절연테이프(6)와, 상기 칩(4)의 본딩패드(4a)와 기판(2) 상면에 형성된 금속 배선(1)을 전기적으로 연결하는 금속세선(7)과, 상기 칩(4)과 기판(2)상의 배선(1) 및 금속세선(7)을 봉지하는 몰딩부재(8)를 구비한 것을 특징으로 하는 볼 그리드 어레이 패키지가 제공된다.To this end, according to the present invention, a circuit is formed therein and a substrate 2 having a metal wiring 1 patterned thereon, a die pad 3 attached to an upper surface of the substrate 2, and the die pad 3. A chip attached to an upper surface and having a size that is within a width between the two wirings 1 patterned on the upper surface of the substrate 2 or a size where an edge surface is seated on the insulating tape 6 beyond the width between the two wirings 1. (4) and an adhesive (5) interposed between the substrate (2) and the die pad (3) and between the die pad (3) and the chip (4) to fix the die pad (3) and the chip (4), respectively. And an insulating tape 6 attached to the upper surface of the inner end of the metal wire 1 patterned on the substrate 2 and having a thickness coplanar with the adhesive 5 applied to the die pad 3. A thin metal wire 7 electrically connecting the bonding pad 4a of the chip 4 and the metal wire 1 formed on the upper surface of the substrate 2, and on the chip 4 and the substrate 2. The ball grid array package to the wiring 1 and the thin metal wire (7) having a molding element (8) for sealing according to claim is provided.
Description
본 고안은 볼 그리드 어레이 패키지에 관한 것으로서, 더욱 상세하게는 칩 사이즈에 구애받지 않고 범용으로 사용할 수 있는 볼 그리드 어레이 패키지에 관한 것이다.The present invention relates to a ball grid array package, and more particularly, to a ball grid array package that can be used universally regardless of chip size.
일반적으로, 볼 그리드 어레이 패키지(BGA package ; Ball Grid Array package)는 도 1에 나타낸 바와 같이 기판(2)의 이면에 구형의 솔더볼(9)을 소정의 상태로 배열(Array)하여 아우터 리드(outer lead) 대신으로 사용하게 되며, 상기 볼 그리드 어레이 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다.In general, a ball grid array package (BGA package) has an outer lead by arranging a spherical solder ball 9 in a predetermined state on a rear surface of the substrate 2 as shown in FIG. 1. The ball grid array package may have a smaller package body area than a QFP (Quad Flat Package) type, and unlike the QFP, there is no lead deformation.
한편, 상기 볼 그리드 어레이 패키지 제작을 위한 패키지 공정은 개략 다음과 같은 순서로 진행된다.On the other hand, the package process for manufacturing the ball grid array package proceeds in the following order.
먼저, 웨이퍼 상면에 집적회로를 형성하는 FAB(Fabrication)공정이 끝난 상태에서 웨이퍼에 형성된 칩(4)을 개별적으로 분리하기 위한 소잉(sawing)을 실시한다.First, sawing is performed to individually separate the chips 4 formed on the wafer in the state where the FAB (Fabrication) process for forming the integrated circuit on the upper surface of the wafer is completed.
그 다음, 내부에 회로가 형성된 기판(2)이 공정에 투입됨에 따라 기판(2) 상면에 접착제(5)를 도포하여 절단된 칩(4)을 본딩시키게 되며, 칩(4) 본딩이 끝난 후에는 칩(4)에 형성된 본딩패드(4a)와 기판(2) 상면에 형성된 소정의 금속 배선(1) 사이를 금속세선(7)을 이용하여 서로 전기적으로 연결시키는 와이어 본딩을 실시하게 된다.Then, as the substrate 2 having a circuit formed therein is introduced into the process, an adhesive 5 is applied to the upper surface of the substrate 2 to bond the cut chips 4, and after the bonding of the chips 4 is completed. The wire bonding is performed to electrically connect the bonding pads 4a formed on the chip 4 and the predetermined metal wires 1 formed on the upper surface of the substrate 2 to each other using the metal thin wires 7.
그리고, 와이어 본딩이 완료된 후에는 칩(4) 및 금속세선(7)을 EMC(Epoxy Molding Compound)로 봉지하는 몰딩 공정을 수행하게 되며, 몰딩이 완료된 다음에는 스크린 프린팅(Screen Printing)을 통해 기판(2) 저면에 일정 패턴의 솔더 페이스트(Solder paste)를 전사하여 플럭스(Flux)를 코팅시키는 플럭스 코팅(Flux Coating) 공정을 수행하게 된다.After the wire bonding is completed, a molding process of encapsulating the chip 4 and the fine metal wire 7 with an EMC (Epoxy Molding Compound) is performed. After the molding is completed, the substrate may be formed through screen printing. 2) Flux coating process is performed to transfer the flux paste to the bottom surface to coat the flux.
또한, 플럭스 코팅 공정이 끝난 다음에는 기판(2) 저면에 일정 패턴으로 코팅된 플럭스에 솔더볼(9)을 부착시킨 다음, 열처리 공정인 리플로우(Reflow)를 수행하여 솔더볼(9)을 기판(2)에 견고히 고정시키게 된다.In addition, after the flux coating process is completed, the solder balls 9 are attached to the flux coated in a predetermined pattern on the bottom surface of the substrate 2, and then the solder balls 9 are formed by performing a reflow process. It is fixed firmly).
그 후, 클리닝 및 마킹 공정을 거쳐 완제품인 볼 그리드 어레이 패키지를 출하하게 된다.After that, we ship the finished ball grid array package through a cleaning and marking process.
이와 같이 제조된 볼 그리드 어레이 패키지는 칩(4)의 전기적 특성을 기판(2) 상면의 금속배선(1) 및 기판(2)의 내부회로를 통해 패키지 하부의 솔더볼(9)로 전달하여 상기 패키지가 실장된 메인보드(도시는 생략함)에 전달할 수 있게 된다.In the ball grid array package manufactured as described above, the electrical characteristics of the chip 4 are transferred to the solder balls 9 under the package through the metal wiring 1 on the upper surface of the substrate 2 and the internal circuits of the substrate 2. It can be delivered to the mounted motherboard (not shown).
그러나, 이와 같은 종래의 볼 그리드 어레이 패키지는 도 1에 나타낸 바와 같이 기판(2) 양측 배선(1) 사이의 폭(W)이 일정하여, 칩(4) 사이즈만 커지고 금속 배선(1)이 패터닝된 기판(2) 사이즈가 변경되지 않을 경우, 양측 금속배선(1)과 칩(4)이 접촉되게 된다.However, in this conventional ball grid array package, as shown in FIG. 1, the width W between the wirings 2 on both sides of the substrate 2 is constant, so that only the size of the chip 4 is increased and the metal wirings 1 are patterned. If the size of the substrate 2 is not changed, the metal wirings 1 and the chip 4 are brought into contact with each other.
따라서, 칩(4) 사이즈가 커질 경우, 기존의 칩(4)사이즈에 적용되던 배선(1)을 갖는 기판(2)을 더 이상 사용하지 못하고, 새로운 기판(2)을 신규 개발해야 하므로 인해, 비용이 발생하게 되며, 시간 제약이 발생하게 되는 문제점이 있었다.Therefore, when the size of the chip 4 increases, the board 2 having the wiring 1 applied to the existing chip 4 size can no longer be used, and a new board 2 must be newly developed. There is a problem that the cost occurs, the time constraints occur.
또한, 생산 프로세스 내에서 기판(2)의 변경시마다 해당 툴(tool)이 교체되어 생산성의 저하를 야기하게 되는 문제점이 있었다.In addition, there is a problem that the tool is replaced every time the substrate 2 is changed in the production process, causing a decrease in productivity.
본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 볼 그리드 어레이 패키지에 관한 것으로 칩 사이즈에 구애받지 않고 범용으로 사용할 수 있도록하여 칩 사이즈가 바뀔 때마다 바뀐 칩에 맞는 배선을 갖는 기판을 새로 개발하지 않아도 되도록 하므로써, 제조비용을 절감하는 한편 생산성을 향상시킬 수 있도록 한 볼 그리드 어레이 패키지를 제공하는데 그 목적이 있다.The present invention is to solve the above problems, and relates to a ball grid array package, so that it can be used for general purpose regardless of the chip size does not newly develop a board having a wiring for the changed chip each time the chip size is changed. Its purpose is to provide a ball grid array package that can reduce manufacturing costs and improve productivity.
도 1은 종래의 플라스틱 볼 그리드 어레이 패키지를 나타낸 종단면도Figure 1 is a longitudinal cross-sectional view showing a conventional plastic ball grid array package
도 2는 본 고안의 일실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩 사이즈가 작은 경우2 is a longitudinal sectional view showing a ball grid array package according to an embodiment of the present invention, the chip size is small
도 3은 본 고안의 일실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩 사이즈가 큰 경우3 is a longitudinal sectional view showing a ball grid array package according to an embodiment of the present invention, the chip size is large
도 4는 본 고안의 다른 실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩 사이즈가 작은 경우Figure 4 is a longitudinal cross-sectional view showing a ball grid array package according to another embodiment of the present invention, the chip size is small
도 5는 본 고안의 다른 실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩 사이즈가 큰 경우5 is a longitudinal sectional view showing a ball grid array package according to another embodiment of the present invention, in the case where the chip size is large
도 6은 도 2 및 도 3에 나타낸 볼 그리드 어레이 패키지에 적용된 리드프레임을 나타낸 단면도6 is a cross-sectional view showing a lead frame applied to the ball grid array package shown in FIG. 2 and FIG.
도 7은 도 4 및 도 5에 나타낸 볼 그리드 어레이 패키지에 적용된 리드프레임을 나타낸 단면도FIG. 7 is a cross-sectional view illustrating a lead frame applied to the ball grid array package shown in FIGS. 4 and 5.
도 8은 도 6의 절연테이프를 나타낸 확대 단면도8 is an enlarged cross-sectional view illustrating the insulating tape of FIG. 6.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
1:배선 2, 2a:기판1: wiring 2, 2a: substrate
3:다이패드 4:칩3: diepad 4: chip
4a:본딩패드 5:접착제4a: Bonding pad 5: Adhesive
6:절연테이프 6a:접착제층6: insulating tape 6a: adhesive layer
6b:절연필름층 7:금속세선6b: insulating film layer 7: thin metal wire
8:몰딩부재 9:솔더볼8: Molding member 9: Solder ball
10:돌출부10: protrusion
상기한 목적을 달성하기 위해, 본 고안은 내부에 회로가 형성되고 상면에는 금속 배선이 패터닝된 기판과, 상기 기판 상면에 부착되는 다이패드와, 상기 다이패드 상면에 부착되며 상기 기판 상면에 패터닝된 양측 배선 사이의 폭 내에 위치하는 사이즈 또는 양측 배선 사이의 폭을 벗어나 절연테이프에 가장자리면이 안착되는 사이즈의 칩과, 상기 다이패드 상면에 부착되며 상기 기판 상면에 패터닝된 양측 배선 사이의 폭 내에 위치하는 사이즈의 칩과, 상기 기판과 다이패드 사이 및, 다이패드와 칩 사이에 개재되어 다이패드 및 칩을 각각 고정시키는 접착제와, 상기 기판에 패터닝된 금속 배선의 내측 선단 상면에 부착되며 상기 다이패드에 도포된 접착제와 동일평면을 이루는 두께를 갖는 절연테이프와, 상기 칩의 본딩패드와 기판 상면에 형성된 금속 배선을 전기적으로 연결하는 금속세선과, 상기 칩과 기판 상의 배선 및 금속세선을 봉지하는 몰딩부재를 구비한 것을 특징으로 하는 볼 그리드 어레이 패키지가 제공된다.In order to achieve the above object, the present invention is a circuit is formed therein and a metal wiring patterned on the upper surface, a die pad attached to the upper surface of the substrate, the die pad is attached to the upper surface and patterned on the substrate Located within the width between the chip located in the width between the two wires or the size between the two wires and the size of the edge seated on the insulating tape, and the two wires attached to the upper surface of the die pad and patterned on the upper surface of the substrate. A chip having a size to be attached, an adhesive interposed between the substrate and the die pad, and between the die pad and the chip to fix the die pad and the chip, and attached to an upper surface of the inner end of the metal wiring patterned to the substrate. An insulating tape having a thickness coplanar with the adhesive applied to the adhesive, and formed on the bonding pad of the chip and the upper surface of the substrate. The ball grid array package comprising the thin metal wire electrically connecting the wiring and in, the molding element to the sealing wire and a metal thin wire on the chip and substrate.
상기한 목적을 달성하기 위한 본 고안의 다른 형태에 따르면, 내부에 회로가 형성되고 상면에는 금속 배선이 패터닝되며 상면 중앙부에는 돌출부가 형성된 기판과, 상기 기판의 돌출부 상면에 부착되며 상기 기판 상면에 패터닝된 양측 배선 사이의 폭 내에 위치하는 사이즈 또는 양측 배선 사이의 폭을 벗어나 절연테이프에 가장자리면이 안착되는 사이즈의 칩과, 상기 기판과 칩 사이에 개재되어 칩을 고정시키는 접착제와, 상기 기판에 패터닝된 금속 배선의 내측 선단 상면에 부착되며 상기 기판의 돌출부에 도포된 접착제와 동일평면을 이루는 두께를 갖는 절연테이프와, 상기 칩의 본딩패드와 기판 상면에 형성된 배선을 전기적으로 연결하는 금속세선과, 상기 칩과 기판상의 배선 및 금속세선을 봉지하는 몰딩부재를 구비한 것을 특징으로 하는 볼 그리드 어레이 패키지가 제공된다.According to another aspect of the present invention for achieving the above object, a circuit is formed therein, a metal wiring is patterned on the upper surface and a substrate having a protrusion formed on the center of the upper surface, attached to the upper surface of the protrusion of the substrate and patterned on the substrate A chip having a size positioned within a width between the two wirings or a width between the two wirings and a size of which an edge surface is seated on an insulating tape, an adhesive interposed between the substrate and the chip to fix the chip, and patterning the substrate An insulating tape attached to an upper end surface of the inner metal wire and having a thickness coplanar with an adhesive applied to the protrusion of the substrate, a metal wire for electrically connecting the bonding pad of the chip and the wire formed on the upper surface of the chip; And a molding member for encapsulating the wiring and the metal thin wire on the chip and the substrate. Grid array packages are provided.
이하, 본 고안의 실시예들을 첨부도면 도 2 내지 도 8을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 8.
도 2 는 본 고안의 일실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩 사이즈가 작은 경우이다.2 is a longitudinal sectional view showing a ball grid array package according to an embodiment of the present invention, in which the chip size is small.
이 경우, 본 고안은 내부에 회로가 형성되고 상면에는 배선(1)이 패터닝된 기판(2) 상면에 다이패드(3)가 부착되고, 상기 다이패드(3) 상면에는 상기 기판(2) 상면에 패터닝된 양측 배선(1) 사이의 폭(W) 내에 위치하는 사이즈의 칩(4)이 부착된다.In this case, the present invention has a circuit formed therein and a die pad 3 is attached to the upper surface of the substrate 2 on which the wiring 1 is patterned, and an upper surface of the substrate 2 on the upper surface of the die pad 3. The chip 4 of the size located in the width W between the patterned both wirings 1 is attached to it.
또한, 상기 기판(2)과 다이패드(3) 사이 및, 다이패드(3)와 칩(4) 사이에는 다이패드(3)를 기판(2)에 고정시키는 한편, 상기 칩(4)을 다이패드(3)에 고정시키는 접착제(5)가 각각 개재(介在)된다.In addition, the die pad 3 is fixed to the substrate 2 between the substrate 2 and the die pad 3 and between the die pad 3 and the chip 4, while the die 4 is fixed to the die 2. The adhesives 5 fixed to the pads 3 are respectively interposed.
그리고, 상기 기판(2)에 패터닝된 금속 배선(1)의 내측 선단 상면에는 상기 다이패드(3)에 도포된 접착제(5)와 동일평면을 이루는 두께를 갖는 절연테이프(6)가 부착되며, 상기 칩(4)의 본딩패드(4a)와 기판(2) 상면에 형성된 배선(1)은 이들을 연결하는 금속세선(7)에 의해 전기적으로 연결되며, 상기 칩(4)과 기판(2)상의 배선(1) 및 금속세선(7)은 몰딩부재(8)인 에폭시 몰딩 콤파운드에 의해 봉지(encapsulation)되어 구성된다.An insulating tape 6 having a thickness coplanar with the adhesive 5 applied to the die pad 3 is attached to the upper surface of the inner end of the metal wire 1 patterned on the substrate 2. The bonding pads 4a of the chip 4 and the wirings 1 formed on the upper surface of the substrate 2 are electrically connected to each other by metal thin wires 7 connecting them. The wiring 1 and the metal fine wire 7 are encapsulated by the epoxy molding compound which is the molding member 8, and are comprised.
또한, 도 3은 칩 사이즈가 큰 경우로서, 상기한 볼 그리드 어레이 패키지의 구성중 나머지 부분은 동일하나, 다이패드(3)에 부착되는 칩(4)의 사이즈가 칩(4)의 가장자리면이 상기 기판(2)의 양측 배선(1)에 부착된 절연테이프(6) 상면에 안착되는 사이즈 이상이 되도록 구성된다.3 is a case where the chip size is large, the remaining parts of the ball grid array package described above are the same, but the size of the chip 4 attached to the die pad 3 is the edge of the chip 4. It is comprised so that it may become more than the size seated on the upper surface of the insulating tape 6 attached to the both wiring 1 of the said board | substrate 2.
한편, 도 8은 본 고안의 절연테이프를 나타낸 확대 단면도로서, 절연테이프(6)는 상기 기판(2)의 패턴에 부착되는 접착제층(6a)과, 상기 접착제층(6a) 상면에 부착되는 절연필름층(6b)으로 이루어지게 된다.On the other hand, Figure 8 is an enlarged cross-sectional view showing the insulating tape of the present invention, the insulating tape 6 is an adhesive layer 6a adhered to the pattern of the substrate 2, and the insulation adhered to the upper surface of the adhesive layer 6a It is made of a film layer 6b.
이와 같이 구성된 본 고안의 실시예의 작용은 다음과 같다.The operation of the embodiment of the present invention configured as described above is as follows.
전술한 구성을 갖는 본 고안의 볼 그리드 어레이 패키지는 도 6에 나타낸 바와 같은 단면 구조를 갖는 기판(2) 상에 반도체 칩(4)이 부착되어 패키징되며, 패키징된 볼 그리드 어레이 패키지는 칩(4)의 전기적 특성을 기판(2) 상면의 금속 배선(1) 및 기판(2)의 내부회로를 통해 패키지 하부의 솔더볼(9)로 전달하여 상기 볼 그리드 어레이 패키지가 실장된 메인보드(도시는 생략함)에 전달할 수 있게 된다.The ball grid array package according to the present invention having the above-described configuration is packaged with a semiconductor chip 4 attached to a substrate 2 having a cross-sectional structure as shown in FIG. 6, and the packaged ball grid array package is a chip 4. ) Is transferred to the solder ball 9 at the bottom of the package through the metal wiring 1 on the upper surface of the substrate 2 and the internal circuit of the substrate 2, and the main board on which the ball grid array package is mounted (not shown). Will be delivered.
이 때, 다이패드(3)를 기준으로 기판(2) 양측에 형성된 패턴 사이의 폭(W)보다 칩(4)의 사이즈가 큰 경우, 칩(4)의 가장자리저면이 절연테이프(6) 상면에 안착되어 안정적으로 고정된다.At this time, when the size of the chip 4 is larger than the width W between the patterns formed on both sides of the substrate 2 with respect to the die pad 3, the bottom edge of the chip 4 is the upper surface of the insulating tape 6. It is seated on and fixed stably.
또한, 상기 다이패드(3) 상면에 도포된 접착제(5)가 이루는 면과 절연테이프(6)의 면은 동일 평면상에 위치하도록하여 단차가 생기지 않도록 하므로써 칩(4) 본딩시 칩(4)의 좌·우 밸런스를 유지시킬 수 있게 된다.In addition, the surface formed by the adhesive 5 applied to the upper surface of the die pad 3 and the surface of the insulating tape 6 are positioned on the same plane so that no step is generated so that the chip 4 is bonded when the chip 4 is bonded. The left and right balance of can be maintained.
따라서, 본 고안의 볼 그리드 어레이 패키지는 다이패드(3)에 안착되는 칩(4)을 칩(4)의 사이즈에 구애받지 않고 폭넓게 패키징할 수 있게 된다.Accordingly, the ball grid array package of the present invention can package the chip 4 mounted on the die pad 3 regardless of the size of the chip 4.
한편, 도 4는 본 고안의 다른 실시예에 따른 볼 그리드 어레이 패키지를 나타낸 종단면도로서, 칩(4) 사이즈가 작은 경우이다.On the other hand, Figure 4 is a longitudinal cross-sectional view showing a ball grid array package according to another embodiment of the present invention, when the chip 4 size is small.
이 경우에는, 내부에 회로가 형성되고 상면에는 금속 배선(1)이 패터닝되며 상면 중앙부에는 돌출부(10)가 형성된 기판(2)의 돌출부(10) 상면에 상기 기판(2) 상면에 패터닝된 양측 배선(1) 사이의 폭 내에 위치하는 사이즈의 칩(4)이 부착되고, 상기 기판(2)과 칩(4) 사이에는 칩(4)을 고정시키는 접착제(5)가 개재되며, 상기 기판(2)에 패터닝된 금속 배선(1)의 내측 선단 상면에는 상기 기판(2)의 돌출부(10)에 도포된 접착제(5)와 동일평면을 이루는 두께를 갖는 절연테이프(6)가 부착된다.In this case, a circuit is formed therein, and the metal wiring 1 is patterned on the upper surface, and the upper surface is patterned on the upper surface of the substrate 2 on the upper surface of the protrusion 10 of the substrate 2 on which the protrusion 10 is formed. A chip 4 having a size located within the width between the wirings 1 is attached, and an adhesive 5 for fixing the chip 4 is interposed between the substrate 2 and the chip 4. An insulating tape 6 having a thickness coplanar with the adhesive agent 5 applied to the protrusion 10 of the substrate 2 is attached to the upper surface of the inner end of the metal wire 1 patterned in 2).
그리고, 상기 칩(4)의 본딩패드(4a)와 기판(2) 상면에 형성된 금속 배선(1)은 금속세선(7)에 의해 전기적으로 연결되며, 상기 칩(4)과 기판(2)상의 배선(1) 및 금속세선(7)은 몰딩부재(8)에 의해 봉지되어 구성된다.In addition, the bonding pads 4a of the chip 4 and the metal wires 1 formed on the upper surface of the substrate 2 are electrically connected to each other by the metal thin wires 7, and on the chip 4 and the substrate 2. The wiring 1 and the metal fine wire 7 are sealed by the molding member 8, and are comprised.
도 5는 칩(4) 사이즈가 큰 경우로서, 상기한 볼 그리드 어레이 패키지의 구성중 나머지 부분은 동일하나, 상기 기판(2)의 돌출부(10) 상면에 부착되는 칩(4)의 사이즈가 칩(4)의 가장자리면이 상기 기판(2)의 양측 금속 배선(1)에 부착된 절연테이프(6) 상면에 부착되는 사이즈 이상이 되도록 구성된다.5 is a case in which the size of the chip 4 is large, and the rest of the configuration of the ball grid array package is the same, but the size of the chip 4 attached to the upper surface of the protrusion 10 of the substrate 2 is different. The edge surface of (4) is comprised so that it may be more than the size adhere | attached on the upper surface of the insulating tape 6 attached to the metal wiring 1 of both sides of the said board | substrate 2. As shown in FIG.
이와 같이 구성된 다른 실시예에 따른 본 고안의 볼 그리드 어레이 패키지는 도 7에 나타낸 바와 같은 단면 구조를 갖는 기판(2)의 돌출부(10)에 반도체 칩(4)이 부착되어 패키징되므로써, 전술한 실시예의 다이패드(3)가 행하던 기능을 기판(2)의 돌출부(10)가 행하게 되며, 패키징 과정 및 작용은 전술한 실시예의 작용과 동일하므로 설명을 생략한다.The ball grid array package according to another embodiment configured as described above is packaged by attaching the semiconductor chip 4 to the protrusion 10 of the substrate 2 having the cross-sectional structure as shown in FIG. The protrusion 10 of the board | substrate 2 performs the function which the die pad 3 of the example performed, and since a packaging process and an action are the same as that of the above-mentioned embodiment, it abbreviate | omits description.
이상에서와 같이, 본 고안은 볼 그리드 어레이 패키지의 구조 개선을 통해 칩(4) 사이즈가 변화하더라도 일정 배선(1)을 갖는 한 종류의 기판(2)으로 패키징이 가능하도록 한 것이다.As described above, the present invention is intended to enable packaging into one type of substrate 2 having a certain wiring 1 even if the size of the chip 4 is changed by improving the structure of the ball grid array package.
이에 따라, 칩(4) 사이즈의 변화에 따른 기판(2)의 재설계 및 툴(tool)교체에 따른 비용 발생 요소를 제거하여 제조 비용을 절감할 수 있게 될 뿐만 아니라, 기판(2)의 변경에 따른 여러 가지 시간적·물적 손실 요소를 해소하여 볼 그리드 어레이 패키지 제조 공정의 생산성을 향상시킬 수 있게 된다.Accordingly, the manufacturing cost can be reduced by eliminating the cost incurred due to the redesign of the substrate 2 and the tool replacement due to the change in the size of the chip 4, and the change of the substrate 2 as well. It is possible to improve the productivity of the ball grid array package manufacturing process by eliminating various time and material loss factors.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970032508U KR200169583Y1 (en) | 1997-11-17 | 1997-11-17 | Ball grid array package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970032508U KR200169583Y1 (en) | 1997-11-17 | 1997-11-17 | Ball grid array package |
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| Publication Number | Publication Date |
|---|---|
| KR19990019174U KR19990019174U (en) | 1999-06-05 |
| KR200169583Y1 true KR200169583Y1 (en) | 2000-02-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970032508U KR200169583Y1 (en) | 1997-11-17 | 1997-11-17 | Ball grid array package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200169583Y1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100818079B1 (en) * | 2002-02-21 | 2008-03-31 | 주식회사 하이닉스반도체 | A method for manufacturing of ball grid array package |
| KR100694425B1 (en) * | 2002-05-06 | 2007-03-12 | 앰코 테크놀로지 코리아 주식회사 | manufacturing method of semiconductor package |
| KR100590477B1 (en) * | 2004-12-22 | 2006-06-19 | 삼성전자주식회사 | Interface between memory module and motherboard edge, and related structure of memory module |
-
1997
- 1997-11-17 KR KR2019970032508U patent/KR200169583Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990019174U (en) | 1999-06-05 |
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