KR100369397B1 - Ball grid array semiconductor package using flexible circuit board - Google Patents

Ball grid array semiconductor package using flexible circuit board Download PDF

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KR100369397B1
KR100369397B1 KR1019970079225A KR19970079225A KR100369397B1 KR 100369397 B1 KR100369397 B1 KR 100369397B1 KR 1019970079225 A KR1019970079225 A KR 1019970079225A KR 19970079225 A KR19970079225 A KR 19970079225A KR 100369397 B1 KR100369397 B1 KR 100369397B1
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semiconductor chip
circuit board
flexible circuit
adhesive
flexible
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KR1019970079225A
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Korean (ko)
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KR19990059030A (en
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하선호
다비욱스 로버트
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A BGA(Ball Grid Array) semiconductor package using a flexible circuit board is provided to be capable of preventing the adhesive coated at the flexible circuit board from contaminating a bond finger. CONSTITUTION: A BGA semiconductor package using a flexible circuit board is provided with a semiconductor chip(10), a flexible circuit board(40) for loading the semiconductor chip, an adhesive for attaching the semiconductor chip to the flexible circuit board, and a bond finger(43). The BGA semiconductor package further includes an adhesive overflow barrier dam(30) between the bond finger and the semiconductor chip. At this time, the thickness of the adhesive overflow barrier dam is smaller than that of the semiconductor chip, so that the adhesive overflow barrier dam doesn't be contacted with a conductive wire(50). Preferably, the adhesive overflow barrier dam is non-conductive.

Description

가요성회로기판을 이용한 볼그리드어레이반도체패키지Ball Grid Array Semiconductor Package Using Flexible Circuit Board

본 발명은 가요성회로기판을 이용한 볼그리드어레이반도체패키지에 관한 것으로, 보다 상세하게 설명하면 가요성회로기판에 반도체칩을 접착시키기 위해 도포되는 접착제가 본드핑거를 오염시키지 않토록 접착제넘침방지용댐을 형성하여 와이어본딩 불량을 제거할 수 있는 가요성회로기판을 이용한 볼그리드어레이반도체패키지에 관한 것이다.The present invention relates to a ball grid array semiconductor package using a flexible circuit board, and more specifically, an adhesive overflow prevention dam to prevent the adhesive applied to bond the semiconductor chip to the flexible circuit board does not contaminate the bond finger. The present invention relates to a ball grid array semiconductor package using a flexible circuit board capable of forming and removing wire bonding defects.

일반적으로 반도체패키지라 함은 각종 전자 회로 및 배선이 접착되어 형성된 단일 소자 및 집적 회로 등의 반도체칩을 먼지, 습기, 전기적, 기계적 부하 등의 각종 외부 환경으로부터 보호하고 상기 반도체칩의 성능을 최적화, 극대화시키기 위해 리드프레임(Lead Frame)이나 인쇄회로기판(PCB ; Printed Circuit Board) 등을 이용해 메인보드(Main Board)로의 신호입/출력단자를 형성하고 봉지수단(Encapsulant)을 이용하여 수지봉지부를 형성한 것을 말한다.In general, a semiconductor package is to protect semiconductor chips such as single devices and integrated circuits formed by bonding various electronic circuits and wirings from various external environments such as dust, moisture, electrical and mechanical loads, and optimize the performance of the semiconductor chips. In order to maximize the signal input / output terminals to the main board using a lead frame or a printed circuit board (PCB), and a resin encapsulation unit is formed using an encapsulant. Say what you did.

이러한 반도체패키지는 전자기기의 고성능화와 경박단소화의 경향으로 점차 고집적화, 소형화, 고기능화되어 가고 있으며, 이에 수반하여 리드프레임을 이용한 수지봉지형반도체패키지는 SOJ(Small Outline J-leaded Package)나 QFP(Quad FlatPackage)와 같은 표면실장형 반도체패키지가 이미 실용화되어 있다. 최근에는 인쇄회로기판 또는 가요성회로기판을 이용함으로써 입/출력단자의 갯수를 극대화하고 또한 메인보드에의 실장밀도를 증대시킬 수 있는 볼그리드어레이반도체패키지(Ball Grid Array Semiconductor Package, 이하 BGA패키지로 칭한다)가 개발되어 반도체패키지의 경박단소화 및 고기능화를 주도하고 있다.Such semiconductor packages are becoming increasingly integrated, miniaturized, and highly functional due to the trend of high performance and light and small size of electronic devices. Surface-mount semiconductor packages such as Quad FlatPackage have already been put to practical use. Recently, a Ball Grid Array Semiconductor Package (BGA) package can be used to maximize the number of input / output terminals and increase the mounting density of the main board by using a printed circuit board or a flexible circuit board. Has been developed to lead to thin and short and high functionality of semiconductor packages.

이러한 BGA패키지중에서 종래의 가요성회로기판을 이용한 BGA패키지(100')를 첨부된 도1a내지 도1c를 참조하여 그 구성을 설명하면 다음과 같다.Referring to FIG. 1A to FIG. 1C attached to the BGA package 100 'using a conventional flexible circuit board, the configuration thereof will be described below.

각종 전자 회로 및 배선이 적층되어 있고 표면에는 다수의 입/출력패드(10a)가 형성되어 있는 반도체칩(10)과, 상기 반도체칩(10)의 저면에 접착제(20)가 개재된 채 가요성수지필름(41)상에 본드핑거(43), 랜드(44) 및 회로패턴(42)이 형성되어 접착된 가요성회로기판(40)과, 상기 반도체칩(10)의 입/출력패드(10a)와 상기 가요성수지필름(41)의 본드핑거(43)를 연결하는 전도성와이어(50)와, 상기 가요성회로기판(40)의 상면 즉, 반도체칩(10) 및 전도성와이어(50) 등을 외부의 환경으로부터 보호하기 위해 봉지수단으로 봉지하여 형성된 수지봉지부(60)와, 상기 가요성수지필름(41)의 회로패턴(42)에 연결된 랜드(44)에 메인보드로의 입/출력단자로써 융착된 전도성볼(70)로 구성된다.Various electronic circuits and wiring are stacked and the semiconductor chip 10 having a plurality of input / output pads 10a formed on the surface thereof, and the adhesive 20 being interposed on the bottom surface of the semiconductor chip 10 is flexible. Bonding fingers 43, lands 44, and circuit patterns 42 formed on the resin film 41 and bonded to the flexible circuit board 40 and the input / output pads 10a of the semiconductor chip 10 ) And the conductive wire 50 connecting the bond finger 43 of the flexible resin film 41, the upper surface of the flexible circuit board 40, that is, the semiconductor chip 10 and the conductive wire 50, etc. To the main board on the resin encapsulation part 60 formed by encapsulating the encapsulation means to protect the external environment and the land 44 connected to the circuit pattern 42 of the flexible resin film 41. Consists of a conductive ball 70 fused as a terminal.

여기서 상기 가요성회로기판(40)의 구성을 좀더 자세히 설명하면 가요성수지필름(41)과, 상기 가요성수지필름(41)상에 구리박막으로써 미세하고 촘촘하게 형성된 회로패턴(42)과, 상기 회로패턴(42)의 소정영역에 반도체칩(10)의 입/출력패드(10a)가 전도성와이어(50)로 본딩되도록 형성된 본드핑거(43)와, 상기회로패턴(42)에 연결된 채 가요성수지필름(41)의 저면을 향하여 노출되어 있으며 차후에 전도성볼(70)이 융착되는 랜드(44)로 구성되어 있다.Herein, the configuration of the flexible circuit board 40 will be described in more detail. The flexible resin film 41 and the circuit pattern 42 finely and tightly formed by a copper thin film on the flexible resin film 41 and the A bond finger 43 formed to bond the input / output pad 10a of the semiconductor chip 10 to the conductive wire 50 in a predetermined region of the circuit pattern 42, and the flexible pattern connected to the circuit pattern 42. It is exposed toward the bottom of the resin film 41, and consists of lands 44 to which the conductive balls 70 are fused later.

도면중 미설명부호 45는 패키지의 제조공정시 가요성회로기판(40)의 위치정렬 및 고정을 위한 핀홀이며, 46은 반도체칩(10)이 접착제(20)가 개재된 채 접착되는 반도체칩접착영역이다.In the drawings, reference numeral 45 denotes a pinhole for aligning and fixing the flexible circuit board 40 during the manufacturing process of the package, and 46 denotes a semiconductor chip adhesion in which the semiconductor chip 10 is bonded with an adhesive 20 interposed therebetween. Area.

각종 전자 회로 등이 집적되어 있는 반도체칩(10)의 표면에는 다수의 입/출력패드(10a)가 형성되어 있으며, 상기 반도체칩(10)은 가요성수지필름(41)상에 구리박막으로 회로패턴(42), 본드핑거(43) 및 랜드(44)가 형성된 가요성회로기판(40)의 중앙에 에폭시와 같은 접착제(20)(전기적으로 비전도성인 것)를 개재하여 부착된다. 여기서 상기 가요성회로기판(40)은 두께 20∼150미크론 범위의 폴리이미드(Polyimide) 등과 같은 가요성수지필름(41)상에 통상적인 방법을 이용하여 회로패턴(42), 본드핑거(43) 및 랜드(44)를 형성시킨다.A plurality of input / output pads 10a are formed on the surface of the semiconductor chip 10 in which various electronic circuits are integrated, and the semiconductor chip 10 is formed of a copper thin film on the flexible resin film 41. A pattern 42, a bond finger 43, and a land 44 are attached to the center of the flexible circuit board 40 via an adhesive 20 such as epoxy (electrically non-conductive). Wherein the flexible circuit board 40 is a circuit pattern 42, bond finger 43, using a conventional method on the flexible resin film 41, such as polyimide (Polyimide) in the range of 20 to 150 microns thick And lands 44 are formed.

상기 회로패턴(42)에 연결된 본드핑거(43)에는 차후에 전도성와이어(50)와의 접착성을 향상시키기 위해 은(Ag)을 도금하며 또한 상기 랜드(44)에도 차후에 전도성볼(70)과의 접착성을 향상시키기 위해 골드(Au)층(44b) 및 니켈(Ni)층(44a)을 도금처리한다. 상기 가요성회로기판(40)의 상면에는 일반적인 인쇄회로기판에서와 같이 솔더마스크를 형성시키지 않는다. 상기 반도체칩(10)의 입/출력패드(10a)와 회로패턴(42)에 연결된 본드핑거(43)는 골드와이어나 알루미늄와이어와 같은 전도성와이어(50)에 의하여 전기적으로 접속된다. 반도체칩(10), 전도성와이어(50) 및 상기 가요성회로기판(40)의 상면은 에폭시몰딩컴파운드(Epoxy Molding Compound)나글럽탑(Glop Top)과 같은 봉지수단으로 봉지되어 수지봉지부(60)가 형성된다. 따라서 상기 가요성회로기판(40)의 반도체칩(10), 전도성와이어(50), 회로패턴(42), 본드핑거(43)는 수지봉지부(60)에 의해 외부의 환경과 완전히 격리된다. 상기 회로패턴(42)에 연결된 랜드(44)에는 솔더볼과 같은 전도성볼(70)을 융착함으로써 메인보드로의 입/출력단자로 사용할 수 있도록 구비된다.The bond finger 43 connected to the circuit pattern 42 is plated with silver (Ag) to improve adhesion to the conductive wire 50 later, and also adhered to the land 44 later with the conductive ball 70. In order to improve the properties, the gold (Au) layer 44b and the nickel (Ni) layer 44a are plated. The upper surface of the flexible circuit board 40 does not form a solder mask as in a general printed circuit board. The bond fingers 43 connected to the input / output pad 10a and the circuit pattern 42 of the semiconductor chip 10 are electrically connected by conductive wires 50 such as gold wires or aluminum wires. The upper surface of the semiconductor chip 10, the conductive wire 50 and the flexible circuit board 40 is encapsulated with a sealing means such as epoxy molding compound or a glove top to form a resin encapsulation part 60 ) Is formed. Therefore, the semiconductor chip 10, the conductive wire 50, the circuit pattern 42, and the bond finger 43 of the flexible circuit board 40 are completely isolated from the external environment by the resin encapsulation unit 60. The land 44 connected to the circuit pattern 42 is provided to be used as an input / output terminal to the main board by fusion bonding a conductive ball 70 such as a solder ball.

이와 같은 구성 및 제조 방법에 의한 가요성회로기판(40)을 이용한 BGA패키지(100')는 가요성회로기판(40)의 반도체칩접착영역(46)에 반도체칩(10)을 접착시킬 때에 미리 에폭시와 같은 접착제(20)를 도포하고 그 위에 반도체칩(10)을 탑재한후 열과 압력을 가하여 접착하게 된다. 그러나 이때 상기 접착제(20)는 유동성이 있는 액체이기 때문에 도포 즉시 또는 반도체칩을 접착시키기 위해 경화가 시작될 때 반도체칩접착영역(46)의 외주연 외측으로 흘러나가가는 레진블리드(Resin Bleed)현상을 유발하여 회로패턴(42)중의 본드핑거(43)부분을 오염시키는 경우가 있다.The BGA package 100 ′ using the flexible circuit board 40 according to the above configuration and manufacturing method is used in advance when the semiconductor chip 10 is bonded to the semiconductor chip bonding region 46 of the flexible circuit board 40. The adhesive 20 such as epoxy is applied and the semiconductor chip 10 is mounted thereon, and the adhesive is applied by applying heat and pressure. However, at this time, since the adhesive 20 is a fluid liquid, a resin bleed phenomenon that flows out of the outer circumference of the semiconductor chip bonding region 46 immediately after application or when curing is started to bond the semiconductor chip is performed. In some cases, the bond finger 43 in the circuit pattern 42 may be contaminated.

도1c에 도시된 바와 같이 접착제(20)가 상기 본드핑거(43)를 오염시켜 상면을 덮어 버리게 되면 차후에 상기 반도체칩(10)의 입/출력패드(10a)와 본드핑거(43)를 전도성와이어(50)로 본딩할때 본딩이 이루어지지 않거나 또는 본딩이 되었다 하더라도 와이어의 전단응력(Wire Shear Strength)이 떨어져 신뢰성 테스트에서 불합격되는 문제가 있다.As shown in FIG. 1C, when the adhesive 20 contaminates the bond finger 43 and covers the upper surface, the input / output pad 10a and the bond finger 43 of the semiconductor chip 10 are subsequently connected to conductive wires. When bonding to (50), even if the bonding is not made or even if the bonding, the shear shear (Wire Shear Strength) of the wire is low, there is a problem that fails in the reliability test.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 가요성회로기판에 반도체칩을 접착시키기 위해 도포되는 접착제가 본드핑거를 오염시키지 않토록 접착제넘침방지용댐을 형성하여 와이어본딩 불량을 제거할 수 있는 가요성회로기판을 이용한 BGA패키지를 제공하는데 있다.Therefore, the present invention has been made to solve the conventional problems as described above, the adhesive applied to bond the semiconductor chip to the flexible circuit board to prevent the contamination of the bond finger to form an adhesive overflow prevention dam wire defect To provide a BGA package using a flexible circuit board that can remove the.

도1a은 종래의 가요성회로기판을 이용한 볼그리드어레이반도체패키지를 도시한 단면도이다.1A is a cross-sectional view showing a ball grid array semiconductor package using a conventional flexible circuit board.

도1b는 종래의 가요성회로기판을 도시한 평면도이다.1B is a plan view illustrating a conventional flexible circuit board.

도1c는 접착제가 가요성회로기판의 본드핑거를 오염시켜 불완전하게 와이어본딩된 상태를 도시한 확대 단면도이다.FIG. 1C is an enlarged cross-sectional view illustrating a state in which an adhesive is incompletely wire bonded by contaminating a bond finger of the flexible circuit board.

도2a는 본 발명의 한 구성 요소인 가요성회로기판을 도시한 평면도이다.Figure 2a is a plan view showing a flexible circuit board as one component of the present invention.

도2b는 본 발명에 의한 가요성회로기판을 이용한 볼그리드어레이반도체패키지를 도시한 단면도이다.2B is a cross-sectional view showing a ball grid array semiconductor package using a flexible circuit board according to the present invention.

도2c는 도2b의 소정 부분을 확대도시한 확대단면도이다.FIG. 2C is an enlarged cross-sectional view illustrating a predetermined portion of FIG. 2B.

- 도면중 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

100' ; 종래의 가요성회로기판을 이용한 볼그리드어레이반도체패키지100 '; Ball Grid Array Semiconductor Package Using Conventional Flexible Circuit Boards

100 ; 본 발명에 의한 가요성회로기판을 이용한 볼그리드어레이반도체패키지100; Ball Grid Array Semiconductor Package Using Flexible Circuit Board According to the Present Invention

10 ; 반도체칩 10a ; 입/출력패드10; Semiconductor chip 10a; I / O pad

20 ; 접착제 30 ; 접착제넘침방지용댐20; Adhesive 30; Adhesive Overflow Dam

40 ; 가요성회로기판 41 ; 가요성수지필름40; Flexible circuit board 41; Flexible Resin Film

42 ; 회로패턴 43 ; 본드핑거42; Circuit pattern 43; Bondfinger

44 ; 랜드 44a ; 니켈층44; Land 44a; Nickel layer

44b ; 골드층 50 ; 전도성와이어44b; Gold layer 50; Conductive Wire

60 ; 수지봉지부 70 ; 전도성볼60; Resin encapsulation part 70; Conductive ball

상기한 목적을 달성하기 위해 본 발명에 의한 가요성회로기판을 이용한 BGA패키지는 표면에 다수의 입/출력패드가 형성되어 있는 반도체칩과; 상기 반도체칩의 저면에 접착제가 개재된 채 가요성수지필름상에 본드핑거, 랜드 및 회로패턴이 형성되어 상면 중앙부가 접착된 가요성회로기판과; 상기 반도체칩의 입/출력패드와 상기 가요성수지필름상의 본드핑거를 연결하는 전도성와이어와; 상기 반도체칩 및 전도성와이어 등을 외부의 환경으로부터 보호하기 위해 봉지수단으로 봉지하여 형성된 수지봉지부와; 상기 회로패턴에 연결된 랜드에 메인보드로의 입/출력단자로써 융착된 전도성볼로 이루어진 가요성회로기판을 이용한 BGA패키지에 있어서, 상기 반도체칩이 접착된 가요성회로기판의 일면에는 본드핑거 내측으로 상기 반도체칩의 외주연보다 크게 접착제넘침방지용댐을 형성한 것을 특징으로 한다.BGA package using a flexible circuit board according to the present invention for achieving the above object is a semiconductor chip having a plurality of input / output pads formed on the surface; A flexible circuit board having bond fingers, lands, and circuit patterns formed on the flexible resin film with adhesives interposed on the bottom of the semiconductor chip, and having an upper center bonded thereto; Conductive wires connecting the input / output pads of the semiconductor chip and bond fingers on the flexible resin film; A resin encapsulation portion formed by encapsulating the semiconductor chip and the conductive wire with an encapsulation means to protect the environment from an external environment; In the BGA package using a flexible circuit board made of a conductive ball fused to the land connected to the circuit pattern as an input / output terminal to the main board, the one side of the flexible circuit board to which the semiconductor chip is bonded inside the bond finger An adhesive overflow preventing dam is formed larger than the outer circumference of the semiconductor chip.

여기서 상기 접착제넘침방용댐은 비전도성으로 하여 본 발명의 목적을 달성할 수도 있다.Here, the adhesive overflow dam may be made non-conductive to achieve the object of the present invention.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2a는 본 발명의 한 구성 요소인 가요성회로기판(40)을 도시한 평면도이고,도2b는 본 발명에 의한 가요성회로기판(40)을 이용한 BGA패키지(100)를 도시한 단면도이며, 도2c는 도2b의 소정 부분을 확대도시한 확대단면도이다.Figure 2a is a plan view showing a flexible circuit board 40 which is one component of the present invention, Figure 2b is a cross-sectional view showing a BGA package 100 using a flexible circuit board 40 according to the present invention, FIG. 2C is an enlarged cross-sectional view illustrating a predetermined portion of FIG. 2B.

본 발명의 구성은 각종 전자 회로 및 배선이 적층되어 있고 표면에는 다수의 입/출력패드(10a)가 형성되어 있는 반도체칩(10)과, 상기 반도체칩(10)의 저면에 접착제(20)가 개재된 채 가요성수지필름(41)상에 본드핑거(43), 랜드(44) 및 회로패턴(42)이 형성되어 중앙 상면이 접착된 가요성회로기판(40)과, 상기 가요성수지필름(41)상의 본드핑거(43) 내측으로 상기 반도체칩(10)의 저면 외주연 크기보다 크게 형성된 접착제넘침방지용댐(30)과, 상기 반도체칩(10)의 입/출력패드(10a)와 상기 가요성수지필름(41)상의 본드핑거(43)를 연결하는 전도성와이어(50)와, 상기 가요성회로기판(40)의 상면 즉, 반도체칩(10) 및 전도성와이어(50) 등을 외부의 환경으로부터 보호하기 위해 봉지수단으로 봉지하여 형성된 수지봉지부(60)와, 상기 회로패턴(42)에 연결된 랜드(44)에 메인보드로의 입/출력단자로써 융착된 전도성볼(70)로 구성된다. 도면중 미설명 부호 46은 접착제(20)가 도포되어 반도체칩(10)이 접착되는 반도체칩접착영역이다.According to the configuration of the present invention, a semiconductor chip 10 having various electronic circuits and wirings stacked and a plurality of input / output pads 10a formed on a surface thereof, and an adhesive 20 formed on a bottom surface of the semiconductor chip 10 may be provided. Bonding fingers 43, lands 44, and circuit patterns 42 are formed on the flexible resin film 41 with the upper surface bonded to the flexible circuit board 40, and the flexible resin film is interposed therebetween. An adhesive overflow preventing dam 30 formed inside the bond finger 43 on the 41 and larger than the outer circumference of the bottom surface of the semiconductor chip 10, the input / output pads 10a of the semiconductor chip 10, and the The conductive wire 50 connecting the bond fingers 43 on the flexible resin film 41 and the upper surface of the flexible circuit board 40, that is, the semiconductor chip 10, the conductive wire 50, and the like are externally connected. In order to protect the environment, the main board is formed on the resin encapsulation part 60 formed by encapsulation means and a land 44 connected to the circuit pattern 42. Consists of the conductive ball 70 is fused as the input / output terminals. In the drawing, reference numeral 46 is a semiconductor chip bonding region to which the adhesive 20 is applied to which the semiconductor chip 10 is bonded.

각종 전자 회로 등이 집적되어 있는 반도체칩(10)의 표면에는 다수의 입/출력패드(10a)가 형성되어 있으며, 상기 반도체칩(10)은 가요성수지필름(41)상에 구리박막으로 회로패턴(42), 본드핑거(43) 및 랜드(44)가 형성되어 있고, 상기 본드핑거(43)내측으로는 접착제넘침방지용댐(30)이 형성된 가요성회로기판(40)의 중앙에 에폭시와 같은 접착제(20)(전기적으로 비전도성일 것)를 개재하여 부착된다. 여기서 상기 가요성회로기판(40)은 두께 20∼150미크론 범위의폴리이미드(Polyimide) 등과 같은 가요성수지필름(41)상에 통상적인 방법을 이용하여 회로패턴(42), 본드핑거(43) 및 랜드(44)를 형성시킨다. 상기 회로패턴(42)에 연결된 본드핑거(43)에는 차후에 전도성와이어(50)와의 접착성을 향상시키기 위해 은을 도금하며 또한 상기 랜드(44)에도 차후에 전도성볼(70)과의 접착성을 향상시키기 위해 니켈층(44a) 및 금층(44b)을 도금처리한다. 한편, 상기 접착제넘침방지용댐(30)은 가요성수지필름(41)상의 회로패턴(42) 또는 랜드(44) 들이 서로 도통하지 않토록 에폭시(Epoxy)등에 실리카등을 첨가시켜 제조된 비전도성의 물질을 사용하며 그 높이는 약 20∼100미크론 범위로 형성한다. 또한 상기 접착제넘침방지용댐(30)의 영역은 모든 본드핑거(43)의 내주연측으로 설정하며 최소한 접착제(20)에 의해 접착되는 반도체칩(10)의 저면 외주연 크기보다는 크게 형성함으로써 여러 크기의 반도체칩(10)이 상기 접착제넘침방지용댐(30)의 접착될 수 있도록 한다. 여기서 상기 접착제넘침방지용댐(30)의 높이를 약 100미크론 이상으로 하면 차후에 전도성와이어(50)가 접촉될 수 있음으로써 여러가지 불량을 야기할 수 있으며 20미크론 이하로 하면 접착제(20)가 흘러 넘칠 수 있다. 상기 반도체칩(10)의 입/출력패드(10a)와 회로패턴(42)에 연결된 본드핑거(43)는 골드와이어나 알루미늄와이어와 같은 전도성와이어(50)에 의하여 전기적으로 접속된다. 상기 반도체칩(10), 전도성와이어(50) 및 상기 가요성회로기판(40)의 상면은 에폭시몰딩컴파운드나 글럽탑과 같은 봉지수단으로 봉지되어 수지봉지부(60)가 형성된다. 따라서 상기 가요성회로기판(40)의 반도체칩(10), 전도성와이어(50), 회로패턴(42), 본드핑거(43)는 수지봉지부(60)에 의해 외부의 환경과 완전히 격리된다. 상기 회로패턴(42)에 연결된 랜드(44)에는 솔더볼과 같은 전도성볼(70)이 고온의 환경하에서 융착됨으로써 메인보드로의 입/출력단자로 사용할 수 있도록 구비된다.A plurality of input / output pads 10a are formed on the surface of the semiconductor chip 10 in which various electronic circuits are integrated, and the semiconductor chip 10 is formed of a copper thin film on the flexible resin film 41. The pattern 42, the bond finger 43 and the land 44 is formed, the inside of the bond finger 43, the epoxy and the epoxy in the center of the flexible circuit board 40, the dam overflow prevention dam 30 is formed It is attached via the same adhesive 20 (which is electrically non-conductive). Wherein the flexible circuit board 40 is a circuit pattern 42, bond finger 43, using a conventional method on a flexible resin film 41, such as polyimide (Polyimide) in the range of 20 to 150 microns thick And lands 44 are formed. The bond finger 43 connected to the circuit pattern 42 is plated with silver to improve adhesion to the conductive wire 50 later, and also to the land 44 later to improve adhesion to the conductive ball 70. The nickel layer 44a and the gold layer 44b are plated to make it work. Meanwhile, the adhesive overflow preventing dam 30 is a non-conductive material prepared by adding silica or the like to epoxy so that the circuit patterns 42 or the lands 44 on the flexible resin film 41 do not conduct with each other. The material is used and its height is formed in the range of about 20 to 100 microns. In addition, the area of the adhesive overflow preventing dam 30 is set to the inner circumferential side of all the bond fingers 43 and formed at least larger than the outer circumferential size of the bottom surface of the semiconductor chip 10 bonded by the adhesive 20. The semiconductor chip 10 may be adhered to the adhesive overflow preventing dam 30. Here, when the height of the adhesive overflow preventing dam 30 is about 100 microns or more, the conductive wire 50 may be contacted later, which may cause various defects. When the thickness of the adhesive 30 is less than 20 microns, the adhesive 20 may overflow. have. The bond fingers 43 connected to the input / output pads 10a and the circuit patterns 42 of the semiconductor chip 10 are electrically connected by conductive wires 50 such as gold wires or aluminum wires. The upper surface of the semiconductor chip 10, the conductive wire 50 and the flexible circuit board 40 is sealed with a sealing means such as an epoxy molding compound or a glue top to form a resin encapsulation part 60. Therefore, the semiconductor chip 10, the conductive wire 50, the circuit pattern 42, and the bond finger 43 of the flexible circuit board 40 are completely isolated from the external environment by the resin encapsulation unit 60. The land 44 connected to the circuit pattern 42 is provided to be used as an input / output terminal to the main board by welding a conductive ball 70 such as a solder ball in a high temperature environment.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않고 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 당업자에 의해 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, various modifications may be made by those skilled in the art without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 가요성회로기판을 이용한 BGA패키지(100)는 반도체칩(10)이 접착되는 가요성회로기판(40)의 상면에 상기 반도체칩(10)의 저면 외주연 크기보다 큰 접착제넘침방지용댐(30)이 형성되어 있음으로써 접착제(20)를 도포한 직후 또는 반도체칩(10)을 탑재하여 열과 압력으로 반도체칩(10)을 접착시에 상기 접착제(20)가 본드핑거(43)쪽으로 흘러가지 못하게 함으로써 완벽한 와이어본딩을 제공하여 신뢰성을 향상시키는 효과가 있다.Therefore, the BGA package 100 using the flexible circuit board according to the present invention overflows the adhesive larger than the outer peripheral size of the bottom surface of the semiconductor chip 10 on the upper surface of the flexible circuit board 40 to which the semiconductor chip 10 is bonded. As the prevention dam 30 is formed, the adhesive 20 bonds to the adhesive finger 43 immediately after the adhesive 20 is applied or when the semiconductor chip 10 is adhered with heat and pressure by mounting the semiconductor chip 10. This prevents flow to the side, providing complete wirebonding and improving reliability.

Claims (2)

상면에 다수의 입/출력패드(10a)가 형성되어 있는 반도체칩(10)과, 가요성수지필름(41)의 상면에 상호 연결된 본드핑거(43), 랜드(44) 및 회로패턴(42)이 다수 형성되어 있고, 상기 가요성수지필름(41)의 상면 중앙에는 상기 반도체칩(10)의 하면이 접착제(20)로 접착되어 있는 가요성 회로기판(40)과, 상기 반도체칩(10)의 입/출력패드(10a)와 상기 가요성수지필름(41)의 상면에 형성된 본드핑거(43)를 연결하는 다수의 전도성와이어(50)와, 상기 반도체칩(10) 및 전도성와이어(50) 등을 외부 환경으로부터 보호하기 위해 봉지수단으로 상기 가요성회로기판(40)의 상면을 봉지하여 형성된 수지봉지부(60)와, 상기 회로패턴(42)에 연결된 랜드(44)의 하면에 상기 가요성수지필름(41)을 관통하여 융착된 다수의 전도성볼(70)로 이루어진 가요성회로기판을 이용한 볼그리드어레이반도체패키지(100)에 있어서,The semiconductor chip 10 having the plurality of input / output pads 10a formed on the upper surface, the bond fingers 43, the lands 44, and the circuit patterns 42 interconnected to the upper surface of the flexible resin film 41. A plurality of flexible circuit boards are formed, the lower surface of the semiconductor chip 10 is bonded to the center of the upper surface of the flexible resin film 41 by an adhesive 20, and the semiconductor chip 10 A plurality of conductive wires 50 connecting the input / output pads 10a and the bond fingers 43 formed on the upper surface of the flexible resin film 41, the semiconductor chip 10, and the conductive wires 50. The flexible encapsulation portion 60 formed by encapsulating the upper surface of the flexible circuit board 40 with sealing means to protect the back from the external environment, and the flexible on the lower surface of the land 44 connected to the circuit pattern 42 Ball grid array using a flexible circuit board composed of a plurality of conductive balls 70 fused through the resin film 41 In the conductor package 100, 상기 반도체칩(10)이 접착된 가요성회로기판(40)의 상면에는, 상기 반도체칩(10)을 가요성회로기판(40)에 접착시키는 접착제(20)가 본드핑거(43)를 오염시키지 않도록, 상기 본드핑거(43)와 상기 반도체칩(10)의 사이에 접착제넘침방지용댐(30)이 더 형성되어 있으며, 상기 접착제넘침방지용댐(30)은 상기 전도성와이어(50)와 접촉되지 않도록 상기 반도체칩(10)의 두께보다 작은 두께로 형성된 것을 특징으로 하는 가요성회로기판을 이용한 볼그리드어레이반도체패키지.On the upper surface of the flexible circuit board 40 to which the semiconductor chip 10 is bonded, an adhesive 20 for adhering the semiconductor chip 10 to the flexible circuit board 40 does not contaminate the bond finger 43. In order to prevent the adhesive overflow prevention dam 30 from being formed between the bond finger 43 and the semiconductor chip 10, the adhesive overflow prevention dam 30 may not be in contact with the conductive wire 50. Ball grid array semiconductor package using a flexible circuit board, characterized in that formed in a thickness smaller than the thickness of the semiconductor chip (10). 제1항에 있어서, 상기 접착제넘침방지용댐(30)은 비전도성인 것을 특징으로하는 가요성회로기판을 이용한 볼그리드어레이반도체패키지.The ball grid array semiconductor package according to claim 1, wherein the adhesive overflow preventing dam (30) is non-conductive.
KR1019970079225A 1997-12-30 1997-12-30 Ball grid array semiconductor package using flexible circuit board KR100369397B1 (en)

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KR100351926B1 (en) * 2000-11-08 2002-09-12 앰코 테크놀로지 코리아 주식회사 Ball Grid Array package

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JPH07176687A (en) * 1993-12-20 1995-07-14 Toshiba Corp Thyristor valve

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JPH07176687A (en) * 1993-12-20 1995-07-14 Toshiba Corp Thyristor valve

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US7498679B2 (en) 2005-07-18 2009-03-03 Samsung Electronics Co., Ltd. Package substrate and semiconductor package using the same

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