KR100639210B1 - ball grid array package - Google Patents

ball grid array package Download PDF

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Publication number
KR100639210B1
KR100639210B1 KR1020040113820A KR20040113820A KR100639210B1 KR 100639210 B1 KR100639210 B1 KR 100639210B1 KR 1020040113820 A KR1020040113820 A KR 1020040113820A KR 20040113820 A KR20040113820 A KR 20040113820A KR 100639210 B1 KR100639210 B1 KR 100639210B1
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South Korea
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bond finger
semiconductor chip
circuit board
printed circuit
input
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KR1020040113820A
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Korean (ko)
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KR20060074708A (en
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조일환
최형석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

본 발명은 볼그리드 어레이 패키지에 관해 개시한 것으로서, 상면에 다수의 입출력 패드가 형성된 반도체 칩; 반도체 칩의 저면에 열경화성 접착테이프가 개재된 채 솔더레지스트에 의해 덮이되, 상면에는 본드핑거, 저면에는 랜드가 노출되고 내부에 회로패턴이 형성된 인쇄회로기판; 반도체 칩의 입출력 패드와 상기 회로기판의 본드핑거를 전기적으로 접속하는 다수의 전도성 와이어; 인쇄회로기판 상부에 형성되어, 상기 반도체 칩, 전도성 와이어, 본드핑거 및 본드핑거의 끝단을 덮는 수지봉지부; 및 인쇄회로기판의 각 볼랜드에 융착된 다수의 솔더볼을 포함하여 이루어진다.The present invention relates to a ball grid array package, comprising: a semiconductor chip having a plurality of input / output pads formed on an upper surface thereof; A printed circuit board covered with a solder resist with a thermosetting adhesive tape interposed on a bottom surface of the semiconductor chip, a bond finger on an upper surface, and lands exposed on a bottom surface, and a circuit pattern formed therein; A plurality of conductive wires electrically connecting the input / output pad of the semiconductor chip and the bond finger of the circuit board; A resin encapsulation portion formed on the printed circuit board and covering the ends of the semiconductor chip, the conductive wire, the bond finger, and the bond finger; And a plurality of solder balls fused to each borland of the printed circuit board.

Description

볼 그리드 어레이 패키지{ball grid array package}Ball grid array package

도 1은 종래기술에 따른 볼 그리드 어레이 패키지를 도시한 단면도.1 is a cross-sectional view showing a ball grid array package according to the prior art.

도 2 및 도 3은 본 발명에 따른 볼 그리드 어레이 패키지를 도시한 단면도 및 평면도.2 and 3 are a cross-sectional view and a plan view showing a ball grid array package according to the present invention.

본 발명은 볼 그리드 어레이 패키지에 관한 것으로서, 보다 구체적으로는 크기를 최소화할 수 있는 볼 그리드 어레이 패키지에 관한 것이다.The present invention relates to a ball grid array package, and more particularly to a ball grid array package that can be minimized in size.

일반적으로 볼그리드 어레이 반도체패키지(Ball Grid Array Semiconductor Package)란 다수의 회로패턴(본드핑거, 랜드 등등)이 일정한 단위 형태(예를 들면 바둑판 형상)로 형성되어 있는 인쇄회로기판위에 반도체 칩을 에폭시(Epoxy)를 개재하여 접착하고, 와이어본딩, 수지봉지 및 솔더볼융착 공정을 실시하여 반도체패키지를 말한다.In general, a ball grid array semiconductor package is an epoxy chip formed on a printed circuit board on which a plurality of circuit patterns (bond fingers, lands, etc.) are formed in a predetermined unit form (for example, a checkerboard shape). Epoxy) is bonded to each other, and wire bonding, resin encapsulation and solder ball fusion processes are performed to refer to a semiconductor package.

이러한 볼 그리드 어레이 패키지의 대표적인 상태를 도1에 도시하였으며 이를 참조하여 그 구조 및 작용을 설명하면 다음과 같다. A representative state of such a ball grid array package is shown in FIG. 1 and the structure and operation thereof will be described with reference to the following.

각종 전자 회로 및 배선이 적층되어 있고 표면에는 다수의 입력/출력 패드(1a)가 형성되어 있는 반도체 칩(1)과, 상기 반도체 칩(1)의 저면에 에폭시(9)가 개재된 채 솔더레지스트(solder-resist; 12)에 의해 덮이되, 상면에는 본드핑거(11b)가 저면에는 랜드(11c)가 각각 노출되며, 내부에 회로패턴(11a)이 형성된 인쇄회로기판(11)과, 반도체 칩(1)의 입력/출력 패드(1a)와 솔더레지스트(12)의 본드핑거(11b)를 연결하는 전도성 와이어(3)와, 상기 인쇄회로기판(11)의 상면 즉, 반도체 칩(1) 및 전도성 와이어(3) 등을 외부의 환경으로부터 보호하기 위해 봉지수단으로 봉지하여 형성된 수지봉지부(5)와, 솔더레지스트(12)의 회로패턴(11a)에 연결된 랜드(11c)에 메인보드로의 입력/출력단자로써 융착된 솔더볼(7)로 구성된다.Solder resist with various electronic circuits and wiring stacked and a plurality of input / output pads 1a formed on the surface thereof, and an epoxy 9 interposed on the bottom surface of the semiconductor chip 1. a printed circuit board 11 and a semiconductor, each of which is covered by a solder-resist 12, a bond finger 11b is exposed on a top surface, and lands 11c are exposed on a bottom surface, and a circuit pattern 11a is formed therein. A conductive wire 3 connecting the input / output pad 1a of the chip 1 and the bond finger 11b of the solder resist 12 and the upper surface of the printed circuit board 11, that is, the semiconductor chip 1. And a resin encapsulation portion 5 formed by encapsulating the conductive wire 3 and the like with an encapsulation means and a land 11c connected to the circuit pattern 11a of the solder resist 12 as a main board. It consists of a solder ball (7) fused as an input / output terminal of.

이상에서와 같은 구조를 하는 종래의 볼그리드 어레이 패키지는 패키지 신뢰성을 위하여 본드핑거(11b)의 가장자리에서 패키지 끝단(솔더레지스트)까지의 거리(A)가 500㎛ 정도 여유분을 두도록 디자인된다. 여기서, 패키지 끝단의 솔더레지스트는 단위 패키지로 쏘잉 시 스트레스로 인한 크랙 발생을 최소화하기 위한 것이다. 따라서, 이로 인해, 패키지의 크기를 줄이는 데 한계가 있다. 이때, 패키지 쏘잉(sawing) 공정 시, 본드핑거(11b)의 가장자리에서 패키지 끝단까지의 거리(A)가 500㎛ 이하로 할 경우, 크랙(crack)이 발생되기 때문에 500㎛ 가량의 일정 거리를 유지하여야 하는 문제가 있다. In the conventional ball grid array package having the structure as described above, the distance A from the edge of the bond finger 11b to the package end (solder resist) is designed to allow a margin of about 500 μm for package reliability. Here, the solder resist at the end of the package is intended to minimize cracking caused by stress when sawing in a unit package. Therefore, there is a limit to reducing the size of the package. At this time, when the distance A from the edge of the bond finger 11b to the end of the package is 500 μm or less during the package sawing process, cracks are generated, so a constant distance of about 500 μm is maintained. There is a problem that must be done.

따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 본드핑거의 가장자리에서 패키지 끝단까지의 거리를 최소화할 수 있는 볼그리드 어레이 패키지를 제공하려는 것이다.Accordingly, to solve the above problem, an object of the present invention is to provide a ball grid array package that can minimize the distance from the edge of the bond finger to the end of the package.

상기 목적을 달성하고자, 본 발명에 따른 볼그리드 어레이 패키지는 상면에 다수의 입출력 패드가 형성된 반도체 칩; 반도체 칩의 저면에 열경화성 접착테이프가 개재된 채 솔더레지스트에 의해 덮이되, 상면에는 본드핑거, 저면에는 랜드가 노출되고 내부에 회로패턴이 형성된 인쇄회로기판; 반도체 칩의 입출력 패드와 상기 회로기판의 본드핑거를 전기적으로 접속하는 다수의 전도성 와이어; 인쇄회로기판 상부에 형성되어, 상기 반도체 칩, 전도성 와이어, 본드핑거 및 본드핑거의 끝단을 덮는 수지봉지부; 및 인쇄회로기판의 각 볼랜드에 융착된 다수의 솔더볼을 포함한다.In order to achieve the above object, the ball grid array package according to the present invention comprises a semiconductor chip having a plurality of input and output pads on the upper surface; A printed circuit board covered with a solder resist with a thermosetting adhesive tape interposed on a bottom surface of the semiconductor chip, a bond finger on an upper surface, and lands exposed on a bottom surface, and a circuit pattern formed therein; A plurality of conductive wires electrically connecting the input / output pad of the semiconductor chip and the bond finger of the circuit board; A resin encapsulation portion formed on the printed circuit board and covering the ends of the semiconductor chip, the conductive wire, the bond finger, and the bond finger; And a plurality of solder balls fused to each borland of the printed circuit board.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 볼 그리드 어레이 패키지를 도시한 단면도 및 평면도이다. 2 is a cross-sectional view and a plan view of a ball grid array package according to the present invention.

본 발명에 따른 볼 그리드 어레이 패키지는, 도 2 및 도 3에 도시된 바와 같이, 각종 전자 회로 및 배선이 적층되어 있고 표면에는 다수의 입력/출력 패드(21a)가 형성되어 있는 반도체 칩(21)과, 반도체 칩(21)의 저면에 열경화성 접착테이프(29)가 개재된 채 솔더레지스트(32)에 의해 덮이되, 상면에는 본드핑거(31b), 저면에는 랜드(31c)가 노출되고 내부에 회로패턴(31a)이 형성된 인쇄회로기판(31)과, 반도체 칩(21)의 입력/출력 패드(21a)와 본드핑거(31b)를 연결하는 전도성 와이어(23)와, 인쇄회로기판(31)의 상부에 형성되어, 반도체 칩(21), 전도성 와이어(23), 본드핑거(31b) 및 본드핑거(31b)의 끝단을 덮어 외부의 환경으로부터 보호하기 위한 수지봉지부(25)와, 회로패턴에 연결된 랜드(31c)에 메인보드로의 입력/출력단자로써 융착된 솔더볼(27)로 구성된다.In the ball grid array package according to the present invention, as shown in FIGS. 2 and 3, various electronic circuits and wirings are stacked and a plurality of input / output pads 21a are formed on a surface of the semiconductor chip 21. And, the bottom surface of the semiconductor chip 21 is covered by the solder resist 32 with the thermosetting adhesive tape 29 interposed therebetween, the bond finger 31b on the upper surface, the land 31c on the bottom surface is exposed and The printed circuit board 31 having the circuit pattern 31a formed thereon, the conductive wire 23 connecting the input / output pad 21a of the semiconductor chip 21 and the bond finger 31b, and the printed circuit board 31. A resin encapsulation portion 25 formed over the semiconductor chip 21, the conductive wire 23, the bond finger 31b, and the ends of the bond finger 31b to protect from the external environment, and a circuit pattern. The solder ball 27 is fused to the land 31c connected to the main board as an input / output terminal to the main board.

각종 전자회로 등이 집적되어 있는 반도체 칩(21)의 표면에는 다수의 입출력 패드(21a)가 형성되어 있으며, 반도체 칩(21)은 인쇄회로기판(31)의 반도체 칩 접착영역(미도시)에 열경화성 접착테이프(29)가 개재되어 부착된다. 반도체 칩(21)의 입력/출력 패드(21a)는 그 반도체 칩(21)의 외주연에 일정거리 이격되어 형성되어 있는 인쇄회로기판(31)의 본드핑거(31b)에 전도성 와이어(23)로 본딩된다. 여기서 상기 본드핑거(31b)의 표면에는 본딩력을 강화하기 위해 통상적으로 은(Ag)이 도금된다. A plurality of input / output pads 21a are formed on the surface of the semiconductor chip 21 in which various electronic circuits and the like are integrated, and the semiconductor chip 21 is attached to a semiconductor chip adhesion region (not shown) of the printed circuit board 31. The thermosetting adhesive tape 29 is interposed and attached. The input / output pad 21a of the semiconductor chip 21 is a conductive wire 23 to the bond finger 31b of the printed circuit board 31 formed at a predetermined distance from the outer circumference of the semiconductor chip 21. Bonded Here, the surface of the bond finger 31b is usually plated with silver (Ag) to enhance bonding strength.

상기 반도체 칩(21) 및 인쇄회로기판(31)의 상면은 외부의 전기적, 기계적, 화학적 환경 등으로부터 보호하기 위해 에폭시 몰딩컴파운드나 글럽탑 같은 봉지수단으로 봉지되어 수지봉지부(25)가 형성된다. The upper surface of the semiconductor chip 21 and the printed circuit board 31 is sealed with an encapsulation means such as an epoxy molding compound or a glue top to protect the external electrical, mechanical, and chemical environment, and the resin encapsulation portion 25 is formed. .

마지막으로, 상기 인쇄회로기판(31)의 랜드(31c)에는 휘발성의 끈적끈적한 플럭스(Flux)를 도포한 상태에서 솔더볼(27)을 안착되고 이것이 고온의 퍼니스(Furnace)에 넣어져 융착된다.Finally, the solder ball 27 is seated on the land 31c of the printed circuit board 31 in a state where a volatile sticky flux is applied, and the solder ball 27 is placed in a high temperature furnace to be fused.

한편, 본드핑거(31b)의 가장자리는 솔더레지스트없이 수지봉지부(25)에 의해 봉지되어 있다. On the other hand, the edge of the bond finger 31b is sealed by the resin sealing part 25 without soldering resist.

본 발명에 따르면, 본드핑거의 가장자리는 솔더레지스트없이 수지봉지부에 의해 봉지된 형태를 가짐으로써, 기존의 A에 해당되는 부위를 500㎛ 보다도 훨씬 작게 제작할 수 있다. 따라서, 패키지의 크기를 최소화할 수 있다. According to the present invention, since the edge of the bond finger is sealed by the resin encapsulation unit without solder resist, the portion corresponding to the existing A can be made much smaller than 500 μm. Therefore, the size of the package can be minimized.

이상에서 설명한 바와 같이, 본 발명은 본드핑거의 가장자리는 솔더레지스트없이 수지봉지부에 의해 봉지된 형태를 가짐으로써, 볼그리드 어레이 패키지에서, 본드핑거의 가장자리에서 패키지 끝단까지의 거리를 기존의 500㎛보다 훨씬 작게 제작이 가능하다. As described above, in the present invention, the edge of the bond finger is sealed by a resin encapsulation part without solder resist, and thus, in a ball grid array package, the distance from the edge of the bond finger to the end of the package is 500 μm. It can be made much smaller.

또한, 본 발명은 본드핑거가 패키지 외곽으로 나오지 않게 됨에 따라, 본드핑거와 수지봉지부 사이가 벌어질 우려가 없어 패키지 신뢰성이 향상된다.In addition, according to the present invention, since the bond finger does not come out of the package, there is no fear that the bond finger and the resin encapsulation portion may be opened, thereby improving package reliability.

Claims (1)

상면에 다수의 입출력 패드가 형성된 반도체 칩;A semiconductor chip having a plurality of input / output pads formed on an upper surface thereof; 상기 반도체 칩의 저면에 열경화성 접착테이프가 개재된 채 솔더레지스트에 의해 덮이되, 상면에는 본드핑거, 저면에는 랜드가 노출되고 내부에 회로패턴이 형성된 인쇄회로기판;A printed circuit board covered with a solder resist with a thermosetting adhesive tape interposed on a bottom surface of the semiconductor chip, a bond finger on an upper surface, a land exposed on a bottom surface, and a circuit pattern formed therein; 상기 반도체 칩의 입출력 패드와 상기 인쇄회로기판의 본드핑거를 전기적으로 접속하는 다수의 전도성 와이어;A plurality of conductive wires electrically connecting the input / output pad of the semiconductor chip and the bond finger of the printed circuit board; 상기 인쇄회로기판 상부에 형성되어, 상기 반도체 칩, 전도성 와이어, 본드핑거 및 본드핑거의 끝단을 덮는 수지봉지부; 및A resin encapsulation portion formed on the printed circuit board and covering the ends of the semiconductor chip, the conductive wire, the bond finger, and the bond finger; And 상기 인쇄회로기판의 각 볼랜드에 융착된 다수의 솔더볼A plurality of solder balls fused to each borland of the printed circuit board 을 포함하고, 상기 본드 핑거의 가장자리는 솔더레지스트없이 수지봉지부에 의해 봉지된 형태를 갖는 반도체 패키지.The semiconductor package of claim 1, wherein the edge of the bond finger is sealed by a resin encapsulation unit without solder resist.
KR1020040113820A 2004-12-28 2004-12-28 ball grid array package KR100639210B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111883A (en) * 1997-10-03 1999-04-23 Mitsui High Tec Inc Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111883A (en) * 1997-10-03 1999-04-23 Mitsui High Tec Inc Semiconductor device

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