KR100331070B1 - Structure of chip size semiconductor package and fabricating method thereof - Google Patents

Structure of chip size semiconductor package and fabricating method thereof Download PDF

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KR100331070B1
KR100331070B1 KR1019970079234A KR19970079234A KR100331070B1 KR 100331070 B1 KR100331070 B1 KR 100331070B1 KR 1019970079234 A KR1019970079234 A KR 1019970079234A KR 19970079234 A KR19970079234 A KR 19970079234A KR 100331070 B1 KR100331070 B1 KR 100331070B1
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South Korea
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circuit board
flexible circuit
semiconductor chip
input
solder ball
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KR1019970079234A
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Korean (ko)
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KR19990059039A (en
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초더리 아십
우찬희
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마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE: A structure of a chip size semiconductor package is provided to make a semiconductor package have a volume similar to a semiconductor chip by using adhesive having conductivity in only Z axis and a flexible circuit board. CONSTITUTION: A plurality of input/output pads(4) are formed on the semiconductor chip. Adhesive(6) is attached to one surface of the semiconductor chip having the plurality of input/output pads, having non-conductivity in X and Y axes and conductivity in only a Z axis. The flexible circuit board(10) is attached to the upper surface of the adhesive having conductivity only in a Z axis. A connecting pad(14) is formed in a position under flexible tape(12) corresponding to the input/output pads of the semiconductor chip. A copper trace(16) is connected to the connecting pad. A plurality of solder ball lands(18) are formed in an end of the copper trace, penetrating the flexible tape. A plurality of solder balls(20) are melted and attached to the solder ball lands of the flexible circuit board.

Description

칩싸이즈반도체패키지의 구조 및 그 제조 방법Structure of Chip Size Semiconductor Package and Manufacturing Method Thereof

본 발명은 칩싸이즈반도체패키지의 구조 및 그 제조 방법에 관한 것으로, 보다 상세하게 설명하면 Z축으로만 전도성을 갖는 접착제 및 가요성회로기판을 이용하여 반도체패키지를 제조함으로써 메인보드 등에의 실장밀도를 증가시키고, 각종 전자기기의 부피를 초소형화할 수 있는 칩싸이즈반도체패키지에 관한 것이다.The present invention relates to a structure of a chip size semiconductor package and a method of manufacturing the same. More specifically, the semiconductor package is manufactured by using an adhesive and a flexible circuit board having conductivity only in the Z-axis, thereby reducing the mounting density on a main board or the like. The present invention relates to a chip size semiconductor package capable of increasing and miniaturizing the volume of various electronic devices.

일반적으로 반도체패키지라 함은 각종 전자 회로 및 배선이 접착되어 형성된 단일 소자 및 집적 회로 등의 반도체칩을 먼지, 습기, 전기적, 기계적 부하 등의 각종 외부 환경으로부터 보호하고 상기 반도체칩의 성능을 최적화, 극대화시키기 위해 리드프레임(Lead Frame)이나 인쇄회로기판(PCB ; Printed Circuit Board) 또는 가요성회로기판 등을 이용해 메인보드(Main Board)로의 입/출력단자를 형성하고 봉지수단(Encapsulant)으로 감싸서 수지봉지부가 형성된 것을 말한다.In general, a semiconductor package is to protect semiconductor chips such as single devices and integrated circuits formed by bonding various electronic circuits and wirings from various external environments such as dust, moisture, electrical and mechanical loads, and optimize the performance of the semiconductor chips. To maximize, form an input / output terminal to the main board by using a lead frame, a printed circuit board (PCB) or a flexible circuit board, and wrap the resin with an encapsulant. It means that the sealing portion is formed.

이러한 반도체패키지는 전자기기의 고성능화와 경박단소(輕薄短小)화의 경향으로 점차 고집적화, 소형화, 고기능화되어 가고 있으며, 이에 수반하여 리드프레임을 이용한 수지봉지형반도체패키지는 SOJ(Small Outline J-leaded Package)나 QFP(Quad Flat Package)와 같은 표면실장형 반도체패키지로 발전하고 있다. 최근에는 인쇄회로기판 또는 가요성회로기판을 이용함으로써 반도체패키지의 부피를 반도체칩의 부피에 가깝게 축소하고 또한 입/출력단자의 갯수를 극대화하여 메인보드에의 실장밀도를 증대시킬 수 있는 칩싸이즈반도체패키지가 개발되어 반도체패키지의 경박단소화 및 고기능화를 주도하고 있다.Such semiconductor packages are becoming increasingly integrated, miniaturized, and highly functional due to the trend of high performance and light and small size of electronic devices, and consequently, resin-encapsulated semiconductor packages using lead frames are SOJ (Small Outline J-leaded Package). And surface-mount semiconductor packages such as QFP (Quad Flat Package). Recently, the use of a printed circuit board or a flexible circuit board reduces the volume of a semiconductor package to be close to that of a semiconductor chip, and also maximizes the number of input / output terminals, thereby increasing the chip density semiconductor. Packages have been developed to lead to thin and short and high functionality of semiconductor packages.

이러한 반도체패키지중에서 종래 가요성회로기판을 이용한 칩싸이즈반도체패키지(100')를 첨부된 도1을 참조하여 그 구성을 간단히 설명하면 다음과 같다.The configuration of the semiconductor package will be described briefly with reference to FIG. 1 to which the chip size semiconductor package 100 ′ using a conventional flexible circuit board is attached.

각종 전자 회로 및 배선이 적층되어 있고 표면에는 다수의 입/출력패드(10a')가 형성되어 있는 반도체칩(10')과, 상기 반도체칩(10')의 저면에 접착제(20')가 개재된 채 가요성수지필름(41')상에 본드핑거(43'), 랜드(44') 및 회로패턴(42')이 형성되어 접착된 가요성회로기판(40')과, 상기 반도체칩(10')의 입/출력패드(10a')와 상기 가요성수지필름(41')의 본드핑거(43')를 연결하는 전도성와이어(50')와, 상기 가요성회로기판(40')의 상면 즉, 반도체칩(10') 및 전도성와이어(50') 등을 외부의 환경으로부터 보호하기 위해 봉지수단으로 봉지하여 형성된 수지봉지부(60')와, 상기 가요성수지필름(41')의 회로패턴(42')에 연결된 랜드(44')에 메인보드로의 입/출력단자로써 융착된 솔더볼(70')로 구성된다.Various electronic circuits and wirings are stacked, and a semiconductor chip 10 'having a plurality of input / output pads 10a' formed on a surface thereof, and an adhesive 20 'interposed on a bottom surface of the semiconductor chip 10'. And a flexible circuit board 40 'bonded with a bond finger 43', a land 44 'and a circuit pattern 42' formed on the flexible resin film 41 'and the semiconductor chip ( 10 ') of the conductive wire 50' connecting the input / output pad 10a 'and the bond finger 43' of the flexible resin film 41 'and the flexible circuit board 40' The resin encapsulation part 60 'formed by encapsulating the upper surface, that is, the semiconductor chip 10', the conductive wire 50 ', and the like from the external environment, and the flexible resin film 41' The solder ball 70 'is fused to the land 44' connected to the circuit pattern 42 'as an input / output terminal to the main board.

이와 같은 구성을 하는 종래 칩싸이즈반도체패키지(100')의 제조 방법은 가요성회로기판(40')의 중앙부에 접착제(20')를 개재하여 반도체칩(10')을 접착하는 반도체칩접착단계와, 상기 반도체칩(10')의 입/출력패드(10a')와 가요성회로기판(40')의 회로패턴(42')중 본드핑거(43')를 골드와이어(Au Wire) 또는 알루미늄와이어(Al Wire) 등의 전도성와이어(50')로 본딩하는 와이어본딩단계와, 상기 반도체칩(10'), 전도성와이어(50') 등을 포함한 가요성회로기판(40')의 상면을 외부의 환경으로부터 보호하기 위해 에폭시몰딩컴파운드(Epoxy Molding Compound)나 글럽탑(Glop Top)등의 봉지수단으로 봉지하여 수지봉지부(60')를 형성하는 수지봉지부형성단계와, 상기 가요성회로기판(40')의 랜드(44')에 전도성볼(70')을 융착하는 전도성볼융착단계를 포함하여 이루어져 있다.A conventional chip size semiconductor package 100 'manufacturing method having such a configuration is a semiconductor chip bonding step of adhering a semiconductor chip 10' through an adhesive 20 'at a central portion of a flexible circuit board 40'. The bond finger 43 'of the input / output pad 10a' of the semiconductor chip 10 'and the circuit pattern 42' of the flexible circuit board 40 'may be formed of gold wire or aluminum wire. The wire bonding step of bonding the conductive wire 50 'such as Al wire, and the upper surface of the flexible circuit board 40' including the semiconductor chip 10 ', the conductive wire 50', etc. Resin encapsulation forming step of encapsulating with encapsulation means such as epoxy molding compound or glove top to form a resin encapsulation portion 60 'to protect it from the environment, and the flexible circuit board And a conductive ball fusion step for fusion bonding the conductive ball 70 'to the land 44' of the 40 '.

이상에서와 같은 종래 칩싸이즈반도체패키지는 반도체칩의 부피에 비해 가요성회로기판 및 수지봉지부의 부피가 더 큼으로써 아직 완전한 칩싸이즈반도체패키지의 형태에 가까워졌다고는 볼 수 없으며 그럼으로써 메인보드 등에의 실장밀도 증대 및 전자기기의 소형화에 한계를 보이고 있다. 또한 반도체칩의 입/출력패드와 가요성회로기판의 본드핑거를 전도성와이어로 본딩함으로써 전기저항이 커져 반도체칩의 전기적 수행능력을 저하시키는 원인이 되고 있다. 한편, 그 제조 방법에 있어서, 상기 반도체칩을 웨이퍼에서 하나씩 소잉(Sawing)하여 가요성회로기판에 접착시키는 방법을 채택함으로써 절차가 복잡하고 제조 시간이 오래 소비되는 문제점이 있다. 더불어 상기 수지봉지부를 에폭시몰딩컴파운드로 형성할 때는 일정한 모양의 금형이 필요함으로써 제조 원가가 대폭 상승하게 되는 문제점이 있다.As mentioned above, the conventional chip size semiconductor package has a larger volume of the flexible circuit board and the resin encapsulation than the volume of the semiconductor chip, and thus, it is not considered that the chip size semiconductor package is closer to the shape of the complete chip size semiconductor package. There is a limit to increasing the mounting density and miniaturization of electronic devices. In addition, bonding the input / output pads of the semiconductor chip and the bond finger of the flexible circuit board with the conductive wires increases the electrical resistance, thereby degrading the electrical performance of the semiconductor chip. On the other hand, in the manufacturing method, there is a problem that the procedure is complicated and the manufacturing time is consumed by adopting a method of sawing the semiconductor chips one by one from the wafer and bonding them to the flexible circuit board. In addition, when the resin encapsulation portion is formed of an epoxy molding compound, there is a problem in that a manufacturing cost is greatly increased because a mold having a predetermined shape is required.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 본 발명의 첫번째 목적은 Z축으로만 전도성을 갖는 접착제 및 가요성회로기판을 이용하여 반도체패키지를 제조함으로써 반도체패키지의 부피를 반도체칩 부피와 비슷하게 축소하여 메인보드 등에의 실장밀도를 증가시키고, 각종 전자기기의 부피를 초소형화할 수 있는 칩싸이즈반도체패키지를 제공하는데 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems. The first object of the present invention is to manufacture a semiconductor package using an adhesive and a flexible circuit board having conductivity only in the Z-axis, thereby increasing the volume of the semiconductor package. It is to provide a chip size semiconductor package that can be reduced to a similar to the chip volume to increase the mounting density on the motherboard, and to miniaturize the volume of various electronic devices.

본 발명의 두번째 목적은 수지봉지부를 형성하지 않음으로써 금형의 구비가 불필요하고 이로 인하여 제조 원가를 대폭 절감할 수 있는 칩싸이즈반도체패키지를 제공하는데 있다.A second object of the present invention is to provide a chip size semiconductor package, which does not require a resin encapsulation unit, thereby eliminating the need for a mold, and thereby greatly reducing manufacturing costs.

본 발명의 세번째 목적은 다수의 반도체칩이 구비되어 있는 웨이퍼상에서 제조공정의 대부분을 수행함으로써 그 절차가 간단하고 제조가 용이한 칩싸이즈반도체패키지의 제조 방법을 제공하는데 있다.A third object of the present invention is to provide a method for manufacturing a chip size semiconductor package, which is simple and easy to manufacture, by performing most of the manufacturing process on a wafer having a plurality of semiconductor chips.

도1은 종래 칩싸이즈반도체패키지의 구조를 도시한 단면도이다.1 is a cross-sectional view showing the structure of a conventional chip size semiconductor package.

도2는 본 발명에 의한 칩싸이즈반도체패키지의 구조를 도시한 단면도이다.2 is a cross-sectional view showing the structure of a chip size semiconductor package according to the present invention.

도3a는 본 발명의 칩싸이즈반도체패키지에 사용된 가요성회로기판의 저면도이고, 도3b는 평면도이며, 도3c는 반도체칩의 평면도이다.FIG. 3A is a bottom view of the flexible circuit board used in the chip size semiconductor package of the present invention, FIG. 3B is a plan view, and FIG. 3C is a plan view of the semiconductor chip.

도4a내지 도4e는 본 발명에 의한 칩싸이즈반도체패키지의 제조 방법을 도시한 설명도이다.4A to 4E are explanatory views showing a method for manufacturing a chip size semiconductor package according to the present invention.

- 도면중 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

100 ; 본 발명에 의한 칩싸이즈반도체패키지100; Chip size semiconductor package according to the present invention

2 ; 반도체칩 4 ; 입/출력패드2 ; Semiconductor chip 4; I / O pad

6 ; 접착제 6a ; 접착물질6; Adhesive 6a; Adhesive

6b ; 전도성물질 10 ; 가요성회로기판6b; Conductive material 10; Flexible circuit board

12 ; 가요성테이프 14 ; 커넥팅패드12; Flexible tape 14; Connecting pad

16 ; 카파트레이스 18 ; 솔더볼랜드16; Kappatrace 18; Solder Borland

20 ; 솔더볼 W ; 웨이퍼20; Solder ball W; wafer

상기한 목적을 달성하기 위해 본 발명의 첫번째 양태(樣態)에 의하면 표면에 다수의 입/출력패드가 형성되어 있는 반도체칩과; 상기 입/출력패드가 형성되어 있는 반도체칩의 일면 전체에 접착되어 있으며, X,Y축으로는 비전도성이고 Z축으로만 전도성을 갖는 접착제와; 상기 Z축으로만 전도성을 갖는 접착제 상면에 접착되어 있으며, 가요성테이프를 중심으로 그 저면에는 상기 반도체칩의 입/출력패드와 대응하는 위치에 커넥팅패드가 형성되어 있고, 상기 커넥팅패드에는 카파트레이스가 연결되어 있으며 상기 카파트레이스의 단부에는 상기 가요성테이프를 관통하여 솔더볼랜드가 형성되어 있는 가요성회로기판과; 상기 가요성회로기판의 솔더볼랜드에 융착된 솔더볼을 포함하여 이루어진 것을 특징으로 한다.According to a first aspect of the present invention, a plurality of input and output pads are formed on the surface to achieve the above object; An adhesive that is attached to the entire surface of the semiconductor chip on which the input / output pad is formed, and which is non-conductive on the X and Y axes and conductive only on the Z axis; It is adhered to the upper surface of the conductive adhesive only in the Z-axis, the bottom of the center of the flexible tape, the connecting pad is formed in a position corresponding to the input / output pad of the semiconductor chip, the connecting pad is kappa trace A flexible circuit board connected to the end of the kappa trace and having a solder ball land penetrating the flexible tape; It characterized in that it comprises a solder ball fused to the solder ball land of the flexible circuit board.

상기한 목적을 달성하기 위해 본 발명의 두번째 양태에 의하면, 입/출력패드를 포함하는 다수의 반도체칩이 형성되어 있는 웨이퍼를 구비하는 웨이퍼준비단계와; 상기 웨이퍼 상면 전체에 Z축으로만 전도성을 갖는 접착제를 개재한채 가요성테이프에 상기 반도체칩의 입/출력패드와 대응하는 위치에는 커넥팅패드가 형성되어 있고, 상기 커넥팅패드에는 카파트레이스가 연결되어 있으며, 상기 카파트레이스의 단부에는 솔더볼랜드가 형성되어 있는 가요성회로기판을 접착하는 가요성회로기판접착단계와; 상기 가요성회로기판의 솔더볼랜드에 다수의 솔더볼을 융착하는 솔더볼융착단계와; 상기 웨이퍼에서 각각의 반도체칩 유닛을 소잉하여 독립된 반도체패키지로 형성하는 웨이퍼소잉단계를 포함하여 이루어진 것을 특징으로 한다.According to a second aspect of the present invention for achieving the above object, a wafer preparation step comprising a wafer on which a plurality of semiconductor chips including an input / output pad is formed; A connecting pad is formed at a position corresponding to the input / output pad of the semiconductor chip on the flexible tape with the adhesive having conductivity only in the Z axis on the entire upper surface of the wafer, and the capatrace is connected to the connecting pad. And a flexible circuit board bonding step of bonding the flexible circuit board having solder balls to the ends of the kappa trace. A solder ball fusion step of fusion welding a plurality of solder balls to the solder ball lands of the flexible circuit board; And a wafer sawing step of sawing each semiconductor chip unit in the wafer to form an independent semiconductor package.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2는 본 발명에 의한 칩싸이즈반도체패키지(100)의 구조를 도시한 단면도이다.2 is a cross-sectional view showing the structure of the chip size semiconductor package 100 according to the present invention.

도시된 바와 같이 본 발명에 의한 칩싸이즈반도체패키지(100)의 구성은 표면에 다수의 입/출력패드(4)가 형성되어 있는 반도체칩(2)과, 상기 입/출력패드(4)가 형성되어 있는 반도체칩(2)의 일면 전체에 접착되어 있으며 Z축으로만 전도성을 갖는 접착제(6)와, 상기 접착제(6) 상면에 접착되어 있으며, 가요성테이프(12)를 중심으로 그 저면에는 상기 반도체칩(2)의 입/출력패드(4)와 대응하는 위치에 커넥팅패드(14)가 형성되어 있고, 상기 커넥팅패드(14)에는 카파트레이스(16)가 연결되어 있으며 상기 카파트레이스(16)의 단부에는 상기 가요성테이프(12)를 관통하여 솔더볼랜드(18)가 형성되어 있는 가요성회로기판(10)과, 상기 가요성회로기판(10)의 솔더볼랜드(18)에 융착된 솔더볼(20)로 이루어진다.As illustrated, the chip size semiconductor package 100 according to the present invention includes a semiconductor chip 2 having a plurality of input / output pads 4 formed on a surface thereof, and the input / output pad 4 formed thereon. It is adhered to the entire surface of the semiconductor chip (2), which is conductive only on the Z-axis, and the adhesive (6), and the upper surface of the adhesive (6), the bottom of the flexible tape 12 A connecting pad 14 is formed at a position corresponding to the input / output pad 4 of the semiconductor chip 2, and a kappa trace 16 is connected to the connecting pad 14. ) And a solder ball fused to the flexible circuit board 10 having the solder ball land 18 formed therethrough and the solder ball land 18 of the flexible circuit board 10 through the flexible tape 12. It consists of 20.

도3c에 도시한 반도체칩(2)의 입/출력패드(4)는 알루미늄(Al)으로 형성되어 있으며, 그 표면에는 Z축으로만 전도성을 갖는 접착제(6)와의 양호한 본딩(Bonding)과 전기적 저항을 최소화하기 위해 니켈(Ni)과 금(Au)이 무전해도금(Eletroless Plating)되어 있다. 상기 접착제(6)는 널리 주지된바와 같이 X,Y축으로는 비전도성이고, Z축으로는 전도성을 가지는 것으로서 상기 접착제(6)를 중심으로 하여 양면에 대응되어 있는 반도체칩(2)의 입/출력패드(4)와 가요성회로기판(10)의 커넥팅패드(14)는 전기적으로 전도된다. 여기서 상기 접착제(6)의 성질을 좀더 자세히 설명하면 도2의 부분 확대도에 도시된 바와 같이 상기 접착제(6)는 일반적인 접착물질(6a)내부에 전도성물질(6b)이 일렬로 세로방향을 향하여 형성되어 있으며, 상기 각각의 전도성물질은 가로방향으로는 일정거리 이격되어 있음으로써 결국 Z축으로는 전도성이 되며 X,Y축으로는 비전도성이 된다.The input / output pad 4 of the semiconductor chip 2 shown in FIG. 3C is made of aluminum (Al), and has good bonding and electrical properties with the adhesive 6 having conductivity only in the Z axis on the surface thereof. Nickel (Ni) and gold (Au) are electroless plated to minimize resistance. As is widely known, the adhesive 6 is non-conductive on the X and Y axes, and has conductivity on the Z axis. The adhesive 6 has a mouth on a semiconductor chip 2 corresponding to both surfaces of the adhesive 6. The output pad 4 and the connecting pad 14 of the flexible circuit board 10 are electrically conductive. Herein, the properties of the adhesive 6 will be described in more detail. As shown in a partially enlarged view of FIG. 2, the adhesive 6 has a conductive material 6b lined in a vertical direction in a general adhesive material 6a. Each conductive material is formed to be spaced apart by a predetermined distance in the horizontal direction, thereby becoming conductive on the Z axis and non-conductive on the X and Y axes.

또한 상기 접착제(6)상에 접착된 가요성회로기판(10)은 도3a내지 도3b에 도시한 바와 같이 가요성테이프(12)를 중심으로 그 저면에는 반도체칩(2)의 입/출력패드(4)와 대응되는 위치에 사각형 모양의 커넥팅패드(14)가 형성되어 있고, 상기 커넥팅패드(14)에는 얇은 구리(Cu) 박막인 카파트레이스(16, Copper Trace)가 연결된채 가요성테이프(12)의 표면에 박막처리되어 있으며, 상기 카파트레이스(16)의 단부에는 원형의 솔더볼랜드(18)가 가요성테이프(12)를 관통하여 형성되어 있다. 여기서 상기 커넥팅패드(14) 및 솔더볼랜드(18) 역시 상기 카파트레이스(16)와 마찬가지로 구리로 형성되며, 상기 커넥팅패드(14)의 표면에는 접착제(6)와의 접착력을 향상시키는 동시에 전기 전도도를 향상시키기 위해 금이 도금되어 있으며, 마찬가지로 상기 솔더볼랜드(18)의 상부 표면에도 차후에 솔더볼(20)과의 융착이 견고해지도록 금이 도금되어 있다. 상기 솔더볼(20)은 널리 주지된바와 같이 납(Pb)과 주석(Sn)의 합금체이다.In addition, the flexible circuit board 10 adhered to the adhesive 6 has an input / output pad of the semiconductor chip 2 on the bottom of the flexible tape 12 as shown in FIGS. 3A to 3B. A connecting pad 14 having a rectangular shape is formed at a position corresponding to (4), and the connecting pad 14 has a flexible tape (copper trace) 16, which is a thin copper (Cu) thin film, connected thereto. A thin film treatment is carried out on the surface of 12, and a circular solder ball land 18 is formed at the end of the kappa trace 16 through the flexible tape 12. Here, the connecting pad 14 and the solder ball land 18 are also made of copper, similar to the capacitive 16, and the surface of the connecting pad 14 improves adhesive strength with the adhesive 6 and at the same time improves electrical conductivity. The gold is plated to make it possible, and similarly, the upper surface of the solder ball land 18 is also plated so that the fusion with the solder ball 20 can be secured later. The solder ball 20 is an alloy of lead (Pb) and tin (Sn), as is well known.

이러한 구성을 하는 본 발명에 의한 칩싸이즈반도체패키지(100)의 제조 방법은 도4a내지 도4e에 도시된 바와 같이, 입/출력패드(4)를 포함하는 다수의 반도체칩(2)이 형성되어 있는 웨이퍼(W)를 구비하는 웨이퍼준비단계와(도4a), 상기 웨이퍼(W) 상면 전체에 Z축으로만 전도성을 갖는 접착제(6)를 개재한채 가요성테이프(12)에 상기 반도체칩(2)의 입/출력패드(4)와 대응하는 위치에는 커넥팅패드(14)가 형성되어 있고, 상기 커넥팅패드(14)에는 카파트레이스(16)가 연결되어 있으며, 상기 카파트레이스(16)의 단부에는 솔더볼랜드(18)가 형성되어 있는 가요성회로기판(10)을 접착하는 가요성회로기판접착단계와(도4b), 상기 가요성회로기판(10)의 솔더볼랜드(18)에 다수의 솔더볼(20)을 융착하는 솔더볼융착단계와(도4d), 상기 웨이퍼(W)에서 각각의 반도체칩(2)을 소잉하여 독립된 반도체패키지로 형성하는 웨이퍼소잉단계(도4e)로 이루어져 있다.In the method for manufacturing the chip size semiconductor package 100 according to the present invention having such a configuration, as shown in FIGS. 4A to 4E, a plurality of semiconductor chips 2 including an input / output pad 4 are formed. The semiconductor chip on the flexible tape 12 with a wafer preparation step including a wafer W (FIG. 4A), and an adhesive 6 having conductivity only in the Z axis on the entire upper surface of the wafer W. A connecting pad 14 is formed at a position corresponding to the input / output pad 4 of 2), and a kappa trace 16 is connected to the connecting pad 14, and an end of the kappa trace 16 is formed. The flexible circuit board bonding step of adhering the flexible circuit board 10 on which the solder ball lands 18 are formed (FIG. 4B), and a plurality of solder balls on the solder bores 18 of the flexible circuit board 10. A solder ball fusion step of fusion 20 (FIG. 4D), and sawing each semiconductor chip 2 from the wafer W; It consists of a wafer sawing step (FIG. 4E) formed of an independent semiconductor package.

상기 웨이퍼준비단계에서 각각의 반도체칩(2)의 입/출력패드(4)에는 니켈과 금을 무전해도금시켜 차후에 Z축으로만 전도성을 갖는 접착제(6)와의 전기적 본딩이 양호해지도록 한다. 또한 웨이퍼(W)상에 상기한 접착제(6)를 개재하여 가요성회로기판(10)을 접착하는 단계에서 상기 접착제(6)는 X,Y축으로는 비전도성이고 Z축으로만 전도성인 것을 사용하며 상기 가요성회로기판(10)은 그 커넥팅패드(14) 및 솔더볼랜드(18)의 표면에 금을 도금시켜 전기전도도 및 본딩력이 향상되도록 한다. 한편, 상기 가요성회로기판접착단계후에는 웨이퍼(W)의 후면에 제조 회사 등의 로고, 문자, 상표등을 잉크 또는 레이저로 마킹(Marking)하는 마킹단계를 추가할 수 있으며 이는 제한된 것이 아니고 당업자에 의해 임의적으로 실시될 수 있다. 그리고 상기 솔더볼융착단계는 상기 가요성회로기판(10)의 솔더볼랜드(18)에 고융체상의 끈적한 플럭스(Flux)를 도포하고 상기 플럭스상에 주석과 납의 합금체인 솔더볼(20)을 안착시킨 후 고온의 퍼니스(Furnace) 내에서 상기 솔더볼(20)이 각각의 솔더볼랜드(18)에 녹아 흘러들어가서 고정되도록 한다.In the wafer preparation step, the input / output pads 4 of each of the semiconductor chips 2 are electroless plated with nickel and gold, so that the electrical bonding with the adhesive 6 which is conductive only in the Z-axis is performed later. In addition, in the step of bonding the flexible circuit board 10 through the adhesive 6 described above on the wafer W, the adhesive 6 is non-conductive on the X and Y axes and only conductive on the Z axis. The flexible circuit board 10 is plated with gold on the surface of the connecting pad 14 and the solder ball land 18 so as to improve the electrical conductivity and bonding strength. Meanwhile, after the flexible circuit board bonding step, a marking step of marking a logo, letters, trademarks, etc. of a manufacturing company, etc., with ink or a laser may be added to the back of the wafer W, which is not limited thereto. It can be carried out arbitrarily. The solder ball fusion step may be performed by applying a high melt sticky flux on the solder ball land 18 of the flexible circuit board 10 and depositing a solder ball 20, which is an alloy of tin and lead, on the flux. In the furnace (Furnace) of the solder ball 20 is melted in each of the solder ball lands 18 to be fixed.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 당업자에 의해 여러가지로 변형된 실시예가 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, various modifications may be made by those skilled in the art without departing from the scope and spirit of the present invention.

따라서 본 발명에 의한 칩싸이즈반도체패키지의 구조 및 그 제조 방법에 의하면, Z축으로만 전도성을 갖는 접착제 및 가요성회로기판을 이용하여 반도체패키지를 제조함으로써 반도체패키지의 부피가 반도체칩의 부피와 비슷하게 축소되어 메인보드 등에의 실장밀도를 증가시키고, 또한 각종 전자기기의 부피를 초소형화할 수 있는 효과가 있다. 또한 종래와 같이 두꺼운 수지봉지부를 형성시키지 않아도 됨으로써 금형의 구비가 불필요하며 이로서 제조 원가를 대폭 절감할 수 있는 효과가 있다. 마지막으로 다수의 반도체칩이 구비되어 있는 웨이퍼상에서 제조 공정의 대부분이 수행됨으로써 그 절차가 간단하고 제조가 용이한 효과가 있다.Therefore, according to the structure of the chip size semiconductor package and the manufacturing method thereof according to the present invention, the semiconductor package is manufactured using an adhesive and a flexible circuit board having conductivity only in the Z-axis so that the volume of the semiconductor package is similar to that of the semiconductor chip. It is reduced, thereby increasing the mounting density of the main board and the like, and also has the effect of miniaturizing the volume of various electronic devices. In addition, since there is no need to form a thick resin encapsulation as in the prior art, it is unnecessary to provide a mold, thereby significantly reducing the manufacturing cost. Finally, the majority of the manufacturing process is performed on a wafer equipped with a plurality of semiconductor chips, the procedure is simple and easy to manufacture.

Claims (2)

표면에 다수의 입/출력패드가 형성되어 있는 반도체칩과;A semiconductor chip having a plurality of input / output pads formed on a surface thereof; 상기 입/출력패드가 형성되어 있는 반도체칩의 일면 전체에 접착되어 있으며, X,Y축으로는 비전도성이고 Z축으로만 전도성을 갖는 접착제와;An adhesive that is attached to the entire surface of the semiconductor chip on which the input / output pad is formed, and which is non-conductive on the X and Y axes and conductive only on the Z axis; 상기 Z축으로만 전도성을 갖는 접착제 상면에 접착되어 있으며, 가요성테이프를 중심으로 그 저면에는 상기 반도체칩의 입/출력패드와 대응하는 위치에 커넥팅패드가 형성되어 있고, 상기 커넥팅패드에는 카파트레이스가 연결되어 있으며 상기 카파트레이스의 단부에는 상기 가요성테이프를 관통하여 솔더볼랜드가 형성되어 있는 가요성회로기판과;It is adhered to the upper surface of the conductive adhesive only in the Z-axis, the bottom of the center of the flexible tape, the connecting pad is formed in a position corresponding to the input / output pad of the semiconductor chip, the connecting pad is kappa trace A flexible circuit board connected to the end of the kappa trace and having a solder ball land penetrating the flexible tape; 상기 가요성회로기판의 솔더볼랜드에 융착된 솔더볼을 포함하여 이루어진 것을 특징으로 하는 칩싸이즈반도체패키지의 구조.The structure of the chip size semiconductor package comprising a solder ball fused to the solder ball land of the flexible circuit board. 입/출력패드를 포함하는 다수의 반도체칩이 형성되어 있는 웨이퍼를 구비하는 웨이퍼준비단계와;A wafer preparation step comprising a wafer on which a plurality of semiconductor chips including input / output pads are formed; 상기 웨이퍼 상면 전체에 Z축으로만 전도성을 갖는 접착제를 개재한채 가요성테이프에 상기 반도체칩의 입/출력패드와 대응하는 위치에는 커넥팅패드가 형성되어 있고, 상기 커넥팅패드에는 카파트레이스가 연결되어 있으며, 상기 카파트레이스의 단부에는 솔더볼랜드가 형성되어 있는 가요성회로기판을 접착하는 가요성회로기판접착단계와;A connecting pad is formed at a position corresponding to the input / output pad of the semiconductor chip on the flexible tape with the adhesive having conductivity only in the Z axis on the entire upper surface of the wafer, and the capatrace is connected to the connecting pad. And a flexible circuit board bonding step of bonding the flexible circuit board having solder balls to the ends of the kappa trace. 상기 가요성회로기판의 솔더볼랜드에 다수의 솔더볼을 융착하는 솔더볼융착단계와;A solder ball fusion step of fusion welding a plurality of solder balls to the solder ball lands of the flexible circuit board; 상기 웨이퍼에서 각각의 반도체칩 유닛을 소잉하여 독립된 반도체패키지로 형성하는 웨이퍼소잉단계를 포함하여 이루어진 것을 특징으로 하는 칩싸이즈반도체패키지 제조 방법.And a wafer sawing step of sawing each semiconductor chip unit in the wafer to form an independent semiconductor package.
KR1019970079234A 1997-12-30 1997-12-30 Structure of chip size semiconductor package and fabricating method thereof KR100331070B1 (en)

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