KR20020049821A - chip scale semiconductor package in wafer level and method for fabricating the same - Google Patents
chip scale semiconductor package in wafer level and method for fabricating the same Download PDFInfo
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- KR20020049821A KR20020049821A KR1020000079116A KR20000079116A KR20020049821A KR 20020049821 A KR20020049821 A KR 20020049821A KR 1020000079116 A KR1020000079116 A KR 1020000079116A KR 20000079116 A KR20000079116 A KR 20000079116A KR 20020049821 A KR20020049821 A KR 20020049821A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 웨이퍼 레벨 칩스케일 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 값싸고 신뢰성 높으며 경박단소화되고 열방출 성능이 향상된 새로운 구조의 웨이퍼 레벨 칩스케일 패키지를 제공하기 위한 것이다.The present invention relates to a wafer level chip scale package and a method of manufacturing the same, and more particularly, to provide a wafer level chip scale package having a novel structure which is inexpensive, reliable, light and small, and having improved heat dissipation performance.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
반도체 조립공정의 개요에 대해 현재 가장 많이 사용되고 있는 플라스틱 타입의 반도체소자를 예로 들어 설명하면 다음과 같다.An overview of the semiconductor assembly process will be described below with an example of a plastic type semiconductor device which is most used.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip, and Si (silicon) has a Mohs hardness of 7 and is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer. In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은 리드프레임의 다이패드에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each separated semiconductor chip is bonded to the die pad of the lead frame, and the bonding method is Au-Si process, soldering method, resin bonding method, etc. Used.
한편, 전술한 바와 같이 반도체 칩을 리드프레임의 다이패드에 접착하는 목적은 조립이 완료된 후 기판에 실장시키기 위해서 뿐만 아니라, 전기적 입출력단자나 어스(earth)를 겸하는 일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로 하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of bonding the semiconductor chip to the die pad of the lead frame is not only to be mounted on the substrate after assembly is completed, but also to serve as an electrical input / output terminal or earth, This is because the heat dissipation path may be required.
상기와 같이 반도체 칩을 본딩한 후에는 칩의 본딩패드와 리드프레임의 인너리드를 와이어로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 패키지에서는 일반적으로 골드 와이어를 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip as described above, the bonding pad of the chip and the inner lead of the lead frame are connected by wire bonding. In the plastic sealing package, the thermal bonding method or the thermocompression bonding using gold wire is generally performed. The method which mixed the method and the ultrasonic method is mainly used.
또한, 와이어 본딩에 의해 반도체 칩과 인너리드가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하므로써 몰드바디를 형성시키는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the semiconductor chip and the inner lead are electrically connected by wire bonding, a molding process of forming a mold body by forming and sealing the chip using a high purity epoxy resin is performed. In addition, the improvement of the high purity of the resin and the reduction of the stress for reducing the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판에 실장하기 위해 아웃터리드(outer lead)를 소정의 형상으로 절단하고 성형하는 공정이 행해지며, 아웃터리드에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다.After the above process is completed, a process of cutting and molding an outer lead into a predetermined shape is carried out to mount the IC package on a socket or a substrate, and the mount is improved in solderability. Plating or dip dips are applied to make them.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 전술한 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and the lead type. As a representative example of the package, in addition to the above-described dual inline package (DIP), QFP (Quad Flat Package), TSOP (Thin Small Outline Package), and BGA package (Ball) Grid Array package (BLP), Bottom Leaded Package (BLP), and the like, continue to be multi-pin or light and thin.
상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여 아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있으며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the above package types, the BGA package (Ball Grid Array package) is used to replace the outer lead by arranging a spherical solder ball in a predetermined state on the back side of the substrate on which the semiconductor chip is attached. The BGA package can make the package body area smaller than the QFP (Quad Flat Package) type, and unlike QFP, there is an advantage that there is no deformation of the lead.
대신, 상기 BGA 패키지는 기존의 리드프레임에 비해 값이 비싼 회로기판을 사용하므로 제조원가가 높아지고, 반도체 칩 및 골드 와이어의 보호를 위해 봉지공정 수행시 상형 및 하형에 의해 회로기판이 눌러져 솔더마스크에 크랙이 발생할 우려가 높아지는 등의 단점이 있다.Instead, the BGA package uses a circuit board that is more expensive than a conventional lead frame, thereby increasing manufacturing costs, and cracking the solder mask by pressing the upper and lower molds during the encapsulation process to protect the semiconductor chip and the gold wire. There are disadvantages such as a high possibility of occurrence.
한편, BLP(Bottom Leaded Package)는 패키지 몸체의 바텀면을 통해 노출된 리드를 이용하여 기판에 실장하므로, 패키지 몸체의 두께를 아웃터리드를 갖는 DIP나 QFP 타입에 비해 작게 할 수 있다.On the other hand, since BLP (Bottom Leaded Package) is mounted on the substrate using the lead exposed through the bottom surface of the package body, the thickness of the package body can be made smaller than that of the DIP or QFP type having an outlier.
그리고, 최근에는 μ-BGA등 웨이퍼 레벨 칩스케일 패키지의 개발이 가속화되고 있으며, 상기한 각 반도체 패키지들은 실장면적, 입출력 단자수, 전기적 신뢰성, 제조공정의 유연성, 제조비용등에 있어 제각기 장점 및 단점을 갖고 있다.In recent years, development of wafer-level chip scale packages such as μ-BGA has been accelerated, and each of the semiconductor packages has advantages and disadvantages in terms of mounting area, number of input / output terminals, electrical reliability, manufacturing process flexibility, and manufacturing cost. Have
따라서, 상기한 각 패키지들의 장점을 살리면서 단점을 해소한 새로운 타입의 반도체 패키지가 지속적으로 연구 개발되고 있는 실정이다.Therefore, a new type of semiconductor package that solves the disadvantages while making use of the advantages of the above-mentioned packages is constantly being researched and developed.
본 발명은 상기한 바와 같이 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 웨이퍼 레벨 칩스케일 패키지를 제공하기 위한 것으로서, 값싸고 방열성이 좋은 알루미나 기판에 회로패턴을 형성하여 제조 비용 측면에서는 저비용으로 제조가능하고 구조적 측면에서는 경박단소하며 신뢰성이 높은 웨이퍼 레벨 칩스케일 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention is to provide a new type of wafer-level chip scale package, which maximizes the advantages of the conventional semiconductor package while eliminating its disadvantages, and is manufactured by forming a circuit pattern on an inexpensive and heat-resistant alumina substrate. The object of the present invention is to provide a wafer-level chip scale package which can be manufactured at low cost in terms of cost, and is light and simple in structure and high reliability.
도 1은 본 발명의 웨이퍼 레벨 칩스케일 패키지를 나타낸 종단면도1 is a longitudinal cross-sectional view showing a wafer level chip scale package of the present invention;
도 2a 내지 도 2h는 본 발명의 패키지 제조 과정을 나타낸 것으로서,Figure 2a to 2h shows a package manufacturing process of the present invention,
도 2a는 일관공정(fabrication)이 완료된 웨이퍼를 나타낸 평면도2A is a plan view showing a wafer on which fabrication has been completed
도 2b는 칩사이즈와 동일한 패턴들을 가진 알루미나 기판을 나타낸 평면도2B is a plan view showing an alumina substrate having patterns identical to chip size
도 2c는 웨이퍼 상면에 어드헤시브가 부착된 상태를 나타낸 종단면도Figure 2c is a longitudinal cross-sectional view showing a state that the adhered to the wafer upper surface
도 2d는 어드헤시브 상면에 알루미나 기판이 부착된 상태를 나타낸 종단면도Figure 2d is a longitudinal cross-sectional view showing a state where the alumina substrate is attached to the upper surface of the adaptive
도 2e는 와이어 본딩후 상태를 나타낸 종단면도Figure 2e is a longitudinal cross-sectional view showing a state after the wire bonding
도 2f는 봉지후의 상태를 나타낸 종단면도Figure 2f is a longitudinal cross-sectional view showing a state after sealing
도 2g는 솔더볼 부착후의 상태를 나타낸 종단면도Figure 2g is a longitudinal cross-sectional view showing a state after the solder ball attached.
도 2h는 소잉시의 상태를 나타낸 종단면도2H is a longitudinal sectional view showing a state at sawing
도 2i는 소잉 후의 완성된 개별 패키지를 나타낸 종단면도2i is a longitudinal sectional view of the completed individual package after sawing
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:칩 2:센터패드1: chip 2: center pad
3:어드헤시브 300:윈도우3: Advance 300: Windows
4:알루미나 기판 400:윈도우4: alumina substrate 400: window
410:본더핑거 420:솔더볼랜드410: Bonder Finger 420: Solder Borland
5:와이어 6:몰드바디5: Wire 6: Molded body
7:솔더볼 8:소잉휠7: Solder Ball 8: Saw Wheel
W:웨이퍼W: Wafer
상기한 목적을 달성하기 위해, 본 발명은 센터패드를 구비한 칩과, 상기 칩상면에 부착되며 센터패드가 노출되는 윈도우가 형성된 어드헤시브와, 상기 센터패드 영역이 노출되도록 하는 윈도우와 상기 윈도우 주위에 배치되는 와이어 본딩을 위한 본더핑거 및 상기 본더핑거 외측에 배치되는 솔더볼 부착을 위한 솔더볼랜드가 구비되며 상기 어드헤시브 상면에 부착되며 알루미나 기판과, 상기 알루미나 기판의 본더핑거와 칩의 센터패드를 각각 연결하는 와이어와, 상기 와이어와 센터패드와 및 본더핑거 부위를 봉지하는 몰드바디와, 상기 알루미나 기판의 솔더볼랜드에 부착되는 솔더볼을 포함하여서 됨을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지가 제공된다.In order to achieve the above object, the present invention provides a chip having a center pad, an adhering window formed on the chip surface and exposing a center pad, a window allowing the center pad area to be exposed, and the window. Bond finger for wire bonding disposed around and solder ball land for solder ball attachment disposed on the outside of the bond finger is provided and attached to the upper surface of the additive and alumina substrate, bonder of the alumina substrate and the center pad of the chip And a mold body encapsulating the wire, the center pad, and the bond finger portion, and a solder ball attached to the solder ball land of the alumina substrate, a wafer level chip scale package is provided.
상기한 목적을 달성하기 위한 본 발명의 다른 형태에 따르면, 웨이퍼 상면에 각 단위소자의 센터패드가 노출되도록 윈도우가 형성된 어드헤시브가 부착되는 단계와, 상기 어드헤시브 상면에 웨이퍼 상의 칩사이즈와 동일한 패턴들을 가지며 웨이퍼 상의 각 단위소자의 센터패드가 노출되도록 윈도우가 구비된 알루미나 기판을 부착하는 단계와, 상기 각 단위소자의 센터패드와 알루미나 기판상에 구비된 본더핑거를 각각 와이어로 본딩하여 전기적으로 연결하는 단계와, 상기 각 단위소자의 센터패드와 본더핑거와 와이어를 봉지하는 단계와, 상기 각 단위소자의 센터패드에 전기적으로 연결되는 솔더볼랜드 상에 솔더볼을 부착하는 단계와, 소잉하여 개별 패키지 단위로 분리하는 단계를 포함하여서 됨을 특징으로 하는 웨이퍼 레벨 칩스케일 패키지 제조방법이 제공된다.According to another aspect of the present invention for achieving the above object, the step of adhering a window formed to expose the center pad of each unit element on the upper surface of the wafer, and the chip size on the wafer on the upper surface Attaching an alumina substrate having windows having the same patterns and having a window exposed to expose the center pad of each unit element on the wafer, and bonding the center finger of each unit element and the bonder provided on the alumina substrate to each other by wire; Connecting to the center pad, encapsulating the center pad, the bonder finger and the wire of each unit device, attaching solder balls onto the solder ball lands electrically connected to the center pad of each unit device, and sawing each other. Wafer level chip scale package characterized in that it comprises the step of separating into packages A manufacturing method is provided.
이하, 본 발명의 실시예를 첨부도면 도 1 내지 도 2i를 참조하여 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 2I.
도 1은 본 발명의 칩스케일 패키지를 나타낸 종단면도로서, 본 발명의 칩스케일 패키지는, 센터패드(2)를 구비한 칩(1)과, 상기 칩(1) 상면에 부착되며 상기 센터패드(2)가 노출되는 윈도우(300)가 형성된 어드헤시브(3)와, 상기 센터패드(2) 영역이 노출되도록 하는 윈도우(400)와 상기 윈도우(400) 주위에 배치되는 와이어 본딩을 위한 본더핑거(410) 및 상기 본더핑거(410) 외측에 배치되는 솔더볼 부착을 위한 솔더볼랜드(420)가 구비되며 상기 어드헤시브(3) 상면에 부착되며 알루미나 기판(4)(Alumina substrate)과, 상기 알루미나 기판(4)의 본더핑거(410)와 칩(1)의 센터패드(2)를 각각 연결하는 와이어(5)와, 상기 와이어(5)와 센터패드(2)와 및 본더핑거(410) 부위를 봉지하는 봉지제와, 상기 알루미나 기판(4)의 솔더볼랜드(420)에 부착되는 솔더볼(7)를 구비하여 구성된다.1 is a longitudinal cross-sectional view illustrating a chip scale package of the present invention, wherein the chip scale package of the present invention includes a chip 1 having a center pad 2 and an upper surface of the chip 1 attached to the chip 1. Bonding finger for wire bonding disposed around the window 400 and the window 400 to expose the area of the center pad (2) is formed, the window 300 is exposed 2) 410 and a solder ball land 420 for attaching solder balls disposed outside the bond finger 410 are attached to an upper surface of the aggressive 3 and have an alumina substrate 4 and the alumina. Wire 5 connecting the bonder 410 of the substrate 4 and the center pad 2 of the chip 1, the wire 5, the center pad 2, and the bonder 410. And a solder ball 7 attached to the solder ball lands 420 of the alumina substrate 4.
이 때, 상기 어드헤시브(3)로서는 열전도성이 좋은 접착테이프 또는 에폭시가 사용되며, 상기 에폭시는 B-스테이지 에폭시임이 바람직하다.At this time, the adhesive 3 or an adhesive tape having good thermal conductivity is used as the advised 3, and the epoxy is preferably a B-stage epoxy.
한편, 상기 알루미나(Alumina; Al2O3) 자체는 구리에 비해 더 뛰어난 절연성을 보이는 절연물질이다.On the other hand, the alumina (Alumina; Al 2 O 3 ) itself is an insulating material showing better insulation than copper.
이와 같이 구성된 본 발명의 웨이퍼 레벨 칩스케일 패키지 제조 과정은 다음과 같다.The wafer level chip scale package manufacturing process of the present invention configured as described above is as follows.
먼저, 도 2a에 도시된 바와 같은 일관공정(fabrication)이 완료된 웨이퍼(W)와, 도 2b에 도시된 바와 같은 칩사이즈와 동일한 패턴들을 가진 알루미나 기판(4)을 준비한다.First, a wafer W having a completed fabrication as shown in FIG. 2A and an alumina substrate 4 having the same patterns as the chip size as shown in FIG. 2B are prepared.
이 때, 상기 알루미나 기판(4)에는, 각 단위소자의 센터패드(2) 영역이 노출되도록 하는 윈도우(400)가 구비되고, 상기 윈도우(400) 주위에는 와이어 본딩을 위한 본더핑거(410)가 구비되며, 상기 본더핑거(410) 외측에는 솔더볼(7) 부착을 위한 솔더볼랜드(420)가 구비되어 있다.At this time, the alumina substrate 4 is provided with a window 400 for exposing the center pad 2 region of each unit element, and a bond finger 410 for wire bonding around the window 400. A solder ball land 420 for attaching the solder ball 7 is provided at the outside of the bond finger 410.
이와 같이 웨이퍼(W)와 알루미나 기판(4)이 준비된 상태에서, 먼저, 웨이퍼(W) 상면에는, 각 단위소자의 센터패드(2)가 노출되도록 윈도우(300)가 형성된 어드헤시브(3)를 도 2c에 나타낸 바와 같이 부착한다.As described above, in the state where the wafer W and the alumina substrate 4 are prepared, first, on the upper surface of the wafer W, the adviser 3 having the window 300 formed so that the center pad 2 of each unit element is exposed. Is attached as shown in FIG. 2C.
이어, 상기 어드헤시브(3) 상면에는, 도 2d에 나타낸 바와 같이, 웨이퍼(W) 상의 칩사이즈와 동일한 패턴들을 가짐과 더불어 상기 웨이퍼 상의 각 단위소자의 센터패드(2)가 노출되도록 윈도우(400)가 구비된 알루미나 기판(4)을 부착한다.Subsequently, as shown in FIG. 2D, the upper surface of the adaptive 3 has the same pattern as the chip size on the wafer W, and the center pad 2 of each unit element on the wafer is exposed. The alumina substrate 4 provided with 400 is attached.
그 다음, 상기 각 단위소자의 센터패드(2)와 알루미나 기판(4)상에 구비된 본더핑거(410)를 윈도우(300)(400)를 통해 연결되는 와이어(5)로 본딩하여 전기적으로 연결하게 된다.Then, the bonder 410 provided on the center pad 2 and the alumina substrate 4 of each unit device is electrically connected by bonding the wires 5 connected through the windows 300 and 400. Done.
이어, 상기 각 단위소자의 센터패드(2)와 본더핑거(410)와 와이어(5)를 봉지하여 몰드바디(6)를 형성하는 봉지공정을 수행하게 된다.Subsequently, an encapsulation process of encapsulating the center pad 2, the bond finger 410, and the wire 5 of each unit element is performed to form the mold body 6.
이 때, 상기 몰드바디(6)는 봉지제의 디스펜싱에 의해 형성되거나, 트랜스퍼 몰딩에 의해 형성된다.At this time, the mold body 6 is formed by dispensing of an encapsulant, or is formed by transfer molding.
그 후, 상기 각 단위소자의 센터패드(2)에 전기적으로 연결되는 솔더볼랜드(420) 상에 솔더볼(7)을 부착하게 되며, 솔더볼(7) 부착 완료 후에는 소잉휠(8)을 이용하여 개별 패키지 단위로 분리하는 소잉을 행하게 된다.Thereafter, the solder balls 7 are attached onto the solder ball lands 420 electrically connected to the center pads 2 of the unit devices. After the solder balls 7 are attached, the sawing wheel 8 is used. The sawing which separates into individual package units is performed.
이와 같이 제조된 본 발명의 칩스케일 패키지는 절연성이 있으면서도 값싸고 구리(copper)재질에 비해 열방출 성능이 좋은 알루미나에 회로를 형성한 회로기판을 이용하는 한편, 범프나 탭 본딩이 아닌 와이어 본딩 방식을 이용하므로 인해, 비용 측면에서 유리하며, 웨이퍼(W) 상태에서 전공정을 끝낸 후 낱개로 분리하기 때문에 제조시간을 단축시킬 수 있게 된다.The chip scale package according to the present invention uses a circuit board in which a circuit is formed on alumina, which is insulated and inexpensive and has better heat dissipation performance than copper, while using wire bonding instead of bump or tab bonding. Because of the use, it is advantageous in terms of cost, and the manufacturing time can be shortened because the process is separated separately after finishing the whole process in the wafer (W) state.
이상에서와 같이, 본 발명은 기존의 반도체 패키지가 갖는 장점을 최대한 살리면서 단점은 해소한 새로운 타입의 웨이퍼 레벨 칩스케일 패키지를 제공하기 위한 것이다.As described above, the present invention is to provide a new type of wafer-level chip scale package that maximizes the advantages of the existing semiconductor package while eliminating its disadvantages.
즉, 본 발명은 값싸고 열방출 성능이 뛰어난 신뢰성 높은 재료에 회로패턴을 형성하여 기판으로 이용하므로써 비용 측면에서는 저비용으로 제조가 가능하며, 구조적 측면에서는 와이어 본딩 방식을 사용하므로서 경박단소하며 신뢰성이 높은 웨이퍼 레벨 칩스케일 패키지의 제조가 가능하다.That is, the present invention can be manufactured at low cost in terms of cost by forming a circuit pattern on a highly reliable material having low heat and excellent heat dissipation performance, and using a wire bonding method in terms of structure, is light and simple and high in reliability. It is possible to manufacture wafer level chip scale packages.
Claims (10)
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| KR1020000079116A KR20020049821A (en) | 2000-12-20 | 2000-12-20 | chip scale semiconductor package in wafer level and method for fabricating the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587081B1 (en) * | 2004-06-30 | 2006-06-08 | 주식회사 하이닉스반도체 | Semiconductor package with improved thermal emission property |
| KR101014577B1 (en) * | 2007-07-18 | 2011-02-16 | 엘피다 메모리 가부시키가이샤 | Semiconductor apparatus, and method of manufacturing semiconductor apparatus |
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2000
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100587081B1 (en) * | 2004-06-30 | 2006-06-08 | 주식회사 하이닉스반도체 | Semiconductor package with improved thermal emission property |
| KR101014577B1 (en) * | 2007-07-18 | 2011-02-16 | 엘피다 메모리 가부시키가이샤 | Semiconductor apparatus, and method of manufacturing semiconductor apparatus |
| US7964962B2 (en) | 2007-07-18 | 2011-06-21 | Elpidia Memory, Inc. | Method of manufacturing a semiconductor apparatus |
| US8441126B2 (en) | 2007-07-18 | 2013-05-14 | Elpida Memory, Inc. | Semiconductor device |
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