KR20010018381A - Circuit board using conductive ink and semiconductor package using the same - Google Patents
Circuit board using conductive ink and semiconductor package using the same Download PDFInfo
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- KR20010018381A KR20010018381A KR1019990034330A KR19990034330A KR20010018381A KR 20010018381 A KR20010018381 A KR 20010018381A KR 1019990034330 A KR1019990034330 A KR 1019990034330A KR 19990034330 A KR19990034330 A KR 19990034330A KR 20010018381 A KR20010018381 A KR 20010018381A
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- conductive ink
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- conductive
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
본 발명은 전도성 잉크를 이용한 회로 기판 및 이를 이용한 반도체 패키지에 관한 것으로, 더욱 상세하게는 수지기판에 형성되는 도전성 트레이스로서 전도성 잉크를 사용하는 것에 의해 경박화하고 및 고신뢰성을 갖는 회로 기판 및 이를 이용한 반도체 패키지에 관한 것이다.The present invention relates to a circuit board using a conductive ink and a semiconductor package using the same, and more particularly, to a circuit board having a thin and high reliability by using a conductive ink as a conductive trace formed on a resin substrate and using the same. A semiconductor package.
근래, 전자 제품, 통신 기기, 컴퓨터 등 반도체 패키지가 사용되는 전자 제품들의 급속한 소형화 추세에 따라, 수지 기판으로 사용되는 인쇄 회로 기판 또는 필름(film)등이 더욱 그 두께가 경박화된 볼 그리드 어레이 반도체 패키지가 요구되어지고 있다.Recently, due to the rapid miniaturization of electronic products using semiconductor packages such as electronic products, communication devices, computers, and the like, printed circuit boards or films used as resin substrates have become thinner and thinner. Package is required.
현재, 통상적인 볼 그리드 어레이 반도체 패키지(이하, 'BGA 반도체 패키지'라 약칭함), 가요성 회로 기판을 이용한 BGA 반도체 패키지, 칩 스케일 반도체 패키지 등은, 기판을 중심으로 상면에는 반도체 칩을 접착시키고 하면에는 다수의 솔더볼을 융착하여 입출력수단으로 사용하는 표면 실장형 반도체 패키지이다. 상기한 반도체 패키지는 많은 수의 입출력 수단을 수용할 수 있을 뿐만 아니라, 패키징 분야에서 요구되고 있는 경박단소(輕薄短小)화에 적합하므로 현재 가장 활발히 보급되고 있는 반도체 패키지들중의 하나이다.Currently, a conventional ball grid array semiconductor package (hereinafter, abbreviated as 'BGA semiconductor package'), a BGA semiconductor package using a flexible circuit board, a chip scale semiconductor package, and the like are bonded to a semiconductor chip on an upper surface of the substrate. The lower surface is a surface-mount semiconductor package used to fuse a plurality of solder balls to use as an input / output means. The above-mentioned semiconductor package is not only able to accommodate a large number of input / output means, but also suitable for light and small size, which is required in the packaging field, and thus is one of the most popular semiconductor packages.
상기한 반도체 패키지들의 기본 구성은 실질적으로 유사하므로, 이들중 BGA 반도체 패키지에 대한 일반적인 구성을 도 1에 도시하였으며 이를 참조하여 간단히 설명하면 다음과 같다.Since the basic configurations of the semiconductor packages are substantially similar, a general configuration of the BGA semiconductor package is shown in FIG. 1 and will be briefly described with reference to the following.
각종 반도체 소자 및 집적 회로 등이 적층되어 있고 표면에는 다수의 입/출력패드(4')가 형성되어 있는 반도체 칩(2')이 접착층(6')을 개재하여 인쇄 회로 기판(10')의 상면 중앙부에 실장되어 있다. 인쇄 회로 기판(10')은 통상 수지 기판(11')을 미리 펀치등에 의하여 천공시킨 후 그 상하면에 구리 박막을 코팅하여 회로 패턴을 형성하고 이 회로 패턴 부분에 레이저 조사 또는, 화학적 엣칭 등에 의하여 그 상하면에 구리층(12',13')으로 이루어지는 회로패턴이 형성되며, 구리층(12',13')의 상면은 고분자 수지인 솔더마스크(30')가 코팅되어 있다.Various semiconductor elements, integrated circuits, and the like are stacked, and a semiconductor chip 2 'having a plurality of input / output pads 4' formed on a surface thereof is formed of a printed circuit board 10 'via an adhesive layer 6'. It is mounted in the center of the upper surface. The printed circuit board 10 'is usually formed by punching the resin substrate 11' in advance with a punch or the like and then coating a copper thin film on the upper and lower surfaces thereof to form a circuit pattern. The circuit pattern portion is formed by laser irradiation or chemical etching. Circuit patterns made of copper layers 12 'and 13' are formed on upper and lower surfaces, and a solder mask 30 'made of a polymer resin is coated on upper surfaces of the copper layers 12' and 13 '.
이를 자세히 설명하면 수지 기판(11')의 중앙 상부에는 일정 크기의 구리층으로 된 반도체 칩 탑재부(16')가 형성되어 반도체 칩(2')이 접착층(6')을 개재하여 접착될 수 있도록 되어 있고, 상기한 탑재부(16')의 외주연으로부터 일정 거리 이격한 동일 평면상에는 소정의 회로 패턴이 다수의 구리층(12')에 의해 형성되어 있으며 그 표면은 솔더마스크(30')로 코팅되어 있다. 또한 상기 수지 기판(11')의 저면에는 상기한 구리층(12') 및 도전성 비아홀(14')과 전기적으로 연결되어 있는 구리층(13')가 다수 형성되어 있고 이 다수의 구리층(13') 각각에는 니켈(Ni)과 골드(Au)가 전해 도금(Electrolytic Plating) 또는 무전해 도금(Electroless Plating)에 의해 원형의 솔더볼 랜드(15')가 형성되어 있으며, 상기한 다수의 솔더볼 랜드(15') 각각에는 메인 보드(도면부호미부여)로의 입/출력수단으로 사용되는 주석(Sn)/납(Pb)의 합금체인 솔더볼(20')이 각각 융착되어 있다. 그리고, 상기한 반도체 칩(2')상의 다수의 입/출력패드(4') 각각은 수지 기판(11') 상면의 다수의 구리층(12') 각각에 골드 와이어(Gold Wire)나 알루미늄 와이어(Al Wire) 또는 범프 등의 전기적 연결 수단(40')에 의하여 연결되어 있으며, 상기한 반도체칩(2') 및 전기적 연결 수단(40') 등을 유해한 전기적, 기계적 및 화학적 외부 환경으로부터 보호하기 위하여 에폭시 몰딩 컴파운드(Epoxy Molding Compound)나 액상 봉지제(Glop Top) 등을 이용하여 몰딩 형성된 봉지부(50')로 원사이드 몰딩되어 있다.In detail, the semiconductor chip mounting portion 16 ′ formed of a copper layer having a predetermined size is formed on the center of the resin substrate 11 ′ so that the semiconductor chip 2 ′ may be bonded through the adhesive layer 6 ′. On the same plane spaced apart from the outer periphery of the mounting portion 16 ', a predetermined circuit pattern is formed by a plurality of copper layers 12', the surface of which is coated with a solder mask 30 '. It is. In addition, a plurality of copper layers 13 'electrically connected to the copper layer 12' and the conductive via hole 14 'are formed on the bottom surface of the resin substrate 11'. ') Each of nickel (Ni) and gold (Au) is formed with a circular solder ball land (15') by electrolytic plating (Electrolytic Plating) or electroless plating (Electroless Plating). 15 ') solder balls 20', which are alloys of tin (Sn) and lead (Pb), which are used as input / output means to the main board (not shown) are fused. Each of the plurality of input / output pads 4 'on the semiconductor chip 2' is a gold wire or an aluminum wire on each of the plurality of copper layers 12 'on the upper surface of the resin substrate 11'. It is connected by electrical connection means 40 'such as (Al Wire) or bump, and protects the semiconductor chip 2' and the electrical connection means 40 'from harmful electrical, mechanical and chemical external environment. In order to do this, one-side molding is performed using an encapsulation part 50 'formed by using an epoxy molding compound or a liquid encapsulant.
이와 같은 구성의 BGA 패키지(100')는 반도체 칩(2'), 전기적 연결 수단(40'), 수지 기판(11'), 수지 기판(11') 상면의 구리층(12'), 도전성 비아홀(14'), 수지 기판(11') 하면의 구리층(13'), 원형 솔더볼 랜드(15'), 솔더볼(20') 등의 순으로 메인 보드(Main Board)와 신호를 교환하고 또한 소정의 전원을 공급받음으로서 반도체 칩(2') 고유의 일정한 전기적 기능을 수행할 수 있게 된다.The BGA package 100 'having such a configuration includes a semiconductor chip 2', an electrical connection means 40 ', a resin substrate 11', a copper layer 12 'on an upper surface of the resin substrate 11', and conductive via holes. 14 ', the copper layer 13' on the bottom surface of the resin substrate 11 ', the circular solder ball land 15', the solder ball 20 ', and the like, and exchange signals with the main board in order. By supplying the power of the semiconductor chip 2 'can perform a specific electrical function inherent.
그러나, 상기한 바와 같이, 수지 기판(11')의 상하면에 구리층(12',13')으로 회로패턴이 형성되어 있는 종래의 BGA 패키지에 있으서는, 수지기판의 경박화에 따라 수지 기판으로 사용되는 인쇄 회로 기판 및 필름의 두께를 더욱 얇게하는 경우, 수지기판(11') 자체의 성질이 매우 가요적인 특성을 가지고 있음으로, 인쇄 회로 기판 의 취급시, 외력에 의해 인쇄 회로 기판가 심하게 휘거나 뒤틀리는 심한 변형이 발생할 수 있고, 이에 따라, 수지 기판{11')의 상하면에 형성된 구리층(12', 13')이 심하게 손상될 우려가 있어 패키지 전체의 기능에 이상을 가져올 수가 있음으로 신뢰성에 치명적일 수가 있다.However, as described above, in a conventional BGA package in which circuit patterns are formed with copper layers 12 'and 13' on the upper and lower surfaces of the resin substrate 11 ', the resin substrate is thinned to the resin substrate. When the thickness of the printed circuit board and the film used is thinner, the properties of the resin substrate 11 'itself are very flexible, and when the printed circuit board is handled, the printed circuit board may be severely bent due to external force. Severe distortion may occur, and therefore, the copper layers 12 'and 13' formed on the upper and lower surfaces of the resin substrate 11 'may be severely damaged, resulting in abnormality in the function of the entire package. It can be fatal.
또한, 수지 기판{11')의 상하면에 형성된 구리층(12', 13')은 그 물질의 특징상 층두께를 더욱 경박화하는 데 한계가 있어, 패키징 분야에서의 경박단소화의 추세에 맞추어 더욱 신뢰성 높은 패키지를 제조할 수 없는 문제점이 있었다.In addition, the copper layers 12 'and 13' formed on the upper and lower surfaces of the resin substrate 11 'have a limitation in further thinning the layer thickness due to the characteristics of the material, and in accordance with the trend of light and short reduction in the packaging field. There was a problem that can not produce a more reliable package.
따라서, 본 발명의 첫 번째 목적은 수지기판에 형성되는 도전성 트레이스로서 외력에 대해 유연성을 갖는 전도성 잉크를 사용하는 것에 의해, 도전성 트레이스로서의 전도성 잉크가 인쇄 회로 기판의 취급시에, 외력에 의해 인쇄 회로 기판이 심하게 휘거나 뒤틀리는 경우에도 변형력에 대한 강한 저항성을 가질 수 있음으로 인쇄 회로 기판 취급시 오류를 방지할 수 있고 패키지 내부의 전기적 연결에 손상을 주지 않는 고신뢰성의 회로 기판을 제공하는 것이다.Therefore, the first object of the present invention is to use a conductive ink having flexibility with respect to external force as the conductive trace formed on the resin substrate, so that the conductive ink as the conductive trace is caused by the external force when handling the printed circuit board. It is possible to provide a highly reliable circuit board which can prevent the errors in handling the printed circuit board and does not damage the electrical connection inside the package because it can have a strong resistance to deformation even when the substrate is severely bent or warped.
본 발명의 두 번째 목적은 수지기판에 도전성 트레이스로서 유연성을 갖는 전도성 잉크를 얇게 도포하여 형성하는 것에 의해, 도전성 트레이스의 두께를 보다 경박하게 수지기판에 도포할 수가 있음으로 보다 경박화된 회로 기판을 제공하는 것이다.The second object of the present invention is to form a thinner coating of the conductive ink having flexibility as a conductive trace on the resin substrate, so that the thickness of the conductive trace can be applied to the resin substrate more lightly. To provide.
본 발명의 세 번째 목적은 수지기판에 형성되는 도전성 트레이스로서 외력에 대해 유연성을 갖는 전도성 잉크를 사용하는 것에 의해, 제조공정이 보다 단축되고 생산성의 향상을 도모할 수 있으며, 원가 절감을 이룰 수 있는 회로 기판을 제공하는 것이다.The third object of the present invention is to use a conductive ink having flexibility against external force as the conductive trace formed on the resin substrate, which can shorten the manufacturing process, improve productivity, and achieve cost reduction. It is to provide a circuit board.
본 발명의 네 번째 목적은 전기 목적에 의한 반도체 패키지를 제공하는 것이다.A fourth object of the present invention is to provide a semiconductor package according to the electrical purpose.
도 1은 종래의 볼 그 리드 어레이 반도체 패키지를 도시한 단면도이다.1 is a cross-sectional view illustrating a conventional ball grid array semiconductor package.
도 2a는 본 발명에 의한 볼 그리드 어레이 반도체 패키지를 도시한 단면도이다.Figure 2a is a cross-sectional view showing a ball grid array semiconductor package according to the present invention.
도 2b는 본 발명에 의한 가요성 회로 기판을 이용한 볼 그리드 어레이 반도체 패키지를 도시한 단면도이다.Figure 2b is a cross-sectional view showing a ball grid array semiconductor package using a flexible circuit board according to the present invention.
도 2c는 본 발명에 의한 칩 사이즈 반도체 패키지를 도시한 단면도이다.2C is a cross-sectional view illustrating a chip size semiconductor package according to the present invention.
-도면중 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
100' : 종래의 볼 그리드 어레이 반도체 패키지100 ': conventional ball grid array semiconductor package
100, 100a, 100b : 본 발명에 의한 반도체 패카자100, 100a, 100b: semiconductor packer according to the present invention
2 : 반도체 칩 4 : 입출력 패드2: semiconductor chip 4: input / output pad
6 : 접착층 10 : 기판6: adhesive layer 10: substrate
11 : 수지 기판 12,13 : 전도성 잉크층11: resin substrate 12, 13 conductive ink layer
14 : 도전성 비아홀14: conductive via hole
15 : 원형의 솔더볼 랜드 16 : 반도체 칩 탑재부15: circular solder ball land 16: semiconductor chip mounting portion
20 : 솔더볼 30 : 솔더 마스크20: solder ball 30: solder mask
40 : Au 와이어 50 : 봉지부40: Au wire 50: encapsulation
60 : Au층60: Au layer
이하, 본 발명을 첨부 도면을 참조하여 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
먼저, 도 2a 는 본 발명에 의한 BGA 패키지(100)의 단면도로서, 도시된 바와 같이, 본 발명에 의한 BGA 패키지(100)는, 반도체 소자 및 집적회로 등이 적층, 형성되고 다수의 입출력 패드(4)가 상면 외주연부에 형성되어 있는 반도체 칩(2)이 접착층(6)을 인쇄회로 기판(10)의 상면 중앙부에 실장되어 있다.First, FIG. 2A is a cross-sectional view of the BGA package 100 according to the present invention. As shown in the drawing, the BGA package 100 according to the present invention includes a semiconductor device, an integrated circuit, and the like, stacked and formed. The semiconductor chip 2 in which 4) is formed in the outer periphery of the upper surface is mounted on the upper surface center of the printed circuit board 10 with the adhesive layer 6.
인쇄 회로 기판(10)은 예컨대, 유리 섬유 보강 열경화성 수지 복합재 또는 비스밀레이미드트리아진 등과 같은 수지 기판(11)의 상면 중앙부에 외력에 대해 유연성이 양호한 전도성 잉크를 도포하여 형성되는 반도체 칩 탑재부(16)가 형성되며, 상기한 탑재부(16)와 일정 거리 이격된 동일 평면상에는 다수의 전도성 잉크층(12)로 이루어지는 회로 패턴이 형성되어 있다. 또한, 상기한 수지 기판(11)의 하면에도 다수의 전도성 잉크층(13)로 이루어지는 회로 패턴이 형성되어 있고 상기한 하면의 전도성 잉크층(13) 각각에는 니켈 및 골드가 순차적으로 도금된 원형 솔더볼 랜드(15) 및/또는 타원형 솔더볼 랜드(15a)가 형성된다. 그리고, 상기한 수지 기판(11)의 상하면에 각각 형성된 다수의 전도성 잉크층(12,13) 각각은 전도성 잉크로 된 전도성 비아홀(14)에 의하여 상호 전기적으로 연결되며, 상기한 다수의 솔더볼 랜드(15 및 15a), 반도체 칩 탑재부(16) 및, 수지 기판(11) 상면의 전도성 잉크층(12)의 내측 단부를 제외한 영역에는 고분자 수지인 솔더 마스크(30)가 코팅되어 있어서 상기한 다수의 전도성 잉크층(12,13) 상호간을 절연시킴과 아울러, 이들을 외부 환경으로 보호한다.The printed circuit board 10 is a semiconductor chip mounting portion 16 formed by applying a conductive ink having good flexibility to external forces to a central portion of the upper surface of a resin substrate 11 such as, for example, a glass fiber reinforced thermosetting resin composite or bismilimide triazine. ) Is formed, and a circuit pattern including a plurality of conductive ink layers 12 is formed on the same plane spaced apart from the mounting portion 16 by a predetermined distance. In addition, a circuit pattern including a plurality of conductive ink layers 13 is formed on the lower surface of the resin substrate 11, and each of the conductive ink layers 13 on the lower surface is a circular solder ball sequentially plated with nickel and gold. Lands 15 and / or elliptical solder ball lands 15a are formed. Each of the plurality of conductive ink layers 12 and 13 formed on the upper and lower surfaces of the resin substrate 11 is electrically connected to each other by conductive via holes 14 made of conductive ink. 15 and 15a), the semiconductor chip mounting portion 16, and the solder mask 30 made of a polymer resin are coated on a region except the inner end of the conductive ink layer 12 on the upper surface of the resin substrate 11, thereby forming a plurality of conductive materials. The ink layers 12 and 13 are insulated from each other and protected from the external environment.
상기한 본 발명의 바람직한 구체예에 있어서, 수지 기판(11)의 상면 중앙부에 전도성 잉크층를 도포하여 형성되는 반도체 칩 탑재부(16), 수지 기판(11)의 상하면에 각각 형성된 다수의 전도성 잉크층(12,13) 및 전도성 비아홀(14)은 전도성 잉크를 일반적으로 산업체에서 널리 사용되는 실크 스크린 프린팅(silk screen printing) 방식을 이용해서 미리 펀치등에 의하여 천공된 수지기판상에 도포할 수도 있으나, 대량 생산에 유리한 마크 잉크 프린팅(mark ink printing)방식을 사용함으로써 단기간에 효율적인 작업이 가능하다.In the above-described preferred embodiment of the present invention, a plurality of conductive ink layers formed on the upper and lower surfaces of the semiconductor chip mounting portion 16 and the resin substrate 11 respectively formed by applying a conductive ink layer to the upper center portion of the resin substrate 11 ( 12 and 13 and the conductive via hole 14 may apply conductive ink onto a resin substrate previously punched by a punch or the like by using a silk screen printing method which is generally used in industry. It is possible to work efficiently in a short time by using a mark ink printing method that is advantageous to the.
또한, 상기 외력에 대해 유연성이 양호한 본 발명의 전도성 잉크의 재료로서는 일본 아케선(Acheson)사등에서 제조되는 다양한 제품을 사용할 수가 있음으로, 도전성 트레이스로서의 전도성 잉크가 인쇄 회로 기판의 취급시, 외력에 의해 인쇄 회로 기판이 심하게 휘거나 뒤틀리는 경우에도 변형력에 대한 저항성을 가질 수 있음으로 인쇄 회로 기판 취급시 오류를 방지할 수 있고 패키지 내부의 전기적 연결에 손상을 주지 않게 되는 것이다.In addition, as a material of the conductive ink of the present invention having good flexibility with respect to the external force, various products manufactured by Japan's Acheson, etc. can be used, so that the conductive ink as the conductive trace is applied to the external force when handling the printed circuit board. As a result, even when the printed circuit board is severely bent or twisted, the printed circuit board may have resistance to deformation force, thereby preventing errors in handling the printed circuit board and not damaging the electrical connection inside the package.
또한, 수지 기판의 상하면에 도포하여 형성되는 전도성 잉크층의 두께는 대략 5-100 미크로 미터, 바람직하게는 15-30 미크로 미터로 도포가능함으로 종래의 구리층보다 훨씬 얇게 형성할 수가 있어 경박단소화한 BGA 패키지의 제조가 가능하다.In addition, the thickness of the conductive ink layer formed by coating on the upper and lower surfaces of the resin substrate is about 5-100 micrometers, preferably 15-30 micrometers, so that the thickness can be formed much thinner than the conventional copper layer. One BGA package can be manufactured.
또한, 본 발명의 상기 인쇄 회로 기판 대신에 필름(film)을 사용해도 무방하며, 이는 제한 적인 것은 아니다.In addition, a film may be used instead of the printed circuit board of the present invention, which is not limited.
한편, 상기한 인쇄 회로 기판(10) 상면의 다수의 전도성 잉크층(12) 각각의 본드 핑거(도면부호 미부여)와 반도체 칩(2) 상면의 입출력 패드(4) 각각은 전기적 골드 와이어(40)에 의하여 상호 접속될 수 있으며, 골드 와이어 대신에 도전성 와이어인 골드 와이어나 알루미늄 와이어, 또는 솔더 범프등을 사용할 수도 있다. 또한, 상기한 반도체 칩(2)와 상기한 Au 와이어(40)등은 유해한 전기적, 기계적, 및 화학적 외부 환경으로 부터 보호하기 위하여 수지로 몰딩된 봉지부(50)내에 봉지된다. 마지막으로, 상기 인쇄 회로 기판(10)의 저면의 솔더볼 랜드(15, 15a)에는 외부 입출력 단자로서 가능하게 되는 주석/납 합금체로 된 솔더볼(20)이 융착되어 진다.Meanwhile, each of the bond fingers (not shown) of the plurality of conductive ink layers 12 on the upper surface of the printed circuit board 10 and the input / output pads 4 on the upper surface of the semiconductor chip 2 are electrically connected to the gold wire 40. ), And instead of gold wires, conductive wires such as gold wires, aluminum wires, or solder bumps may be used. In addition, the semiconductor chip 2 and the Au wire 40 and the like are encapsulated in a resin-molded encapsulation 50 to protect from harmful electrical, mechanical, and chemical external environments. Finally, solder balls 20 made of a tin / lead alloy body that can be used as external input / output terminals are fused to solder ball lands 15 and 15a on the bottom of the printed circuit board 10.
본 발명에 있어서, 상기 솔더 마스크(30)가 코팅되지 않는 상기한 본 발명의 수지 기판(11) 상면의 전도성 잉크층(12)의 내측 단부상에는 전기적 골드 와이어와(40)와 동일한 재료인 Au층(60)을 형성함으로서 다수의 전도성 잉크층(12) 과 반도체 칩(2) 상면의 입출력 패드(4)와의 양호한 전기적 접속이 이루어질 수 있으나, Au, Ag, Ni, Pd 또는 이들의 합금으로 형성할 수 있으며, 이런 층의 형성은 본 발명에 있어 제한적이지는 않다.In the present invention, on the inner end of the conductive ink layer 12 on the upper surface of the resin substrate 11 of the present invention, in which the solder mask 30 is not coated, Au which is the same material as the electrical gold wire 40 is formed. By forming the layer 60, a good electrical connection can be made between the plurality of conductive ink layers 12 and the input / output pad 4 on the upper surface of the semiconductor chip 2, but formed of Au, Ag, Ni, Pd or an alloy thereof. The formation of such a layer is not limited to the present invention.
도 2b는 본 발명에 따른 가요성 회로 기판을 이용한 BGA 패키지(100a)의 단면도로서 그 기본 구성은 전술한 바와 같은 PCB를 이용한 볼 그리드 어레이 반도체 패키지(100)의 기본 구성과 동일하므로 동일한 구성 요소에 대한 중복 설명은 피하고 그 차이점에 대해서만 주로 설명하기로 한다.2B is a cross-sectional view of the BGA package 100a using the flexible circuit board according to the present invention, and its basic configuration is the same as that of the ball grid array semiconductor package 100 using the PCB as described above. Duplicate explanations will be avoided and only the differences will be explained mainly.
도 2b의 반도체 패키지(100a)에 있어서는, 기판(10)에 전도성 잉크로 된 전도성 비아홀, 솔더마스크, 그 하면에 위치하는 전도성 잉크층등은 존재하지 않으며, 회로 패턴(10)상에 단 하나의 전도성 잉크층(12)만이 형성된 회로 패턴을 갖는 가요성 회로 기판(10)을 이용함으로써 패키지의 경박화에 크게 기여할 수가 있다.In the semiconductor package 100a of FIG. 2B, a conductive via hole made of a conductive ink, a solder mask, and a conductive ink layer disposed on a lower surface thereof do not exist in the substrate 10, and only one circuit pattern 10 is formed on the circuit pattern 10. The use of the flexible circuit board 10 having the circuit pattern in which only the conductive ink layer 12 is formed can greatly contribute to the thinning of the package.
상기 도 2b의 반도체 패키지(100a)에 있어서도, 전도성 잉크층의 형성 방법, 재료 및 도포 두께는 전술한 바와같이 동일함으로 더 이상의 설명은 생략하기로 한다.Also in the semiconductor package 100a of FIG. 2B, the method, material, and coating thickness of the conductive ink layer are the same as described above, and thus, further description thereof will be omitted.
또한, 상기 가요성 회로 기판(10)대신에 필름을 사용할 수도 있으며, 본 발명에 있어, 이것은 제한적이지는 않다.In addition, a film may be used instead of the flexible circuit board 10, and in the present invention, this is not limiting.
도 2c는 본 발명에 따른 칩 스케일 또는 칩 사이즈 반도체 패키지(100b)의 단면도로서, 그 기본 구성은 전술한 바와 같은 인쇄 회로 기판을 이용한 볼 그리드 어레이 반도체 패키지(100)의 기본 구성과 유사하므로 동일한 구성 요소에 대한 중복 설명은 피하고 그 차이점에 대해서만 주로 설명하기로 한다.2C is a cross-sectional view of the chip scale or chip size semiconductor package 100b according to the present invention, the basic configuration of which is similar to that of the ball grid array semiconductor package 100 using the printed circuit board as described above. Duplicate descriptions of the elements are avoided, and the differences are mainly explained.
도 2c의 반도체 패키지(100b)에 있어서는, 기판(10)에 전도성 비아홀, 솔더마스크, 그 하면에 위치하는 전도성 잉크층등은 존재하지 않으며, 길이가 짧고 단 한 층의 회로 패턴만을 갖는 가요성 회로 기판(10)을 이용함으로써 패키지의 경박단소화에 크게 기여할 수가 있다. 도면중 도면 부호 21은 솔더 범프로서 반도체 칩(2)의 입출력 패드(미도시)와 전도성 잉크층(12)을 상호 전기적으로 접속하며, 상기한 전도성 잉크층(12)상에는 솔더 마스크(30)가 코팅되어 있으며, 도면중 미설명 부호 6은 접착층이다.In the semiconductor package 100b of FIG. 2C, the conductive via hole, the solder mask, and the conductive ink layer disposed on the lower surface thereof do not exist in the substrate 10, and the flexible circuit has a short length and has only one circuit pattern. By using the board | substrate 10, it can contribute significantly to the thin and light reduction of a package. In the drawing, reference numeral 21 denotes a solder bump to electrically connect the input / output pad (not shown) and the conductive ink layer 12 of the semiconductor chip 2 to each other, and the solder mask 30 is formed on the conductive ink layer 12. It is coated, and reference numeral 6 in the drawings is an adhesive layer.
상기 도 2c의 반도체 패키지(100b)에 있어서도, 전도성 잉크층의 형성 방법, 재료 및 도포 두께는 전술한 바와같이 동일함으로 더 이상의 설명은 생략하기로 한다.Also in the semiconductor package 100b of FIG. 2C, the method, material, and coating thickness of the conductive ink layer are the same as described above, and thus, further description thereof will be omitted.
또한, 상기 가요성 회로 기판(10)대신에 필름을 사용할 수도 있으며, 본 발명에 있어, 이것은 제한적이지는 않다.In addition, a film may be used instead of the flexible circuit board 10, and in the present invention, this is not limiting.
이상 상술한 바와 같이, 본 발명에 의한 전도성 잉크를 이용한 볼 그리드 어레이 반도체 패키지는 도전성 트레이스로서의 유연성을 갖는 전도성 잉크가 인쇄 회로 기판의 취급시, 외력에 의한 인쇄 회로 기판의 휨이나 뒤틀림의 경우에도 변형력에 대한 강한 저항성을 가질 수 있음으로, 인쇄 회로 기판 취급시 오류를 방지할 수 있고 패키지 내부의 전기적 연결에 손상을 주지 않는 것과 아울러, 도전성 트레이스의 두께를 보다 경박하게 수지기판에 도포할 수가 있음으로 보다 경박화되고 신뢰성 있는 회로 기판 및 이를 이용한 반도체 패키지를 제공할 수 있게 된다.As described above, the ball grid array semiconductor package using the conductive ink according to the present invention has a deformable force even when the conductive ink having flexibility as the conductive trace is bent or warped by the external force when the printed circuit board is handled. It can have a strong resistance to, prevents errors in handling printed circuit boards, does not damage the electrical connection inside the package, and the thickness of the conductive traces can be applied to the substrate more lightly. It is possible to provide a thinner and more reliable circuit board and a semiconductor package using the same.
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990034330A KR20010018381A (en) | 1999-08-19 | 1999-08-19 | Circuit board using conductive ink and semiconductor package using the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990034330A KR20010018381A (en) | 1999-08-19 | 1999-08-19 | Circuit board using conductive ink and semiconductor package using the same |
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| KR20010018381A true KR20010018381A (en) | 2001-03-05 |
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| KR1019990034330A KR20010018381A (en) | 1999-08-19 | 1999-08-19 | Circuit board using conductive ink and semiconductor package using the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100731228B1 (en) * | 2002-03-05 | 2007-06-22 | 메탈 포밍 앤드 코이닝 코포레이션 | Method of making pinion carrier for planetary gear train |
| KR100788340B1 (en) * | 2001-04-12 | 2007-12-27 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package |
| US7625781B2 (en) | 2005-02-15 | 2009-12-01 | Infineon Technologies Ag | Semiconductor device having a plastic housing and external connections and method for producing the same |
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| KR19980068016A (en) * | 1997-02-14 | 1998-10-15 | 황인길 | Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof |
| KR19990016613A (en) * | 1997-08-18 | 1999-03-15 | 이해규 | VISAI Semiconductor Package |
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| KR960013968A (en) * | 1994-10-19 | 1996-05-22 | 이희종 | Military management method of elevator |
| JPH08236665A (en) * | 1995-02-28 | 1996-09-13 | Citizen Watch Co Ltd | Resin sealed semiconductor device and manufacture thereof |
| KR19980068016A (en) * | 1997-02-14 | 1998-10-15 | 황인길 | Ball Grid Array (BGA) Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof |
| KR19990016613A (en) * | 1997-08-18 | 1999-03-15 | 이해규 | VISAI Semiconductor Package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100788340B1 (en) * | 2001-04-12 | 2007-12-27 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Package |
| KR100731228B1 (en) * | 2002-03-05 | 2007-06-22 | 메탈 포밍 앤드 코이닝 코포레이션 | Method of making pinion carrier for planetary gear train |
| US7625781B2 (en) | 2005-02-15 | 2009-12-01 | Infineon Technologies Ag | Semiconductor device having a plastic housing and external connections and method for producing the same |
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