CN101958292B - Printed circuit board, encapsulation piece and manufacture methods thereof - Google Patents
Printed circuit board, encapsulation piece and manufacture methods thereof Download PDFInfo
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- CN101958292B CN101958292B CN2009101517796A CN200910151779A CN101958292B CN 101958292 B CN101958292 B CN 101958292B CN 2009101517796 A CN2009101517796 A CN 2009101517796A CN 200910151779 A CN200910151779 A CN 200910151779A CN 101958292 B CN101958292 B CN 101958292B
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- insulated substrate
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- connecting hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The invention relates to a printed circuit board, an encapsulation piece and manufacturing methods thereof. The printed circuit board comprises at least one insulating substrate, a wiring layer, and a lead, wherein the at least one insulating substrate comprises a connecting hole formed to pass through the at least one insulating substrate; the wiring layer is formed on the surface of the at least one insulating substrate and has an exposed surface exposed through the connecting hole; a bonding pad is formed on the wiring layer; and the lead electrically connects the bonding pad formed on the exposed surface to other bonding pads.
Description
Technical field
The present invention relates to a kind of printed circuit board (PCB), a kind of packaging part and manufacturing approach thereof that comprises said printed circuit board (PCB).
Background technology
Printed circuit board (PCB) (PCB) is widely used in the various electronic equipments as the carrier of electronic component.For example, in the packaging part with chip (for example, semiconductor chip), chip is fixed on the PCB, and is electrically connected to the wiring layer on the PCB.Usually, in PCB, be formed with connecting hole, form conductive layer at the inner surface of connecting hole through electroplating technology, thus the electrical connection between the wiring layer on the different surfaces of the insulated substrate of realization PCB.
Figure 1A to Fig. 1 H is the cutaway view that illustrates according to the method for the manufacturing PCB 100 of prior art.
Shown in Figure 1A, at first prepare insulated substrate (base material) 110.Then, metal level 120 ' can on the surface of insulated substrate 110, be formed, shown in Figure 1B.Can on two surfaces of insulated substrate 110, form metal level 120 '.Can form metal level 120 ' through printing (print) technology utilization copper (Cu).
Shown in Fig. 1 C, can go up at metal level 120 ' and form dry film (dry film) 123.Through dry film 123 is made public, develops, thereby with dry film 123 patternings.Then, the structure shown in Fig. 1 C is carried out etching and removed dry film 123, thereby form wiring layer 120, shown in Fig. 1 D.Shown in Fig. 1 E, can on wiring layer 120, form insulating barrier 125 to cover wiring layer 120.Therefore, extra metal level 120 ' can on insulating barrier 125, be formed, shown in Fig. 1 F.
Then, can form connecting hole 130, shown in Fig. 1 G.Generally, connecting hole 130 is formed pass resulting structures.Then, in order to be electrically connected each wiring layer 120 and/or metal level 120 ', can on the inner surface of connecting hole 130, form metal level 140 through electroplating technology.For example, can utilize copper to form metal level 140 through electroplating technology, shown in Fig. 1 G.Shown in Fig. 1 H; After having formed connecting hole 130 and metal level 140; Can be through above-described technology with metal level 120 ' patterning, thus wiring layer formed, can on resulting structures, apply solder mask 160; And pass through exposure, developing process, and form pad 150 at the electroplating technology that on the surface of solder mask 160 exposures, passes through of wiring layer 120 with solder mask 160 patternings.
Through carrying out the technology of describing with reference to Figure 1A to Fig. 1 H, can form the PCB 100 of connecting hole, shown in Fig. 1 H with plating.In the method for the traditional manufacturing PCB that as above describes, connecting hole 130 is carried out electroplating technology, to be electrically connected each wiring layer 120 with reference to Figure 1A to Fig. 1 H.Yet such electroplating technology can increase the manufacturing cost of PCB.Simultaneously, the connecting hole of plating can produce parasitic capacitance, the feasible electric property deterioration that adopts the electronic equipment (chip package that for example, comprises such PCB) of such PCB.
Summary of the invention
Many aspects of the present invention provide a kind of printed circuit board (PCB) (PCB), a kind of packaging part and manufacturing approach thereof that comprises said PCB; In said PCB; Not to adopt electroplating technology but employing lead-in wire incoming call connecting wiring layer; Thereby reduced the manufacturing cost of PCB, and prevented parasitic capacitance, therefore improved the electric property of the electronic equipment that adopts said PCB by the connecting hole generation of electroplating.
One side of the present invention provides a kind of packaging part; Said packaging part comprises: printed circuit board (PCB); Comprise at least one insulated substrate, wiring layer, pad, said at least one insulated substrate comprises and forms the connecting hole that passes said at least one insulated substrate that said wiring layer is formed on the surface of said at least one insulated substrate; And having the exposed surface that exposes through said connecting hole, said pad is formed on the said wiring layer; Chip is arranged on said at least one insulated substrate, and said chip has input/output terminal; Lead-in wire is with being formed on pad or the said input/output terminal that pad on the said exposed surface is electrically connected to other; Encapsulated layer is sealed said chip and said lead-in wire.
Another aspect of the present invention provides a kind of method of manufacturing and encapsulation part, and said method comprises the steps: to prepare insulated substrate; In said insulated substrate, form the connecting hole that passes said insulated substrate; On the surface of said insulated substrate, form wiring layer, said wiring layer forms has the exposed surface that exposes through said connecting hole; On said wiring layer, form pad; On said insulated substrate, chip is set, said chip has input/output terminal; Utilize lead-in wire will be formed on pad on the said exposed surface and be electrically connected to other pad or said input/output terminal; Utilize encapsulating material to seal said chip and said lead-in wire.
Another aspect of the present invention provides a kind of printed circuit board (PCB), and said printed circuit board (PCB) comprises: at least one insulated substrate, said at least one insulated substrate comprise and form the connecting hole that passes said at least one insulated substrate; Wiring layer is formed on the surface of said at least one insulated substrate, and has the exposed surface that exposes through said connecting hole; Pad is formed on the said wiring layer; Lead-in wire is with being formed on the pad that pad on the said exposed surface is electrically connected to other.
Another aspect of the present invention provides a kind of method of making printed circuit board (PCB), and said method comprises the steps: to prepare insulated substrate; In said insulated substrate, form the connecting hole that passes said insulated substrate; On the surface of said insulated substrate, form wiring layer, said wiring layer forms has the exposed surface that exposes through said connecting hole; On said wiring layer, form pad; Utilize lead-in wire will be formed on pad on the said exposed surface and be electrically connected to other pad.
Description of drawings
Through describing embodiments of the invention in detail below in conjunction with accompanying drawing, above-mentioned and/or other aspects, characteristic and advantage of the present invention will become clearer and be easier to understand, in the accompanying drawing:
Figure 1A to Fig. 1 H is the cutaway view that illustrates according to the method for the manufacturing printed circuit board (PCB) (PCB) of prior art;
Fig. 2 is the cutaway view that illustrates according to the PCB of the embodiment of the invention;
Fig. 3 A and Fig. 3 B are the cutaway views that PCB according to other embodiments of the present invention is shown;
Fig. 4 A to Fig. 4 F is the cutaway view that illustrates according to the method for the manufacturing PCB of the embodiment of the invention;
Fig. 5 is the cutaway view that illustrates according to the packaging part of the embodiment of the invention;
Fig. 6 A and Fig. 6 B are the cutaway views that packaging part according to other embodiments of the present invention is shown;
Fig. 7 A and Fig. 7 B are the cutaway views that illustrates according to the method for the manufacturing and encapsulation part of the embodiment of the invention.
Embodiment
Hereinafter, will describe embodiments of the invention in detail with reference to accompanying drawing.Yet the present invention can implement with many different forms, and should not be limited to the embodiment that sets forth here.On the contrary, provide these embodiment to make that the disclosure will be thoroughly also complete, and will make scope of the present invention convey to those skilled in the art fully.For the sake of clarity, size and the relative size in layer and zone have been exaggerated in the accompanying drawings.In the accompanying drawings, identical label is represented components identical all the time.
Now, will describe printed circuit board (PCB) (PCB) and manufacturing approach thereof in detail with reference to Fig. 2 to Fig. 4 F according to the embodiment of the invention.
Fig. 2 is the cutaway view that illustrates according to the PCB of the embodiment of the invention.
As shown in Figure 2, can comprise insulated substrate 210, wiring layer 220, connecting hole 230, lead-in wire 240, pad 250 according to the PCB 200 of the embodiment of the invention.PCB 200 can be used for the manufacturing and encapsulation part, for example, can chip be fixed on the PCB 200, comprises the packaging part of PCB 200 then through lead-in wire connection technology and encapsulating process manufacturing.
Insulated substrate 210 can have writing board shape.Insulated substrate 210 can be by electricity such as plastics, bakelite for example, thermal insulation is good and on-deformable material is processed.
Connecting hole 230 can form and pass insulated substrate 210.Connecting hole 230 can form through punching apparatus or rig.Connecting hole 230 can have the cross section of arbitrary shape, for example, and circle, rectangle, triangle, polygon etc.Preferably, connecting hole 230 can have the cross section of diameter more than or equal to the circle of 0.2mm, thereby allows in the process of making PCB 200, feedthrough connector to be insinuated in the connecting hole 230.Connecting hole 230 can expose the surface of wiring layer 220, hereinafter, the surface through connecting hole 230 exposes of wiring layer 220 is called exposed surface 221.
The material of lead-in wire 240 can comprise electric conducting material and/or their alloys such as gold, silver, copper.Lead-in wire 240 can be electrically connected pad 250.One end of lead-in wire 240 can be connected to preformed soldered ball on the pad 250, and the other end of lead-in wire 240 can be connected to preformed soldered ball on another pad 250.For example, thus a lead-in wire end of 240 can be through being insinuated into the feedthrough connector (not shown) pad 250 that is connected in the connecting hole 230 on the exposed surface 221.
Fig. 3 A and Fig. 3 B are the cutaway views that PCB according to other embodiments of the present invention is shown.
Shown in Fig. 3 A, except solder mask 260, PCB 201 can be identical with the PCB 200 shown in Fig. 2 according to another embodiment of the present invention.Solder mask 260 can cover the surface of PCB 201, to protect wiring layer 220 and to prevent short circuit.Solder mask 260 can expose the part on the surface of wiring layer 220, and pad 250 can be formed on the said part of wiring layer 220.
Can be multi-layer PCB according to PCB of the present invention.For example, Fig. 3 B shows the multi-layer PCB 202 that range upon range of a plurality of insulated substrates 210 with wiring layer 220 and connecting hole 230 obtain that passes through according to the embodiment of the invention.Shown in Fig. 3 B, under the situation of multi-layer PCB 202, connecting hole 230 can be via hole 231 that passes all insulated substrates 210 and/or the blind hole 232 of passing a part of insulated substrate 210.Wiring layer 220 on the outer surface that is formed on a plurality of insulated substrates 210 that via hole 231 can expose.Blind hole 232 can expose the wiring layer 220 that is formed between a plurality of insulated substrates 210.Selectively, multi-layer PCB 202 also can comprise solder mask 260.
Fig. 4 A to Fig. 4 F is the cutaway view that illustrates according to the method for the manufacturing PCB of the embodiment of the invention.Below, will describe method in detail with reference to Fig. 4 A to Fig. 4 F according to the manufacturing PCB of the embodiment of the invention.
Shown in Fig. 4 A, prepare insulated substrate 210.Can be by electricity such as plastics, bakelite for example, thermal insulation is good and on-deformable material is made the insulated substrate 210 of writing board shape.
Then, in insulated substrate 210, form connecting hole 230, shown in Fig. 4 B.Can form the connecting hole 230 that passes insulated substrate 210 through punching apparatus or rig.Can connecting hole 230 be formed the cross section with arbitrary shape, for example, circle, rectangle, triangle, polygon etc.Preferably, can connecting hole 230 be formed and have the cross section of diameter, thereby allow in the technology of back, feedthrough connector to be insinuated in the connecting hole 230 more than or equal to the circle of 0.2mm.
Shown in Fig. 4 C, on the insulated substrate that is formed with connecting hole 230 210, form wiring layer 220.For example, can on two surfaces of insulated substrate 210, form wiring layer 220.Thereby help the quantity that circuit design also increases the electronic building brick that can install.Can utilize electric conducting materials such as copper, tin, silver, gold and/or their alloy to form wiring layer 220.Can wait wiring layer 220 patternings through etch process, thereby realize that various circuit connect.Can wiring layer be formed makes connecting hole 230 can expose the exposed surface 221 of wiring layer 220.
Though do not illustrate; But can on wiring layer 220, form insulating barrier to cover wiring layer 220; And can on said insulating barrier, replace range upon range of extra wiring layer and/or extra insulating barrier, wherein, insulating barrier makes and is electrically insulated from each other between each wiring layer.Therefore, increase the area of wiring layer, helped circuit design.
Then, pad 250 can on the part on the surface of wiring layer 220, be formed, shown in Fig. 4 D.For example, can on exposed surface 221, form pad 250.Can utilize Ni/Au to pass through electroplating technology and form pad 250.
Shown in Fig. 4 E, can utilize lead-in wire 240 to be electrically connected pad 250, thereby form PCB as shown in Figure 2 200.Can form lead-in wire 240 by electric conducting material such as gold, silver, copper and/or their alloy.Can connect lead-in wire 240 like this, that is, can on pad 250, form soldered ball in advance, can a lead-in wire end of 240 be connected to a soldered ball on the pad 250 then, and 240 the other end of will going between is connected to the soldered ball on another pad 250.For example, can the feedthrough connector (not shown) be insinuated in the connecting hole 230, be connected to the pad 250 on the exposed surface 221 of wiring 220 with 240 the end of will going between.Because the cross section of connecting hole 230 preferably can be the circle of diameter more than or equal to 0.2mm, pad 250 that an end of 240 is connected on the exposed surface 221 is easy so utilize feedthrough connector to go between.
Therefore, can connect technology through above-mentioned lead-in wire and make PCB 200 with predetermining circuit connection.
Selectively, shown in Fig. 4 F, before forming pad 250, can on the surface of the structure shown in Fig. 4 C, form solder mask 260, to protect wiring layer 220 and to prevent short circuit.Solder mask 260 can expose the part on the surface of wiring layer 220, thus after step in can on said part, form pad 250.Therefore, can make PCB 201 shown in Fig. 3 A.
According to another embodiment of the present invention, can range upon range of a plurality of insulated substrates 210 shown in Fig. 4 C with wiring layer 220 and connecting hole 230.In this case, can connecting hole 230 be formed via hole 231 that passes all insulated substrates 210 and/or the blind hole 232 of passing a part of insulated substrate 210.Wiring layer 220 on the outer surface that is formed on a plurality of insulated substrates 210 that via hole 231 can expose.Blind hole 232 can expose the wiring layer 220 that is formed between a plurality of insulated substrates 210.Therefore, can form multi-layer PCB 202 shown in Fig. 3 B with a plurality of insulated substrate 210, a plurality of wiring layer 220, a plurality of connecting hole 230.According to another embodiment of the present invention, via hole 231 can form after the step of range upon range of structure shown in Fig. 4 C, thereby practices thrift manufacturing cost, raising product yield.In addition, will can after forming via hole 231, form through the wiring layer 220 that via hole 231 exposes.
Now, will describe packaging part and manufacturing approach thereof in detail with reference to Fig. 5 to Fig. 7 B according to the embodiment of the invention.For fear of redundancy, the assembly identical with step and the detailed description of step have been omitted hereinafter with the assembly of describing with reference to Fig. 2 to Fig. 4 F.
Fig. 5 is the cutaway view that illustrates according to the packaging part of the embodiment of the invention.
As shown in Figure 5, can comprise PCB 200, chip 570, encapsulated layer 580 according to the packaging part 500 of the embodiment of the invention.PCB 200 can be PCB as shown in Figure 2 200, and PCB 200 can comprise insulated substrate 210, wiring layer 220, connecting hole 230, lead-in wire 240, pad 250.
The input/output terminal 571 of chip 570 can 240 be electrically connected to pad 250 through going between.Specifically, an end of lead-in wire 240 can be connected to preformed soldered ball on the pad 250, and the other end of lead-in wire 240 can be connected to the input/output terminal 571 of chip 570.For example, thus a lead-in wire end of 240 can be through being insinuated into the feedthrough connector (not shown) pad 250 that is connected in the connecting hole 230 on the exposed surface 221.
Encapsulated layer 580 can encapsulate chip 570 with lead-in wire 240, thereby prevent that chip 570 and lead-in wire 240 are exposed to the outside.Encapsulated layer 580 can be formed by encapsulating materials such as for example epoxy resin.
Fig. 6 A and Fig. 6 B are the cutaway views that packaging part according to other embodiments of the present invention is shown.
Shown in Fig. 6 A, packaging part 501 can comprise the PCB 201 shown in Fig. 3 A according to another embodiment of the present invention.In this case, chip 570 can be fixed on the solder mask 260.Selectively, the soldered ball 590 that is used for being electrically connected with other element can be formed on pad 250.
Shown in Fig. 6 B, packaging part 502 can comprise the multi-layer PCB 202 shown in Fig. 3 B according to another embodiment of the present invention.In addition, the soldered ball 590 that is used for being electrically connected with other element can be formed on pad 250.
Fig. 7 A and Fig. 7 B are the cutaway views that illustrates according to the method for the manufacturing and encapsulation part of the embodiment of the invention.Below, will describe method in detail with reference to Fig. 7 A and Fig. 7 B according to the manufacturing and encapsulation part of the embodiment of the invention.
At first, can carry out the top technology of describing with reference to Fig. 4 A to Fig. 4 F and make PCB 200.Then, can utilize tack coat that chip 570 is fixed on the PCB 200 and (for example, chip 570 is fixed on the insulated substrate 210), thereby form the structure shown in Fig. 7 A.Can utilize lead-in wire 240 to be electrically connected the input/output terminal 571 of pad 250 and chip 570 then.
Can connect lead-in wire 240 like this, that is, can on pad 250, form soldered ball in advance, can a lead-in wire end of 240 be connected to a soldered ball on the pad 250 then, and 240 the other end of will going between is connected to the input/output terminal 571 of chip 570.For example, can the feedthrough connector (not shown) be insinuated in the connecting hole 230, be connected to the pad 250 on the exposed surface 221 of wiring layer 220 with 240 the end of will going between.Because the cross section of connecting hole 230 preferably can be the circle of diameter more than or equal to 0.2mm, pad 250 that an end of 240 is connected on the exposed surface 221 is easy so utilize feedthrough connector to go between.
Then, can on resulting structures, utilize encapsulating material to form encapsulated layer, with encapsulate chip 570 and lead-in wire 240.Thereby accomplish packaging part as shown in Figure 5 500.
Describe in the above in the method for manufacturing and encapsulation part 500; In the process of making PCB 200, carry out first lead-in wire and connected technology (promptly; Be electrically connected the technology of pads 250 with reference to the utilization lead-in wire 240 of Fig. 4 E description); In the process of utilizing PCB 200 manufacturing and encapsulation parts 500, carry out the second lead-in wire connection technology (that is, describing the technology of utilization lead-in wire 240) then with input/output terminal 571 electrical connections of pad 250 and chip with reference to Fig. 7 A.
According to another embodiment of the present invention, can carry out above-mentioned technology with different orders.For example, at first, can make the structure shown in Fig. 4 D.Then, can utilize tack coat that chip 570 is fixed on the structure shown in Fig. 4 D and (for example, chip 570 is fixed on the insulated substrate 210), thereby obtain the structure shown in Fig. 7 B.Then, can carry out the technology (second goes between is connected technology) of utilizing lead-in wire to be electrically connected the technology (first lead-in wire connects technology) of pad and utilizing lead-in wire that the input/output terminal 571 of pad and chip is electrically connected simultaneously.That is, in the process of making PCB, do not carry out lead-in wire and connect technology, connect technology but in the process of manufacturing and encapsulation part 500, only carry out once lead-in wire.Therefore, can reduce manufacturing cost, increase the product yield, improve output.
Then, can on resulting structures, utilize encapsulating material to form encapsulated layer, with encapsulate chip 570 and lead-in wire 240.Thereby accomplish packaging part as shown in Figure 5 500.
Describe the method for making the packaging part that comprises PCB 200 500 as shown in Figure 5 above in detail.But for a person skilled in the art,, can make the packaging part that comprises PCB201 and PCB202 501 and the method for packaging part 502 shown in Fig. 6 A and 6B through said method is made amendment.For example, can before forming pad, form solder mask, and in the technology of back, chip is fixed on the solder mask.Then, can on pad, be formed for the soldered ball that is electrically connected with other element, thereby produce the packaging part that comprises PCB 201 501 shown in Fig. 6 A.A plurality of insulated substrates that perhaps, can range upon range ofly have wiring layer and connecting hole.In this case, can connecting hole be formed via hole that passes all insulated substrates and/or the blind hole of passing a part of insulated substrate, thereby produce the packaging part that comprises multi-layer PCB 202 502 shown in Fig. 6 B.
PCB according to the present invention with comprise in the packaging part of said PCB; Not to adopt electroplating technology but employing lead-in wire incoming call connecting wiring layer; Thereby reduced the manufacturing cost of PCB; And prevented parasitic capacitance by the connecting hole generation of electroplating, therefore improved the electric property of the electronic equipment that adopts said PCB.
Though described exemplary embodiment of the present invention; But it should be understood that; The invention is not restricted to these exemplary embodiments, and in the spirit and scope of the present invention of protecting like claim, those of ordinary skills can carry out various changes and modification.
Claims (18)
1. packaging part, said packaging part comprises:
Printed circuit board (PCB); Comprise at least one insulated substrate, wiring layer, pad; Said at least one insulated substrate comprises and forms the connecting hole that passes said at least one insulated substrate; Said wiring layer is formed on the surface of said at least one insulated substrate, and has the exposed surface that exposes through said connecting hole, and said pad is formed on the said wiring layer;
Chip is arranged on said at least one insulated substrate, and said chip has input/output terminal;
A plurality of leads; Comprise the lead-in wire between the input/output terminal of the pad that is connected on the said exposed surface and chip and be connected pad and the lead-in wire between other the pad on the said exposed surface, be electrically connected to other pad or said input/output terminal thereby will be formed on pad on the said exposed surface through lead-in wire;
Encapsulated layer is sealed said chip and said lead-in wire.
2. packaging part as claimed in claim 1, wherein, said connecting hole has the cross section of diameter more than or equal to the circle of 0.2mm.
3. packaging part as claimed in claim 1, said packaging part also comprises:
Solder mask is formed on the surface of said printed circuit board (PCB), and exposes said pad,
Wherein, said chip is arranged on the said solder mask.
4. packaging part as claimed in claim 1, said packaging part also comprises:
Soldered ball is formed on the said pad.
5. packaging part as claimed in claim 1; Wherein, Said at least one insulated substrate is the range upon range of a plurality of insulated substrates that are formed with wiring layer and connecting hole; Said connecting hole is included as via hole that passes all insulated substrates in said a plurality of insulated substrate and the blind hole of passing a part of insulated substrate in said a plurality of insulated substrate; Said via hole exposes the wiring layer on the outer surface that is formed on said a plurality of insulated substrates, and said blind hole exposes and is formed on the wiring layer between said a plurality of insulated substrate.
6. the method for a manufacturing and encapsulation part, said method comprises the steps:
Prepare insulated substrate;
In said insulated substrate, form the connecting hole that passes said insulated substrate;
On the surface of said insulated substrate, form wiring layer, said wiring layer forms has the exposed surface that exposes through said connecting hole;
On said wiring layer, form pad;
On said insulated substrate, chip is set, said chip has input/output terminal;
The pad on the said exposed surface of utilization lead-in wire connection and the input/output terminal of chip; And utilize lead-in wire to connect pad and other pad on the said exposed surface, will be formed on perhaps said input/output terminal of pad that pad on the said exposed surface is electrically connected to other;
Utilize encapsulating material to seal said chip and said lead-in wire.
7. method as claimed in claim 6, wherein, the step that forms said connecting hole comprises:
Through punching technology or bore process said connecting hole is formed and to have the cross section of diameter more than or equal to the circle of 0.2mm.
8. method as claimed in claim 6, said method also comprises:
After forming the step of said wiring layer, form solder mask having on the said insulated substrate of said wiring layer, exposing the part that will be formed with said pad of said wiring layer,
Wherein, said chip is set on said solder mask.
9. method as claimed in claim 6, said method also comprises:
After the step of sealing said chip and said lead-in wire, on said pad, form soldered ball.
10. method as claimed in claim 6, said method also comprises:
After the step that forms said wiring layer; The range upon range of a plurality of insulated substrates that are formed with wiring layer and connecting hole; Thereby said connecting hole is formed via hole that passes all insulated substrates in said a plurality of insulated substrate and the blind hole of passing a part of insulated substrate in said a plurality of insulated substrate; Said via hole exposes the wiring layer on the outer surface that is formed on said a plurality of insulated substrates, and said blind hole exposes and is formed on the wiring layer between said a plurality of insulated substrate.
11. a printed circuit board (PCB), said printed circuit board (PCB) comprises:
At least one insulated substrate, said at least one insulated substrate comprise and form the connecting hole that passes said at least one insulated substrate;
Wiring layer is formed on the surface of said at least one insulated substrate, and has the exposed surface that exposes through said connecting hole;
Pad is formed on the said wiring layer;
Lead-in wire is connected between the pad and other pad on the said exposed surface, will be formed on the pad that pad on the said exposed surface is electrically connected to other.
12. printed circuit board (PCB) as claimed in claim 11, wherein, said connecting hole has the cross section of diameter more than or equal to the circle of 0.2mm.
13. printed circuit board (PCB) as claimed in claim 11, said printed circuit board (PCB) also comprises:
Solder mask is formed on the surface of said printed circuit board (PCB), and exposes said pad,
Wherein, chip will be set on the said solder mask.
14. printed circuit board (PCB) as claimed in claim 11; Wherein, Said at least one insulated substrate is the range upon range of a plurality of insulated substrates that are formed with wiring layer and connecting hole; Said connecting hole comprises via hole that passes all insulated substrates in said a plurality of insulated substrate and the blind hole of passing a part of insulated substrate in said a plurality of insulated substrate; Said via hole exposes the wiring layer on the outer surface that is formed on said a plurality of insulated substrates, and said blind hole exposes and is formed on the wiring layer between said a plurality of insulated substrate.
15. a method of making printed circuit board (PCB), said method comprises the steps:
Prepare insulated substrate;
In said insulated substrate, form the connecting hole that passes said insulated substrate;
On the surface of said insulated substrate, form wiring layer, said wiring layer forms has the exposed surface that exposes through said connecting hole;
On said wiring layer, form pad;
Utilize lead-in wire to connect pad and other pad on the said exposed surface, will be formed on the pad that pad on the said exposed surface is electrically connected to other.
16. method as claimed in claim 15, wherein, the step that forms said connecting hole comprises:
Through punching technology or bore process said connecting hole is formed and to have the cross section of diameter more than or equal to the circle of 0.2mm.
17. method as claimed in claim 15, said method also comprises:
After forming the step of said wiring layer, form solder mask having on the said insulated substrate of said wiring layer, exposing the part that will form said pad of said wiring layer,
Wherein, will on said solder mask, chip be set.
18. method as claimed in claim 15, said method also comprises:
After the step that forms said wiring layer; The range upon range of a plurality of insulated substrates that are formed with wiring layer and connecting hole; Thereby said connecting hole is formed via hole that passes all insulated substrates in said a plurality of insulated substrate and the blind hole of passing a part of insulated substrate in said a plurality of insulated substrate; Said via hole exposes the wiring layer on the outer surface that is formed on said a plurality of insulated substrates, and said blind hole exposes and is formed on the wiring layer between said a plurality of insulated substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101517796A CN101958292B (en) | 2009-07-15 | 2009-07-15 | Printed circuit board, encapsulation piece and manufacture methods thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101517796A CN101958292B (en) | 2009-07-15 | 2009-07-15 | Printed circuit board, encapsulation piece and manufacture methods thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101958292A CN101958292A (en) | 2011-01-26 |
| CN101958292B true CN101958292B (en) | 2012-11-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101517796A Expired - Fee Related CN101958292B (en) | 2009-07-15 | 2009-07-15 | Printed circuit board, encapsulation piece and manufacture methods thereof |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160090705A (en) * | 2015-01-22 | 2016-08-01 | 에스케이하이닉스 주식회사 | Package substrate, and semiconductor package using the package substrate |
| US11282811B2 (en) * | 2020-05-13 | 2022-03-22 | Micron Technology, Inc. | Integrated circuit wire bonded to a multi-layer substrate having an open area that exposes wire bond pads at a surface of the inner layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797758A (en) * | 2004-12-30 | 2006-07-05 | 三星电机株式会社 | Bga package having half-etched bonding pad and cut plating line and method of fabricating same |
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2009
- 2009-07-15 CN CN2009101517796A patent/CN101958292B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797758A (en) * | 2004-12-30 | 2006-07-05 | 三星电机株式会社 | Bga package having half-etched bonding pad and cut plating line and method of fabricating same |
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| Publication number | Publication date |
|---|---|
| CN101958292A (en) | 2011-01-26 |
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