JPH0473297B2 - - Google Patents
Info
- Publication number
- JPH0473297B2 JPH0473297B2 JP58083187A JP8318783A JPH0473297B2 JP H0473297 B2 JPH0473297 B2 JP H0473297B2 JP 58083187 A JP58083187 A JP 58083187A JP 8318783 A JP8318783 A JP 8318783A JP H0473297 B2 JPH0473297 B2 JP H0473297B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- external electrode
- package
- mold layer
- resin mold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000011347 resin Substances 0.000 claims description 32
- 229920005989 resin Polymers 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 6
- 230000017525 heat dissipation Effects 0.000 description 14
- 239000004020 conductor Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910002549 Fe–Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置と、この半導体装置を載
置する載置部と、外部電極と、上記半導体装置及
び上記外部電極にそれぞれ接続されている接続用
細線と、上記半導体装置、上記載置部、上記外部
電極及び上記接続用細線を上下から一体にモール
ドしている樹脂モールド層とをそれぞれ具備する
半導体装置のパツケージ及びその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, a mounting section on which the semiconductor device is placed, an external electrode, and a connection connected to the semiconductor device and the external electrode, respectively. The present invention relates to a package for a semiconductor device, which includes a thin wire for connection, and a resin mold layer in which the semiconductor device, the mounting portion, the external electrode, and the thin wire for connection are integrally molded from above and below, and a method for manufacturing the same.
背景技術とその問題点
従来、プリント基板上の実装密度の高いパツケ
ージとして、チツプキヤリアタイプのパツケージ
が知られている。このパツケージはリードレスタ
イプのパツケージで、パツケージの裏面に引き出
されているハンダ付け可能な電極をプリント基板
の導体パタンに直接ハンダ付けして接続すること
により実装を行うものである。BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, a chip carrier type package has been known as a package with high mounting density on a printed circuit board. This package is a leadless type package, and is mounted by directly soldering and connecting the solderable electrodes drawn out on the back side of the package to the conductor pattern of the printed circuit board.
このチツプキヤリアタイプパツケージには、セ
ラミツクタイプとプラスチツクタイプとがある。
セラミツクタイプはパツケージ自体が高価である
ばかりでなく、プリント基板に直接ハンダ付けす
ると、温度サイクル時にセラミツクスと上記ハン
ダ及び上記導体との間の熱膨張係数の差によつて
接続部にはがれやクラツクが生じる恐れがあると
いう欠点を有している。一方、プラスチツクタイ
プはパツケージが安価であるという利点を有して
いるが、熱放散性が悪く、また形状がパツケージ
の製造の自動化に適していないという欠点を有し
ている。 This chip carrier type package includes a ceramic type and a plastic type.
Not only is the ceramic type package itself expensive, but if it is soldered directly to a printed circuit board, the connection may peel or crack due to the difference in thermal expansion coefficient between the ceramic and the solder and conductor during temperature cycling. It has the disadvantage that it may occur. On the other hand, the plastic type has the advantage that the package is inexpensive, but has the disadvantage that it has poor heat dissipation properties and its shape is not suitable for automation of package manufacturing.
このような従来のプラスチツクタイプのチツプ
キヤリアタイプパツケージの構造を第１図に示
す。このパツケージ１は、銅箔製の電極２が予め
形成されているプリント基板３上に半導体装置を
構成するチツプ４を載置し、ワイヤボンデイング
法により上記チツプ４と上記電極２の一端とを
Auの細線から成るワイヤ５で接続した後、上方
より液状のエポキシ樹脂を滴下させて硬化成形す
ることによつて作る。 The structure of such a conventional plastic chip carrier type package is shown in FIG. In this package 1, a chip 4 constituting a semiconductor device is placed on a printed circuit board 3 on which an electrode 2 made of copper foil is formed in advance, and the chip 4 and one end of the electrode 2 are bonded together by wire bonding.
After connecting with a wire 5 made of a thin Au wire, liquid epoxy resin is dropped from above and hardened and molded.
このパツケージ１において、チツプ４は樹脂層
６とプリント基板３とによつて囲まれている。こ
れらの樹脂層６及びプリント基板３の熱抵抗は共
に大きいので、その動作時においてチツプ４で発
生する熱をパツケージ１の外部に効果的に放散す
ることができない。即ち、このパツケージ１は熱
放散性が悪いという欠点を有している。また上述
の液状のエポキシ樹脂を滴下する際に、微量の樹
脂を一定量、しかも高速で滴下することが難し
く、このためにこのパツケージ１はパツケージの
製造の自動化に適していないという欠点を有して
いる。 In this package 1, a chip 4 is surrounded by a resin layer 6 and a printed circuit board 3. Since both the resin layer 6 and the printed circuit board 3 have large thermal resistances, the heat generated in the chip 4 during operation cannot be effectively dissipated to the outside of the package 1. That is, this package 1 has the disadvantage of poor heat dissipation. Furthermore, when dropping the above-mentioned liquid epoxy resin, it is difficult to drop a small amount of resin at a constant rate and at a high speed, and for this reason, this package 1 has the disadvantage that it is not suitable for automation of package manufacturing. ing.
発明の目的
本発明は、上述の問題にかんがみ、熱放散性が
良好で、パツケージの製造の自動化に好適な半導
体装置のパツケージ及びその製造方法を提供する
ことを目的とする。OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device package that has good heat dissipation properties and is suitable for automation of package manufacturing, and a method for manufacturing the same.
発明の概要
本発明に係る半導体装置のパツケージは、半導
体装置と、この半導体装置を載置する載置部と、
外部電極と、上記半導体装置及び上記外部電極に
それぞれ接続されている接続用細線と、上記半導
体装置、上記載置部、上記外部電極及び上記接続
用細線を上下から一体にモールドしている樹脂モ
ールド層とをそれぞれ具備する半導体装置のパツ
ケージにおいて、上記樹脂モールド層の下面から
上記外部電極の下面に至るように上記樹脂モール
ド層に設けられた第１の欠如部と、上記樹脂モー
ルド層の下面から上記載置部の下面に至るように
上記樹脂モールド層に設けられた第２の欠如部と
をそれぞれ具備し、上記第１の欠如部によつて、
上記外部電極を上記樹脂モールド層から突出させ
ることなくこの樹脂モールド層の下面に露出させ
てリードレスタイプに構成すると共に、上記第２
の欠如部によつて、上記半導体装置に発生した熱
を上記第２の欠如部を通して外部に放散するよう
に構成している。このように構成することによつ
て、熱放散性を良好にすることができ、また、信
頼性を高くすることができると共に、パツケージ
の製造を自動化することができる。Summary of the Invention A package for a semiconductor device according to the present invention includes a semiconductor device, a mounting section on which the semiconductor device is mounted,
An external electrode, a thin connecting wire connected to the semiconductor device and the external electrode, respectively, and a resin mold in which the semiconductor device, the mounting section, the external electrode, and the thin connecting wire are integrally molded from above and below. In the semiconductor device package, the semiconductor device package includes a first cutout portion provided in the resin mold layer so as to extend from the lower surface of the resin mold layer to a lower surface of the external electrode, and and a second cutout provided in the resin mold layer so as to reach the lower surface of the placement part, and the first cutout allows for:
The external electrode is exposed on the lower surface of the resin mold layer without protruding from the resin mold layer to form a leadless type, and the second external electrode is configured as a leadless type.
The heat generated in the semiconductor device is dissipated to the outside through the second notch. With this configuration, it is possible to improve heat dissipation, improve reliability, and automate the manufacturing of the package.
また本発明に係る半導体装置のパツケージの製
造方法は、導電性基板に半導体装置載置部と外部
電極部とをそれぞれ設け、上記半導体装置載置部
に半導体装置を載置した後、接続用細線を上記半
導体装置と上記外部電極部とにそれぞれ接続し、
次いで、上記半導体装置、上記導電性基板の上記
外部電極部及び上記半導体装置載置部並びに上記
接続用細線を上下から一体に樹脂モールドし、し
かる後、上記樹脂モールド層の一部を除去して上
記外部電極部の少なくとも一部と上記半導体装置
載置部の少なくとも一部とを上記樹脂モールド層
の下面にそれぞれ露出させると共に、上記導電性
基板から上記半導体装置載置部及び上記外部電極
部をそれぞれ分離させるようにしている。このよ
うにすることによつて、熱放散性が良好でかつ信
頼性の高いリードレスタイプのパツケージを、簡
便かつ安価な方法によつて自動的に製造すること
ができる。 Further, in the method for manufacturing a semiconductor device package according to the present invention, a semiconductor device mounting portion and an external electrode portion are respectively provided on a conductive substrate, and after the semiconductor device is placed on the semiconductor device mounting portion, a thin connecting wire is are respectively connected to the semiconductor device and the external electrode section,
Next, the semiconductor device, the external electrode portion of the conductive substrate, the semiconductor device mounting portion, and the thin connection wire are integrally resin-molded from above and below, and then a part of the resin mold layer is removed. At least a portion of the external electrode section and at least a portion of the semiconductor device mounting section are exposed on the lower surface of the resin mold layer, and the semiconductor device mounting section and the external electrode section are exposed from the conductive substrate. I try to separate them from each other. By doing so, a leadless type package with good heat dissipation properties and high reliability can be automatically manufactured by a simple and inexpensive method.
実施例
以下本発明に係る半導体装置のパツケージ及び
その製造方法の１実施例につき図面を参照しなが
ら説明する。Embodiment Hereinafter, one embodiment of a semiconductor device package and a manufacturing method thereof according to the present invention will be described with reference to the drawings.
第２Ａ図〜第２Ｄ図は本発明の１実施例による
半導体装置のパツケージの製造方法を説明するた
めの工程図である。以下第２Ａ図から工程順に説
明する。 FIGS. 2A to 2D are process diagrams for explaining a method of manufacturing a package for a semiconductor device according to an embodiment of the present invention. The steps will be explained in the order of steps starting from FIG. 2A.
まず第２Ａ図において、第３図にこの平面図を
示す厚さ35〔μ〕の公知のFe−Cu合金製リードフ
レーム１１に半導体装置を構成するチツプ１２の
載置部１１ａと外部電極部１１ｂ，１１ｃとをそ
れぞれ設け、このチツプ載置部１１ａにチツプ１
２を載置した後、ワイヤボンデイング法によつて
このチツプ１２と上記外部電極部１１ｂ，１１ｃ
とをそれぞれAuの細線から成るワイヤ１３で接
続する。次に第２Ｂ図において、第２Ａ図のリー
ドフレーム１１をモールド金型に入れてエポキシ
樹脂によりトランスフア・モールド（移送成形）
する。本実施例においては、樹脂モールド層１４
におけるリードフレーム１１の下側モールド部分
１４ａの厚さt1が20〔μ〕に、またその上側モー
ルド部分１４ｂの厚さt2が１〔mm〕になるように
モールド金型を選んでいる。 First, in FIG. 2A, a mounting part 11a of a chip 12 constituting a semiconductor device and an external electrode part 11b are mounted on a known lead frame 11 made of Fe-Cu alloy with a thickness of 35 [μ] and whose plan view is shown in FIG. , 11c are provided respectively, and the chip 1 is placed on the chip mounting portion 11a.
2, this chip 12 and the external electrode portions 11b and 11c are bonded by wire bonding.
and are connected by wires 13 made of thin Au wires. Next, in FIG. 2B, the lead frame 11 shown in FIG. 2A is placed in a mold and transferred to an epoxy resin.
do. In this embodiment, the resin mold layer 14
The molds are selected so that the thickness t 1 of the lower mold portion 14a of the lead frame 11 is 20 [μ], and the thickness t 2 of the upper mold portion 14b is 1 [mm].
次に第２Ｃ図において、上記下側モールド部分
１４ａにリードフレーム１１に垂直な方向から公
知のYAGレーザビームを照射してレーザトリミ
ングを行うことによつて、上記下側モールド部分
１４ａに欠如部１５ａ，１５ｂ，１５ｃを形成す
る。後述するように、上記欠除部１５ｂ，１５ｃ
によつて露出された金属面が外部電極面１１ｅ，
１１ｆとなり、上記欠如部１５ａによつて露出さ
れた金属面が熱放散面１１ｄとなる。なお欠如部
１５ａの形状は例えば矩形または円形にすればよ
く、また欠如部１５ｂ，１５ｃの形状は例えば矩
形または半円形にすればよい。次に第２Ｄ図にお
いて、第３図に示す切断予定線１７に沿つてリー
ドフレーム１１の不要部分を切断除去することに
よつてチツプ載置部１１ａ及び外部電極部１１ｂ
を互いに分離して、リードレスタイプのパツケー
ジ１６を完成させる。 Next, in FIG. 2C, by irradiating the lower mold part 14a with a known YAG laser beam from a direction perpendicular to the lead frame 11 to perform laser trimming, a cutout 15a is formed in the lower mold part 14a. , 15b, 15c are formed. As described later, the cutout portions 15b, 15c
The metal surface exposed by the external electrode surface 11e,
11f, and the metal surface exposed by the cutout 15a becomes a heat dissipation surface 11d. Note that the shape of the cutout portion 15a may be, for example, a rectangle or a circle, and the shape of the cutout portions 15b and 15c may be, for example, a rectangle or a semicircle. Next, in FIG. 2D, unnecessary parts of the lead frame 11 are cut and removed along the cutting line 17 shown in FIG.
are separated from each other to complete a leadless type package 16.
上述のようにして完成されたパツケージ１６を
プリント基板上に実装する場合には、第２Ｄ図に
示す外部電極面１１ｅ，１１ｆをプリント基板上
の導体パタンに直接ハンダ付けして接続すればよ
い。 When the package 16 completed as described above is mounted on a printed circuit board, the external electrode surfaces 11e and 11f shown in FIG. 2D may be directly connected to the conductor pattern on the printed circuit board by soldering.
なお上述の実施例において、リードフレーム１
１の下側に下側モールド部分１４ａを設けるよう
にしたのは、チツプ載置部１１ａ及び外部電極部
１１ｂ，１１ｃをこれらの上下からモールドして
いる樹脂モールド層によつて互いに確実に固定す
ることによつて、パツケージ１６の使用時におい
てチツプ１２やワイヤ１３に無理な力が加わらな
いようにするためである。 Note that in the above embodiment, the lead frame 1
The reason why the lower molded portion 14a is provided below the chip mounting portion 11a and the external electrode portions 11b and 11c are securely fixed to each other by resin molding layers molded from above and below. In particular, this is to prevent excessive force from being applied to the chip 12 and wire 13 when the package 16 is used.
上述の実施例の熱放散面１１ｄは、その動作時
においてチツプ１２から発生する熱の放散面とな
つている。金属の熱伝導度は非常に高いので、チ
ツプ１２に発生する熱は金属製のチツプ載置部１
１ａを外方に向かつて迅速に流れて、熱放散面１
１ｄから放散されることによつて効果的に除去さ
れる。しかし、より効果的にチツプ１２の発生熱
を除去するためには、広い表面積を有する放熱フ
インの一端を上記熱放散面１１ｄに押し当てて空
冷により熱を放散させるのが好ましい。 The heat dissipation surface 11d of the above embodiment serves as a dissipation surface for the heat generated from the chip 12 during its operation. Since the thermal conductivity of metal is very high, the heat generated in the chip 12 is transferred to the metal chip mounting section 1.
1a to the outside and quickly flow to the heat dissipation surface 1.
It is effectively removed by being dissipated from 1d. However, in order to more effectively remove the heat generated by the chip 12, it is preferable to press one end of a heat dissipation fin having a large surface area against the heat dissipation surface 11d to dissipate the heat by air cooling.
また上述の実施例のパツケージ１６は第２Ａ図
〜第２Ｄ図に示すような簡単な工程によつて作る
ことができるばかりでなく、レーザトリミングに
よつて欠如部１５ａ，１５ｂ，１５ｃを形成する
ようにしているので、これらの欠如部１５ａ，１
５ｂ，１５ｃを形成するための複雑な形状のモー
ルド金型が不要である。従つて、簡便かつ安価な
方法によりパツケージ１６を作ることができる。
さらに上述の実施例では樹脂モールド層１４を形
成する方法としてトランスフア・モールド法（移
送成形法）を用いている。この方法は信頼性の高
い樹脂封止ができるばかりでなく、モールドの機
械化、量産化が容易であるためにパツケージを自
動的に製造できるという利点を有している。 Furthermore, the package 16 of the above-described embodiment can not only be made by a simple process as shown in FIGS. 2A to 2D, but also the cutouts 15a, 15b, and 15c can be formed by laser trimming. Therefore, these missing parts 15a, 1
A mold with a complicated shape is not required to form the parts 5b and 15c. Therefore, the package 16 can be made by a simple and inexpensive method.
Further, in the above embodiment, a transfer molding method is used as a method for forming the resin mold layer 14. This method not only enables highly reliable resin sealing, but also has the advantage that it is easy to mechanize the mold and mass-produce the package, so that the package can be manufactured automatically.
また下側モールド部分１４ａの欠如部１５ｂ，
１５ｃは、上述の実施例においては下側モールド
部分１４ａの外周囲に接続して設けられている
が、必ずしもこのように構成する必要はなく、例
えばリードフレーム１１の外部電極部１１ｂ，１
１ｃを覆つている下側モールド部分１４ａに、上
記リードフレーム１１に垂直な方向の貫通孔を形
成することによつて、上記欠如部１５ｂ，１５ｃ
を上記外周囲よりも内側に設けてもよい。 Also, the missing portion 15b of the lower mold portion 14a,
15c is provided connected to the outer periphery of the lower mold portion 14a in the above-described embodiment, but it does not necessarily have to be configured in this way. For example, the external electrode portions 11b, 1 of the lead frame 11
By forming a through hole in a direction perpendicular to the lead frame 11 in the lower mold portion 14a covering the lead frame 1c, the missing portions 15b, 15c are formed.
may be provided inside the outer periphery.
上述の実施例においては、樹脂材料としてエポ
キシを用いたが、シリコーン等の他の樹脂を用い
ても勿論よい。またリードフレーム１１の材料も
実施例で用いた材料に限定されるものではなく、
例えばコバールのような他の導電性材料を用いて
もよい。さらに欠如部１５ａ，１５ｂ，１５ｃは
YAGレーザ以外の例えばCO2レーザのような他
のレーザを用いて形成してもよいことは勿論、例
えばサンドブラストのようなレーザとは異なる方
法を用いて形成してもよい。なお上記欠如部１５
ａ，１５ｂ，１５ｃを形成する場合には、外部電
極面１１ｅ，１１ｆ及び熱放散面１１ｄに損傷を
与えないように、例えばレーザを用いる場合には
レーザビームのパワーを適当な値に選定する必要
があることは言うまでもない。 In the above embodiments, epoxy was used as the resin material, but other resins such as silicone may of course be used. Further, the material of the lead frame 11 is not limited to the material used in the embodiment,
Other conductive materials such as Kovar may also be used. Furthermore, the missing parts 15a, 15b, 15c are
It goes without saying that a laser other than the YAG laser, such as a CO 2 laser, may be used for formation, and a method other than the laser, such as sandblasting, may be used for formation. Note that the missing portion 15
When forming the external electrode surfaces 11e, 11f and the heat dissipating surface 11d, for example, when using a laser, the power of the laser beam must be selected to an appropriate value so as not to damage the external electrode surfaces 11e, 11f and the heat dissipation surface 11d. Needless to say, there is.
発明の効果
本発明に係る半導体装置のパツケージは、半導
体装置に発生した熱を、樹脂モールド層の下面か
ら半導体装置載置部に至るように樹脂モールド層
に設けられた欠如部を通じて外部に放散すること
ができるので、熱放散性が高くて、半導体装置の
発熱量が大きい場合でも十分な熱放散を行うこと
ができる。Effects of the Invention The semiconductor device package according to the present invention dissipates heat generated in the semiconductor device to the outside through the cutout provided in the resin mold layer from the bottom surface of the resin mold layer to the semiconductor device mounting portion. Therefore, the heat dissipation property is high, and even when the semiconductor device generates a large amount of heat, sufficient heat dissipation can be performed.
また、半導体装置、その載置部、外部電極及び
接続用細線を上下から一体にモールドしている樹
脂モールド層を具備するので、信頼性が高いと共
に、パツケージの製造を自動化することができ
る。 Furthermore, since the resin mold layer is provided in which the semiconductor device, its mounting portion, external electrodes, and thin connection wires are integrally molded from above and below, reliability is high and the manufacturing of the package can be automated.
また、本発明に係る半導体装置のパツケージの
製造方法は、その動作時において上記半導体装置
に発生する熱の放散性が良好でありかつ信頼性の
高いリードレスタイプのパツケージを、簡便かつ
安価な方法によつて自動的に製造することができ
る。 Further, the method for manufacturing a package for a semiconductor device according to the present invention is a simple and inexpensive method for manufacturing a leadless type package that has good dissipation properties for heat generated in the semiconductor device during operation and is highly reliable. can be automatically manufactured by
第１図は従来のプラスチツクタイプのチツプキ
ヤリアタイプパツケージの構造を示す断面図、第
２Ａ図〜第２Ｄ図は本発明の１実施例による半導
体装置のパツケージの製造方法を説明するための
工程図、第３図は第２Ａ図に示すリードフレーム
の平面図である。
なお図面に用いた符号において、１，１６……
パツケージ、４，１２……チツプ、５，１３……
ワイヤ、１１……リードフレーム、１１ａ……チ
ツプ載置部、１１ｂ，１１ｃ……外部電極部、１
１ｄ……熱放散面、１１ｅ，１１ｆ……外部電極
面、１４……樹脂モールド層、１５ａ，１５ｂ，
１５ｃ……欠如部、である。
FIG. 1 is a sectional view showing the structure of a conventional plastic chip carrier type package, and FIGS. 2A to 2D are process diagrams for explaining a method for manufacturing a semiconductor device package according to an embodiment of the present invention. FIG. 3 is a plan view of the lead frame shown in FIG. 2A. In addition, in the symbols used in the drawings, 1, 16...
Package, 4, 12... Chip, 5, 13...
Wire, 11...Lead frame, 11a...Chip placement part, 11b, 11c...External electrode part, 1
1d... Heat dissipation surface, 11e, 11f... External electrode surface, 14... Resin mold layer, 15a, 15b,
15c...This is the missing part.
Claims (1)
置部と、外部電極と、上記半導体装置及び上記外
部電極にそれぞれ接続されている接続用細線と、
上記半導体装置、上記載置部、上記外部電極及び
上記接続用細線を上下から一体にモールドしてい
る樹脂モールド層とをそれぞれ具備する半導体装
置のパツケージにおいて、 上記樹脂モールド層の下面から上記外部電極の
下面に至るように上記樹脂モールド層に設けられ
た第１の欠如部と、 上記樹脂モールド層の下面から上記載置部の下
面に至るように上記樹脂モールド層に設けられた
第２の欠如部とをそれぞれ具備し、 上記第１の欠如部によつて、上記外部電極を上
記樹脂モールド層から突出させることなくこの樹
脂モールド層の下面に露出させてリードレスタイ
プに構成すると共に、 上記第２の欠如部によつて、上記半導体装置に
発生した熱を上記第２の欠如部を通して外部に放
散するように構成したことを特徴とする半導体装
置のパツケージ。 ２ 導電性基板に半導体装置載置部と外部電極部
とをそれぞれ設け、 上記半導体装置載置部に半導体装置を載置した
後、 接続用細線を上記半導体装置と上記外部電極部
とにそれぞれ接続し、 次いで、上記半導体装置、上記導電性基板の上
記外部電極部及び上記半導体装置載置部並びに上
記接続用細線を上下から一体に樹脂モールドし、 しかる後、上記樹脂モールド層の一部を除去し
て上記外部電極部の少なくとも一部と上記半導体
装置載置部の少なくとも一部とを上記樹脂モール
ド層の下面にそれぞれ露出させると共に、 上記導電性基板から上記半導体装置載置部及び
上記外部電極部をそれぞれ分離させるようにした
ことを特徴とする半導体装置のパツケージの製造
方法。[Scope of Claims] 1. A semiconductor device, a mounting portion on which the semiconductor device is placed, an external electrode, and thin connecting wires connected to the semiconductor device and the external electrode, respectively;
In a package of a semiconductor device comprising the semiconductor device, the mounting section, the external electrode, and a resin mold layer in which the thin connection wire is integrally molded from above and below, the external electrode is inserted from the bottom surface of the resin mold layer. A first cutout provided in the resin mold layer so as to reach the lower surface; and a second cutout provided in the resin mold layer so as to extend from the bottom surface of the resin mold layer to the lower surface of the placement part. and a leadless type structure in which the external electrode is exposed on the lower surface of the resin mold layer without protruding from the resin mold layer due to the first cutout part, and 2. A package for a semiconductor device, characterized in that the heat generated in the semiconductor device is dissipated to the outside through the second cutout. 2. After providing a semiconductor device mounting part and an external electrode part on a conductive substrate, and placing a semiconductor device on the semiconductor device mounting part, connect thin connecting wires to the semiconductor device and the external electrode part, respectively. Then, the semiconductor device, the external electrode portion of the conductive substrate, the semiconductor device mounting portion, and the thin connection wire are integrally molded with resin from above and below, and then, a portion of the resin mold layer is removed. At least a portion of the external electrode section and at least a portion of the semiconductor device mounting section are exposed on the lower surface of the resin mold layer, and the semiconductor device mounting section and the external electrode are exposed from the conductive substrate. A method for manufacturing a package for a semiconductor device, characterized in that the parts are separated from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083187A JPS59208755A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device package and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58083187A JPS59208755A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device package and manufacture of the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59208755A JPS59208755A (en) | 1984-11-27 |
| JPH0473297B2 true JPH0473297B2 (en) | 1992-11-20 |
Family
ID=13795315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58083187A Granted JPS59208755A (en) | 1983-05-12 | 1983-05-12 | Semiconductor device package and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208755A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62131449U (en) * | 1986-02-13 | 1987-08-19 | ||
| JPH0421320Y2 (en) * | 1986-02-14 | 1992-05-15 | ||
| JPS63301531A (en) * | 1987-06-01 | 1988-12-08 | Nec Corp | Hybrid integrated circuit device |
| JPH08148603A (en) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | Ball grid array type semiconductor device and manufacture thereof |
| JP3129169B2 (en) * | 1995-11-08 | 2001-01-29 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| US6329711B1 (en) | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
| US5977613A (en) * | 1996-03-07 | 1999-11-02 | Matsushita Electronics Corporation | Electronic component, method for making the same, and lead frame and mold assembly for use therein |
| DE10063041B4 (en) | 2000-12-18 | 2012-12-06 | Infineon Technologies Ag | A method of manufacturing an integrated leadless package circuit and integrated leadless package circuit |
| JP4611569B2 (en) * | 2001-05-30 | 2011-01-12 | ルネサスエレクトロニクス株式会社 | Lead frame and method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5921047A (en) * | 1982-07-27 | 1984-02-02 | Fuji Xerox Co Ltd | Leadless chip carrier |
-
1983
- 1983-05-12 JP JP58083187A patent/JPS59208755A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5921047A (en) * | 1982-07-27 | 1984-02-02 | Fuji Xerox Co Ltd | Leadless chip carrier |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59208755A (en) | 1984-11-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5198964A (en) | Packaged semiconductor device and electronic device module including same | |
| US6911353B2 (en) | Semiconductor device and method of manufacturing same | |
| US6246115B1 (en) | Semiconductor package having a heat sink with an exposed surface | |
| JPH0447977B2 (en) | ||
| US5715593A (en) | Method of making plastic-packaged semiconductor integrated circuit | |
| JPH02501873A (en) | High-density electronic package and its manufacturing method | |
| US5757068A (en) | Carrier film with peripheral slits | |
| US5844779A (en) | Semiconductor package, and semiconductor device using the same | |
| JP5169964B2 (en) | Mold package mounting structure and mounting method | |
| JPH0473297B2 (en) | ||
| US7646089B2 (en) | Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device | |
| US11081428B2 (en) | Electronic device with three dimensional thermal pad | |
| TWI274406B (en) | Dual gauge leadframe | |
| JP2819282B2 (en) | Semiconductor package and manufacturing method thereof | |
| JPH06132441A (en) | Resin-sealed semiconductor device and manufacture thereof | |
| KR101008534B1 (en) | Power semiconductor mudule package and method for fabricating the same | |
| JP3398580B2 (en) | Semiconductor device manufacturing method and substrate frame | |
| JP2002100710A (en) | Semiconductor device and method for manufacturing the same | |
| US20220310409A1 (en) | Method to connect power terminal to substrate within semiconductor package | |
| JP3210503B2 (en) | Multi-chip module and manufacturing method thereof | |
| JP2002184890A (en) | Surface mounting semiconductor device | |
| JP2504262Y2 (en) | Semiconductor module | |
| JP3541751B2 (en) | Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same | |
| JP2002025419A (en) | Overcurrent protection element, semiconductor furnished with the same and manufacturing method of the overcurrent protection element | |
| JP3287327B2 (en) | Manufacturing method of semiconductor resin sealed package |