KR950000457Y1 - Semiconductor package - Google Patents
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- KR950000457Y1 KR950000457Y1 KR92006144U KR920006144U KR950000457Y1 KR 950000457 Y1 KR950000457 Y1 KR 950000457Y1 KR 92006144 U KR92006144 U KR 92006144U KR 920006144 U KR920006144 U KR 920006144U KR 950000457 Y1 KR950000457 Y1 KR 950000457Y1
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- semiconductor
- insulating tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
내용 없음.No content.
Description
제1도 내지 제3도는 종래 일반적으로 알려지고 있는 여러 반도체 패키지의 구조를 보인 도면으로서,1 to 3 are views showing the structure of several semiconductor packages generally known in the art,
제1도는 전형적인 COL타입(Chip on Lead Type) 반도체 패키지의 구조를 보인 단면도.1 is a cross-sectional view showing the structure of a typical chip on lead type (COL) semiconductor package.
제2도는 탭(TAB : Tape Automated Bonding) 반도체 패키지의 구조를 보인 저면도.2 is a bottom view showing the structure of a tape automated bonding (TAB) semiconductor package.
제3도 LOC타입(Lead on Chip Type) 반도체 패키지의 구조를 보인 단면도.3 is a cross-sectional view showing the structure of a lead on chip type (LOC) semiconductor package.
제4도 내지 제7도는 본 고안에 의한 반도체 패키지의 구조를 보이는 도면으로서,4 to 7 are views showing the structure of a semiconductor package according to the present invention,
제4도는 본 고안 반도체 패키지의 종단면도.Figure 4 is a longitudinal cross-sectional view of the semiconductor package of the present invention.
제4도의 (a)(b)는 본 고안에 사용되는 반도체 칩의 본드 패드 배열구조를 보인 평면도.Figure 4 (a) (b) is a plan view showing a bond pad arrangement of the semiconductor chip used in the present invention.
제6도는 제4도의 A부 평면도.6 is a plan view of portion A of FIG.
제7도는 제6도의 B-B선 확대 단면도.7 is an enlarged sectional view taken along line B-B in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 칩 11a : 본드 패드11: semiconductor chip 11a: bond pad
12 : 신호외부 연결부 13 : 금속 와이어12: signal external connection portion 13: metal wire
14 : 패키지 몸체 15 : 몰딩수지14: package body 15: molding resin
21, 22 : 제1, 제2 절연 테이프 23 : 메탈라인21 and 22: first and second insulating tape 23: metal line
23a, 23b : 내·외부 리드23a, 23b: inner and outer lead
본 고안은 반도체 패키지에 관한 것으로, 특히 최근 점차 다핀 화인 피치(fine pitch)화 되어가고 있는 디바이스(device)의 패키징(packaging)에 용이하도록 함과 아울러 패키지의 경박단소화에 기여하고, 패시베이션 크랙(Passivation Crack)등과 같은 패키지 불량을 방지하며, 패키지의 실장을 보다 용이하게 행할 수 있도록 한 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and in particular, to facilitate the packaging (device) of a device that is becoming increasingly fine pitch (fine pitch) in recent years, and contributes to light and short reduction of the package, passivation crack ( The present invention relates to a semiconductor package that prevents package defects such as passivation cracks and the like and facilitates package mounting.
종래 일반적으로 알려지고 있는 여러종류의 반도체 패키지가 제1도 내지 제3도에 도시되어 있는 바, 이를 간단히 살펴보면 다음과 같다.Various types of semiconductor packages generally known in the art are illustrated in FIGS. 1 to 3, which are briefly described as follows.
제1도는 전형적인 COL타입(Chip on Lead Type) 반도체 패키지의 구조를 보인 단면도로서 이러한 반도체 패키지는 반도체 칩(1)을 리드프레임의 패들(2)위에 접착제(adhesive)를 이용하여 부착하고, 상기 반도체 칩(1)의 본드 패드(1a)와 리드프레임의 인너리드(3)를 금선(Gold Wire)(4)으로 접속하여 전기적으로 연결하며, 상기 반도체 칩(1)이 고정된 패들(2)과 리드프레임의 인너리드(3)를 포함하는 일정면적을 에폭시 몰딩 컴파운드(EMC)(5)로 몰딩하여 패키지로 형성한 후, 마지막으로 리드프레임의 서포트바 및 댐바(도시되지 않음)을 절단하여 각각 독립된 패키지로 분리하는 트림(Trim)공정과, 패키지 외부로 돌출된 아웃리드(6)를 소정형태로 절곡형성하는 포밍(forming)공정을 행하는 순서로 제작된다.FIG. 1 is a cross-sectional view illustrating a structure of a typical COL type semiconductor package, in which a semiconductor chip 1 is attached to a paddle 2 of a lead frame using an adhesive. A bond pad 1a of the chip 1 and an inner lead 3 of the lead frame are electrically connected with a gold wire 4, and the paddle 2 having the semiconductor chip 1 fixed thereto A certain area including the inner lead 3 of the lead frame is molded into an epoxy molding compound (EMC) 5 to form a package, and finally, the support bar and the dam bar (not shown) of the lead frame are cut out, respectively. It is produced in the order of performing a trim process of separating into separate packages and a forming process of bending the outlead 6 protruding out of the package into a predetermined form.
제2도는 탭(TAB : Tape automated Bonding) 반도체 패키지의 구조를 개략적으로 보인 저면도로서, 이러한 TAB 반도체 패키지는 칩(1')의 각 본드 패드(도시되지 않음)에 솔더 범프(도시되지 않음)를 형성하고, 메탈라인(Metal line)(7)이 형성되어 있는 절연테이프(8)에 칩(1')을 어태치하여 리드 포밍(Lead forming)이나 트림 및 몰딩공정없이 기판(도시되지 않음)에 아웃리드를 마운팅하는 것에 의하여 표면실장하도록 구성된다.FIG. 2 is a bottom view schematically showing the structure of a tape automated bonding (TAB) semiconductor package, wherein the TAB semiconductor package has solder bumps (not shown) on each bond pad (not shown) of the chip 1 '. And attaching the chip 1 'to the insulating tape 8 having the metal line 7 formed thereon, thereby eliminating the need for lead forming, trimming, and molding. And surface mount by mounting the outlead.
제3도는 일반적인 LOC타입 반도체 패키지의 구조를 보인 단면도로서, 이러한 반도체 패키지는 칩(1")의 표면과 패들이 제거된 리드프레임의 인너리드(3") 부위를 절연테이프(9)로 상호 어태치한 후, 칩(1")의 중간부에 배열된 각 본드 패드(1"a)와 상기 리드프레임의 인너리드(3")를 금선(4")으로 접속하여 전기적으로 연결하고, 상술한 COL타입 반도체 패키지와 동일한 방법으로 와이어 본딩 반도체 칩(1")과 리드프레임의 인너리드(3")를 포함하는 일정면적을 에폭시 몰딩 컴파운드(5")로 몰딩하여 패키지로 형성한 후, 아웃리드(6")를 트림/포밍하여서 최종 패키지를 제작하게 된다.3 is a cross-sectional view showing a structure of a general LOC type semiconductor package, in which the surface of the chip 1 " and the inner lead 3 " After attaching, each of the bond pads 1 "a arranged in the middle of the chip 1" and the inner lead 3 "of the lead frame are electrically connected by gold wires 4", and the above-described COL In the same manner as the type semiconductor package, a certain area including the wire bonding semiconductor chip 1 "and the inner lead 3" of the lead frame is molded with an epoxy molding compound 5 "to form a package, and then the outlead ( 6 ") to trim and form the final package.
도면중 미설명 부호 10은 점프 패드를 보인 것이다.In the figure, reference numeral 10 shows a jump pad.
이와같이 구성되는 상기한 여러 반도체 패키지는 기판에 표면실장법 및 리드삽입 실장형태로 장착되어 소정의 동작을 하게 된다.The above-described various semiconductor packages are mounted on the substrate in a surface mount method and a lead insertion mount type to perform a predetermined operation.
그러나 상기한 바와같은 종래의 반도체 패키지는 일반적인 COL 타입 반도체 패키지의 경우, 리드프레임 패들(2)의 크기 및 두께로 인하여 패키지의 경박단소화에 한계를 가져오는 문제가 있었고, 상기한 TAB 반도체 패키지 및 LOC타입 반도체 패키지는 패키지의 소형화에는 기여하는 바가 크나, 상기 TAB 반도체 패키지에 있어서는 몰딩공정의 생략으로 패키지의 신뢰도(Realiability)에 문제가 발생되고, 상기 LOC타입 반도체 패키지에 있어서는 , 다핀 패키지 제작의 어려움과, 집(1")표면의 에폭시 몰딩 컴파운드(5")의 응력(stress) 차이로 인한 패시베이션 크랙(Passivation crack)등이 발생되는 문제점이 있었다.However, the conventional semiconductor package as described above has a problem in that the size and thickness of the lead frame paddle 2 has a limitation in reducing the thickness of the package in the case of a general COL type semiconductor package. The LOC type semiconductor package contributes to the miniaturization of the package. However, in the TAB semiconductor package, there is a problem in the reliability of the package due to the omission of the molding process. In the LOC type semiconductor package, it is difficult to manufacture a multi-pin package And a passivation crack due to the stress difference of the epoxy molding compound 5 "on the surface of the zip surface 1".
본 고안은 상기한 바와같은 종래의 여러 반도체 패키지가 가지는 문제점을 해소하기 위하여 안출한 것으로 다핀 화인 피치(find pitch)의 패키지 제작에 용이하도록 함과 아울러 패키지의 경박단소화에 기여하고, 패시베이션 크랙 등과 같은 패키지 불량을 감소시키며, 패키지의 실장을 보다 용이하게 할 수 있도록 한 반도체 패키지를 제공하는데 목적이 있다.The present invention has been devised to solve the problems of various conventional semiconductor packages as described above, which facilitates the production of multi-pin fine pitch packages, and contributes to the reduction of light and thin package, and the passivation crack and the like. It is an object of the present invention to provide a semiconductor package which reduces the same package defect and makes it easier to mount the package.
상기와 같은 목적을 달성하기 위하여 상면에 다수개의 본드 패드가 소정형태로 배열된 반도체 칩과, 상기 반도체 칩의 동작신호를 외부로 전달시키기 위한 신호외부 연결부와, 상기 신호외부 연결부의 내부리드와 반도체 칩의 본드 패드를 전기적으로 접속 연결하는 금속 와이어와, 와이어 본딩된 반도체 칩과 상기 신호외부 연결부의 일부분을 포함하는 일정면적을 밀폐시켜 패키지 몸체를 형성하는 몰딩수지로 구성됨을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the above object, a semiconductor chip having a plurality of bond pads arranged in a predetermined shape on an upper surface thereof, a signal external connection unit for transmitting an operation signal of the semiconductor chip to the outside, an internal lead and a semiconductor of the signal external connection unit A semiconductor package comprising a metal wire for electrically connecting and connecting a bond pad of a chip, and a molding resin to form a package body by sealing a predetermined area including a wire bonded semiconductor chip and a portion of the signal external connection part. Is provided.
상기 신호외부 연결부는 반도체 칩의 상면에 부착되는 제1절연 테이프와 제2절연 테이프의 사이에 반도체 칩의 동작신호를 외부로 전달시키기 위한 다수개의 메탈라인이 개재되어 있고, 상기 메탈라인은 칩의 본도 패드에 금속 와이어로 연결되는 내부리드와 기판에 접속되는 외부리드가 서로 상반된 방향으로 절연 테이프로 부터 노출된 구성으로 되어 있다.The signal external connection part includes a plurality of metal lines interposed between the first insulating tape and the second insulating tape attached to the upper surface of the semiconductor chip to transfer the operation signals of the semiconductor chip to the outside, and the metal lines are formed of the chip. The inner lead connected to the pad by the metal wire and the outer lead connected to the substrate are exposed from the insulating tape in directions opposite to each other.
이하, 상기한 바와같은 본 고안에 의한 반도체 패키지를 첨부한 도면에 의거하여 보다 상세히 설명한다.Hereinafter, the semiconductor package according to the present invention as described above will be described in more detail with reference to the accompanying drawings.
제4도는 본 고안에 의한 반도체 패키지의 구성을 보인 단면도로서 이에 도시한 바와같이, 본 고안에 의한 반도체 패키지는 상면에 다수개의 본드 패드(11a)가 소정형태로 배열된 반도체 칩(11)과, 상기 반도체 칩(11)의 동작신호를 외부로 전달시키기 위한 신호외부 연결부(12)와, 상기 신호외부 연결부(12)의 내부리드와, 반도체 칩(1)의 본드 패드(11a)를 전기적으로 접속 연결하는 금속 와이어(13)와, 와이어 본딩된 반도체 칩(11)과 상기 신호외부 연결부(12)의 일부분을 포함하는 일정 면적을 밀폐시켜 패키지 몸체(14)를 형하는 몰딩수지(15)로 구성된다.4 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention, as shown in the present invention, the semiconductor package according to the present invention includes a semiconductor chip 11 having a plurality of bond pads 11a arranged in a predetermined shape on an upper surface thereof, The signal external connection part 12 for transmitting the operation signal of the semiconductor chip 11 to the outside, the inner lead of the signal external connection part 12, and the bond pad 11a of the semiconductor chip 1 are electrically connected. It consists of a molding resin 15 to form a package body 14 by sealing a predetermined area including a metal wire 13 for connecting, a wire bonded semiconductor chip 11 and a portion of the signal external connection 12. do.
상기 본드 패드(11a)는 제5도의 (a) 및 (b)에 도시한 바와같이 반도체 칩(11)의 상면 가장자리를 따라 배열되는 바, (a)와 같이 ㄷ자 형태로 배열할 수도 있고, (b)와 같이 ㄱ자 형태로 배열할 수도 있으며, 도시하지는 않았지만, T자, 및 일변부에만 배열할 수도 있다.The bond pads 11a are arranged along the top edge of the semiconductor chip 11 as shown in FIGS. 5A and 5B, and may be arranged in a U-shape as shown in (a). As shown in b), they may be arranged in an L-shape, and although not shown, may be arranged only in the T-shape and one side.
또한, 상기 신호외부 연결부(12)는 제6도 및 제7도에 도시한 바와같이 반도체 칩(11)의 상면에 부착되는 소정의 폭과 길이를 갖는 제1 절연 테이프(21) 및 제2 절연 테이프(22)와, 상기 제1, 제2 절연 테이프(21)(22) 사이에 개재되어 반도체 칩(11)의 동작신호를 외부로 전달시키기 위한 다수개의 메탈라인(23)으로 구성되어 있으며, 상기 메탈라인(23)은 칩(11)의 본드 패드(11a)에 금속 와이어(13)로 연결되는 내부리드(23a)와, 기판에 접속되는 외부리드(23b)가 연장 형성되어 있고, 상기 내·외부리드(23a)(23b)는 서로 상반된 방향으로 절연 테이프(21)(22)로부터 노출되어 각각의 본드패드(11a)와 기판에 접속할 수 있도록 되어 있다.In addition, the signal external connection part 12 includes a first insulating tape 21 and a second insulating film having a predetermined width and length attached to the upper surface of the semiconductor chip 11 as shown in FIGS. 6 and 7. It is composed of a plurality of metal lines 23 interposed between the tape 22 and the first and second insulating tapes 21 and 22 to transmit an operation signal of the semiconductor chip 11 to the outside. The metal line 23 has an inner lead 23a connected to the bond pad 11a of the chip 11 by a metal wire 13 and an outer lead 23b connected to the substrate. The outer leads 23a and 23b are exposed from the insulating tapes 21 and 22 in directions opposite to each other and can be connected to the respective bond pads 11a and the substrate.
상기 제1, 제2 절연 테이프(21)(22)는 폴리이미드(polyimide)계 또는 에폭시(Epoxy)계 테이프가 사용되며, 메탈라인(23)은 구리(Copper) 또는 골드(Gold)등과 같은 전도성의 금속이 사용되는 바, 상기 제1, 제2 절연 테이프(21)(22)의 두께(Tickness)는 약 76㎛로 함이 바람직하고, 상기 메탈라인(23)의 두께는 35㎛, 폭(width)은 70㎛으로 형성함이 바람직하다.The first and second insulating tapes 21 and 22 may be made of polyimide or epoxy tape, and the metal line 23 may be made of copper, gold, or the like. Since the metal is used, the thickness of the first and second insulating tapes 21 and 22 is preferably about 76 μm, and the thickness of the metal line 23 is 35 μm and the width ( width) is preferably formed to 70 μm.
또한, 상기 메탈라인(23)의 내부리드(23a)는 와이어 본딩을 용이하게 하기 위하여 메탈라인(23)의 폭보다 좀 더 큰 사각형태로 형성하는 바, 가로×세로가 500×650㎛이 되도록 형성함이 바람직하다.In addition, the inner lead 23a of the metal line 23 is formed in a rectangular shape larger than the width of the metal line 23 in order to facilitate wire bonding, so that the width × length is 500 × 650 μm. It is preferable to form.
또한, 상기 반도체 칩(11)에 부착되는 제1 절연 테이프(21)는 메탈라인(23)의 내부리드(23a) 단부보다 소정길이 만큼 크게 형성하게 되는데, 500㎛정도 더 길게 형성함이 바람직하다.In addition, the first insulating tape 21 attached to the semiconductor chip 11 is formed to be larger than the end of the inner lead 23a of the metal line 23 by a predetermined length, but is preferably formed to be longer than 500 μm. .
또한, 메탈라인(23)을 보호하기 위한 제2 절연 테이프(22)는 그의 단부를 메탈라인(23)의 외부리드(23b) 단부보다 길게 형성하여 기판에 실장시 상기 절연 테이프(22)의 접착력으로 실장할 수 있도록 하는 바, 약 800㎛정도 길게 형성함이 바람직하다.In addition, the second insulating tape 22 for protecting the metal line 23 is formed so that its end is longer than the end of the outer lead 23b of the metal line 23, the adhesive force of the insulating tape 22 when mounted on a substrate It can be mounted to the bar, it is preferable to form about 800㎛ long.
이와같이 구성되는 본 고안에 의한 반도체 패키지의 제조과정을 살펴보면, 먼저 소잉(Sawing)공정에 의해 웨이퍼 상태에서 개개로 분리된 반도체 칩(11)의 상면에 메탈라인(23)이 중간부에 개재되어 있는 제1, 제2 절연 테이프(21)(22)로 구성된 신호외부 연결부(12)를 소정의 압력과 열을 가하면서 부착시키고, 금속 와이어(13)를 이용하여 칩(11)의 각 본드 패드(11a)와, 신호 외부 연결부(12)의 각 내부리드(23a)를 전기적으로 접속 연결한다.Looking at the manufacturing process of the semiconductor package according to the present invention configured as described above, first, the metal line 23 is interposed in the middle portion on the upper surface of the semiconductor chip 11 separately separated in the wafer state by a sawing process (Sawing) The signal external connection portion 12 composed of the first and second insulating tapes 21 and 22 is attached while applying a predetermined pressure and heat, and each bond pad of the chip 11 is formed using the metal wire 13. 11a) and each of the inner leads 23a of the signal outer connecting portion 12 are electrically connected to each other.
이후, 와이어 본딩된 반도체 칩(11)과 신호외부 연결부(12)의 일부분을 포함하는 일정면적을 몰딩수지(15)로 몰딩하여 패키지 몸체(14)를 형성하되, 반도체 칩(11)의 하면이 외부로 노출되도록 몰딩하며, 제4도와 같은 반도체 패키지를 제조하는 것이다.Thereafter, the package body 14 is formed by molding a predetermined area including a wire bonded semiconductor chip 11 and a portion of the signal external connection part 12 with the molding resin 15, and the bottom surface of the semiconductor chip 11 Molding to expose to the outside, to manufacture a semiconductor package as shown in FIG.
이와같은 반도체 패키지를 기판에 실장함에 있어서는 신호외부 연결부(12)의 제1 절연 테이프(21)의 단부로 부터 하측으로 오픈되어 있는 메탈라인(23)의 외부리드(23b)를 기판(도시되지 않음)의 동박패턴에 일치시키고 제2 절연 테이프(22)의 접착력을 이용하여 기판에 표면 실장하게 된다.In mounting such a semiconductor package on a substrate, an external lead 23b of the metal line 23 opened downward from an end of the first insulating tape 21 of the signal external connection part 12 is not shown on the substrate (not shown). The copper foil pattern of ()) is used and the surface is mounted on the substrate by using the adhesive force of the second insulating tape 22.
즉, 종래와 같이 반도체 패키지의 실장을 위한 별도의 부재에 예컨대 솔더와 같은 접착부재 사용없이 간편하게 실장할 수 있는 것이다.That is, it can be easily mounted on a separate member for mounting the semiconductor package as in the prior art without using an adhesive member such as solder.
이상에서 상세히 설명한 바와같은 본 고안에 의한 반도체 패키지는 리드프레임의 패들 제거로인한 패키지의 경박단소화와, 다핀 패키지 제작이 매우 용이하다는 효과가 있고, 몰딩수지와 반도체 칩 상면과의 접촉면적이 감소되므로 종래와 같은 패시베이션 크랙등의 패키지 불량을 방지할 수 있으며, 다이본딩 공정과 외부리드 본딩 공정을 간소화 시킬 수 있는 효과도 있다.As described in detail above, the semiconductor package according to the present invention has an effect of reducing the thickness and thinness of the package due to the paddle removal of the lead frame and making the multi-pin package very easy, and reducing the contact area between the molding resin and the upper surface of the semiconductor chip Therefore, it is possible to prevent a package failure such as a passivation crack as in the prior art, there is an effect that can simplify the die bonding process and the external lead bonding process.
또한, 본드 패드의 구조에 따라 메탈라인의 디자인이 자유롭게, 트림/포밍공정이 제거되며, 기판에 실장시 별도의 부재 에컨대, 종래의 패키지 장착에 사용되는 솔더(solder)등과 같은 접착부재 사용없이도 간편하게 실장시킬 수 있는 효과가 있다.In addition, the design of the metal line allows the design of the metal line to be free and the trim / forming process is eliminated, and a separate member is used when mounting on a substrate, for example, without the use of an adhesive member such as a solder used for mounting a conventional package. There is an effect that can be easily mounted.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92006144U KR950000457Y1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor package |
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| KR92006144U KR950000457Y1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor package |
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| Publication Number | Publication Date |
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| KR930024375U KR930024375U (en) | 1993-11-27 |
| KR950000457Y1 true KR950000457Y1 (en) | 1995-01-27 |
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| KR92006144U KR950000457Y1 (en) | 1992-04-14 | 1992-04-14 | Semiconductor package |
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| KR930024375U (en) | 1993-11-27 |
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