KR19990023599U - LOC type package - Google Patents

Abstract

The present invention relates to a LOC type package in which multifunctionalization according to multi-pinning is realized. The package of the present invention includes a semiconductor chip having a center bonding pad, a first lead frame attached by an adhesive to an upper portion of the chip, and an upper portion of the first lead frame while exposing proximal ends of both sides of the first lead frame. And a second lead frame attached by an adhesive.

Description

LOC type package

The present invention relates to a semiconductor device, and more particularly, to a package of a lead on chip (LOC) type for mounting a semiconductor chip to an electronic device.

Today, LOC processes are commonly used for the packaging of semiconductor chips. In the LOC type package, the bonding pad of the semiconductor chip is often required to be located at the center of the semiconductor chip. Such constraints on the position of the bonding pads limit the number of pads and lead to the problem of accessing or positioning the leads only to limited portions. Due to this problem, the lead that can enter the pad side is reduced by about half than when the bonding pad is located at the edge of the chip, which entails design constraints and is an obstacle to the development of a multi-pin package requiring multifunction. .

Therefore, the present invention devised to solve the above problems is to provide a LOC type package that enables the multifunction by the pinning by solving the technical limitation of the number of pads due to the bonding pad is located in the center of the chip. do.

1 is a cross-sectional view showing a LOC type package according to a preferred embodiment of the present invention,

2A to 2G illustrate the manufacture of a package according to FIG. 1.

* Explanation of symbols for the main parts of the drawings

11: Substrate 12: Molding Compound

13: semiconductor chip 14: center bonding pad

15: first lead frame 16: first adhesive tape

17: second lead frame 18: second adhesive tape

19a, 19b: Gold wire 21: F-shaped plated pin

22: T-shaped plated pin

In order to achieve the above object of the present invention, the present invention exposes a semiconductor chip having a center bonding pad, a first lead frame attached by an adhesive on top of the chip, and proximal ends of both sides of the first lead frame. And a second lead frame attached to an upper portion of the first lead frame by an adhesive, and a bonding wire connecting the first lead frame and the second lead frame to the center bonding pad, respectively. Provides a LOC type package.

According to the present invention, by adopting a double lead frame structure in which the second lead frame is superimposed on the first lead frame, it is possible to provide a multifunctional package by solving the pin number limitation problem.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a LOC type package according to the present embodiment, Figures 2a to 2h is a view for explaining the manufacture of the package according to FIG.

Referring to FIG. 1, a package according to the present embodiment includes a substrate 11 such as a PCB and a semiconductor chip 13 encapsulated by a molding compound 12 such as an epoxy resin. The semiconductor chip 13 has a bonding pad 14 at the center, and the first lead frame 15 is attached to the upper both sides of the chip 13 by an adhesive 16. The second lead frame 17 is attached to the upper portion of the first lead frame 15 by the adhesive 18. Here, the adhesive 18 serves as an insulator between the first lead frame 15 and the second lead frame 17. The second lead frame 17 has a shorter length than the first lead frame so as to expose the proximal end portions of the inner and out leads of both side first lead frames 15. Although not shown, the upper surfaces of the first lead frame 15 and the second lead frame 17 are silver plated. Gold wires 19a and 19b are connected between the bonding pad 14 of the semiconductor chip 13 and the upper surfaces of the first lead frame 15 and the second lead frame 17, respectively. An approximately F-shaped plated pin 21 is soldered to the distal end portions of both out leads of the first lead frame 15. An approximately T-shaped plated pin 22 is soldered to the terminal proximal portions of both out leads of the second lead frame 17.

As such, the package having the structure shown in FIG. 1 may be manufactured by the following method.

First, as shown in FIG. 1A, a first lead frame 15 is manufactured by etching in a conventional manner, and then silver is plated on the upper surface of the first lead frame. On the other hand, after fabricating the second lead frame 17a by etching as shown in FIG. 2B, an insulating material is coated on the lower surface of the second lead frame 17a as shown in FIG. 2C. After that, the adhesive tape 18 is preferably attached in three pieces and plated with silver on the upper surface. Thereafter, both ends of the crude second lead frame 17a are cut to produce a second lead frame 18 as shown in FIG. 2D. Then, as shown in FIG. 2E, the second lead frame 17 is attached to the first lead frame by the adhesive tape 18 so as to overlap each other while exposing the upper surfaces of both end adjacent portions of the first lead frame 15. Attach to the top of 15). Here, reference numeral 16 is an adhesive tape. Thereafter, as shown in FIG. 2F, the first lead frame 15 and the second lead frame 17 overlapping each other are die-attached on the semiconductor chip 13 having the center pad 14. Then, wire bonding is performed using gold wires 19a and 19b, as shown in FIG. 2G, in which the gold wires 19a and 19b are bonded to different bonding pads 14, respectively, to separate signals from each other. To form. Subsequently, molding is performed as a molding compound 12 such as an epoxy resin as shown in FIG. 2H. After removing and plating the dam of the first lead frame 15, the lead tip of the first lead frame 15 is cut. Thereafter, as formed in FIG. 1, the substrate 11 is mounted on the substrate 11 as shown in FIG. 1, and then the plated pin 21 having an approximately F shape is mounted on the end of the out lead of the first lead frame 15. On the other hand, an approximately T-shaped plated pin 22 is attached to the end proximal portion of the outlead of the second lead frame 17.

As described above, the LOC type package according to the present invention adopts a lead structure consisting of a second lead frame attached to an upper portion of the first lead frame, thereby solving the problem caused by the number of pins, thereby enabling multifunctionalization. .

Although the present invention has been described and illustrated based on the preferred embodiment thereof, those skilled in the art can clearly see that various changes and modifications to the embodiment can be made without departing from the gist of the present invention.

Claims (3)

A semiconductor chip having a center bonding pad, a first lead frame attached by an adhesive on top of the chip, and an adhesive affixed on top of the first lead frame while exposing proximal ends of both sides of the first lead frame; A second lead frame, and a bonding wire connecting the first lead frame and the second lead frame to the center bonding pad, respectively. The LOC type package according to claim 1, wherein an approximately F-shaped plated pin is soldered to the out lead of the first lead frame. The LOC type package according to claim 1, wherein a substantially T-shaped plated pin is soldered to the out lead of the second lead frame.