JPH053277A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH053277A JPH053277A JP3152881A JP15288191A JPH053277A JP H053277 A JPH053277 A JP H053277A JP 3152881 A JP3152881 A JP 3152881A JP 15288191 A JP15288191 A JP 15288191A JP H053277 A JPH053277 A JP H053277A
- Authority
- JP
- Japan
- Prior art keywords
- outer lead
- semiconductor device
- region
- face
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ガルウィング形状又は
フラット形状のアウターリードを有する半導体装置、そ
の組立技術、その実装技術及びその検査技術に適用して
有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having gull-wing or flat outer leads, an assembly technique thereof, a mounting technique thereof, and an inspection technique effectively applied thereto.
【０００２】[0002]
【従来の技術】ガルウィング形状のアウターリードを有
する樹脂封止型半導体装置は、半導体ペレットの外部端
子とインナーリードの一端とがワイヤで電気的に接続さ
れ、この半導体ペレット、インナーリード及びワイヤが
樹脂封止体で封止される。前記インナーリードの他端は
アウターリードに一体に構成されかつ電気的に接続され
る。2. Description of the Related Art In a resin-sealed semiconductor device having gull wing-shaped outer leads, an external terminal of a semiconductor pellet and one end of an inner lead are electrically connected by a wire, and the semiconductor pellet, the inner lead and the wire are made of resin. It is sealed with a sealing body. The other end of the inner lead is integrally formed with and electrically connected to the outer lead.
【０００３】前記樹脂封止型半導体装置のアウターリー
ド、インナーリードの夫々は、同一リードフレームから
切断されかつ成型され、同一材料具体的には現在主流と
して使用されるＦｅ−Ｎｉ合金、Ｃｕのいずれかで形成
される。樹脂封止型半導体装置は、ＰＣＢ基板等の実装
基板の実装面の端子に半田ペーストを介在してアウター
リードを電気的かつ機械的に接続し、この実装基板への
実装がなされる。基本的に、前述の材料で形成されるア
ウターリードは、半田ペーストとの濡れ性（接着性）が
低いので、この濡れ性を高めことを目的として、半田メ
ッキ層が形成される。The outer lead and the inner lead of the resin-encapsulated semiconductor device are cut and molded from the same lead frame, and are made of the same material, specifically Fe--Ni alloy or Cu which is currently used as a mainstream. It is formed by. The resin-sealed semiconductor device is mounted on the mounting substrate by electrically and mechanically connecting the outer leads to terminals on the mounting surface of a mounting substrate such as a PCB substrate with a solder paste interposed. Basically, the outer lead formed of the above-mentioned material has low wettability (adhesiveness) with the solder paste, and therefore a solder plating layer is formed for the purpose of improving this wettability.
【０００４】前記半田メッキ層は、一般的に、樹脂封止
型半導体装置の組立プロセス中、樹脂封止体の成型後、
リードフレームの切断成型前において形成される。ま
た、半田メッキ層は、所謂半田先付け方法と称され、エ
ッチング加工若しくはプレス加工でリードフレームを形
成した後、樹脂封止体の成型前に形成される。いずれの
場合においても、半田メッキ層はリードフレームの切断
成型（すなわち、リードフレームからアウターリード等
を切り離し、このアウターリードをガルウィング形状に
成型する）前に形成される。In general, the solder plating layer is formed after the resin encapsulant is molded during the assembly process of the resin encapsulation type semiconductor device.
It is formed before cutting and molding the lead frame. Further, the solder plating layer is called a so-called soldering method, and is formed after forming the lead frame by etching or pressing and before molding the resin sealing body. In any case, the solder plating layer is formed before cutting and molding the lead frame (that is, separating the outer leads and the like from the lead frame and molding the outer leads into a gull wing shape).
【０００５】前記樹脂封止体は、トランスファモールド
法で成型され、例えばエポキシ系樹脂が使用される。The resin encapsulant is molded by a transfer molding method and, for example, an epoxy resin is used.
【０００６】なお、樹脂封止型半導体装置の実装基板へ
の実装技術については、例えば、日経エレクトロニク
ス、「別冊マイクロデバイセズ」Ｎo.２、１９８４年６
月１１日、第１８７頁乃至第２０５頁において論じらて
いる。Regarding the mounting technique of the resin-encapsulated semiconductor device on the mounting substrate, see, for example, Nikkei Electronics, "Separate Volume Micro Devices", No. 2, 1984 6
Discussed on the 11th day, pages 187 to 205.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、本発明
者は、前述のガルウィング形状のアウターリードを有す
る半導体装置を実装基板に実装後、半田ペーストの濡れ
性を検査する外観不良検査において、下記の問題点を見
出した。However, the present inventor has found the following problems in the appearance defect inspection for inspecting the wettability of the solder paste after mounting the above-mentioned semiconductor device having the gull wing-shaped outer leads on the mounting substrate. I found a point.
【０００８】樹脂封止型半導体装置のアウターリードの
ファインピッチ化に基づき、実装基板上でのアウターリ
ードと端子との接続部分が微細でしかも接続部分の個数
が多くなる傾向にあり、これに比例して実装技術、外観
不良検査技術のいずれもが進展する傾向にある。この結
果、前述の半田ペーストの濡れ性を検査する外観不良検
査に自動化が導入されてきた。Due to the finer pitch of the outer leads of the resin-encapsulated semiconductor device, the connecting portion between the outer lead and the terminal on the mounting substrate tends to be fine and the number of connecting portions tends to increase, which is proportional to this. Then, both the mounting technology and the visual defect inspection technology tend to progress. As a result, automation has been introduced in the appearance defect inspection for inspecting the wettability of the solder paste.
【０００９】樹脂封止型半導体装置のアウターリードの
表面には半田ペーストとの濡れ性を確保する半田メッキ
層が形成されるが、半田メッキ層を形成した後にアウタ
ーリードがリードフレームから切断されるので、この切
断面に相当する、アウターリードの最先端の端面は半田
メッキ層が形成されておらず母体が露出する。このた
め、樹脂封止型半導体装置は、アウターリードの最先端
の端面に半田ペーストが付着しないので、半田ペースト
量の絶対量が低下し、実装基板への実装に際し、機械的
強度が低下するばかりか、断線などの電気的信頼性が劣
化する。A solder plating layer for ensuring wettability with a solder paste is formed on the surface of the outer lead of the resin-encapsulated semiconductor device, but the outer lead is cut from the lead frame after the solder plating layer is formed. Therefore, the solder plating layer is not formed on the tip end surface of the outer lead, which corresponds to this cut surface, and the mother body is exposed. Therefore, in the resin-encapsulated semiconductor device, since the solder paste does not adhere to the end face of the outer lead, the absolute amount of the solder paste amount decreases, and the mechanical strength does not only decrease when mounting on the mounting board. Otherwise, the electrical reliability such as disconnection deteriorates.
【００１０】また、自動化される外観不良検査におい
て、樹脂封止型半導体装置のアウターリードと実装基板
の端子との接続状態を検査する方向が、アウターリード
の最先端側から樹脂封止体に向う方向に限定される。つ
まり、樹脂封止型半導体装置が実装基板に実装される
と、樹脂封止体からアウターリードの最先端側に向う方
向には樹脂封止体が存在するので検査が難しく、又アウ
ターリードの配列方向においてはファインピッチ化など
でアウターリードの間隔が狭いので同様に検査が難し
い。Further, in the automated visual defect inspection, the direction of inspecting the connection state between the outer lead of the resin-sealed semiconductor device and the terminal of the mounting substrate is from the most distal end of the outer lead to the resin-sealed body. Limited to direction. In other words, when the resin-encapsulated semiconductor device is mounted on the mounting board, the resin encapsulant is present in the direction from the resin encapsulant to the most distal side of the outer leads, making it difficult to inspect. In the same direction, it is also difficult to inspect because the outer lead spacing is narrow due to the fine pitch.
【００１１】このため、外観不良検査においては、前述
のアウターリードの最先端の端面つまり半田ペーストが
付着しない部分の半田ペーストの付着状態を検査するの
で、アウターリードと端子との間が確実に接続されてい
ても、接続していない誤った結果が出力されるなど、外
観不良検査の精度が低下する。場合によっては、検査し
たすべての樹脂封止型半導体装置が、確実に接続されて
いるにもかかわらず、外観不良検査において濡れ性不良
という結果にもなる。Therefore, in the appearance defect inspection, since the solder paste adhesion state of the above-mentioned end face of the outer lead, that is, the portion to which the solder paste does not adhere is inspected, the outer lead and the terminal are surely connected. Even if it is, the accuracy of the visual defect inspection is lowered, such as the output of an incorrect result that is not connected. In some cases, all the resin-encapsulated semiconductor devices that have been inspected may result in poor wettability in the appearance defect inspection even though they are reliably connected.
【００１２】本発明の目的は、以下のとおりである。The objects of the present invention are as follows.
【００１３】（Ａ）ガルウィング形状又はフラット形状
のアウターリードの表面に最先端の端面を除き半田メッ
キ層が形成される半導体装置において、前記アウターリ
ードの最先端の端面の濡れ性を向上する。(A) In a semiconductor device in which a solder-plated layer is formed on the surface of a gull wing-shaped or flat outer lead except the tip end face, the wettability of the tip end face of the outer lead is improved.
【００１４】（Ｂ）前記目的（Ａ）を達成するととも
に、前記半導体装置を実装基板に実装した際の接合強度
を向上する。(B) The object (A) is achieved and the bonding strength when the semiconductor device is mounted on a mounting board is improved.
【００１５】（Ｃ）前記目的（Ａ）の半導体装置を実装
基板に実装した後に行われる外観不良検査の自動化にお
いて、誤検査を低減し、外観不良検査の精度を向上す
る。(C) In the automation of the appearance defect inspection performed after the semiconductor device having the above purpose (A) is mounted on the mounting board, the erroneous inspection is reduced and the accuracy of the appearance defect inspection is improved.
【００１６】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１７】[0017]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
【００１８】（１）ガルウィング形状又はフラット形状
のアウターリードの表面にこのアウターリードが実装基
板の端子に接続される側の最先端の端面の領域を除き半
田メッキ層が形成される半導体装置において、前記アウ
ターリードの最先端の端面の半田メッキ層が形成されて
いない領域の断面積がそれ以外の領域のアウターリード
の断面積に比べて小さく構成される。前記アウターリー
ドの最先端の端面は、それ以外の領域のアウターリード
の板厚に比べて薄く構成され、又はそれ以外の領域のア
ウターリードのリード幅寸法に比べて小さく構成され、
断面積が小さく構成される。(1) In a semiconductor device in which a solder-plated layer is formed on the surface of a gull wing-shaped or flat-shaped outer lead except for the region of the tip end face on the side where the outer lead is connected to a terminal of a mounting board, The cross-sectional area of the region where the solder plating layer is not formed on the most end face of the outer lead is smaller than the cross-sectional area of the outer lead in the other region. The outermost end face of the outer lead is configured to be thinner than the plate thickness of the outer lead in the other region, or configured to be smaller than the lead width dimension of the outer lead in the other region,
The cross-sectional area is small.
【００１９】（２）ガルウィング形状又はフラット形状
のアウターリードの表面にこのアウターリードが実装基
板の端子に接続される側の最先端の端面の領域を除き半
田メッキ層が形成される半導体装置において、前記アウ
ターリードの最先端の半田メッキ層が形成されていない
端面を含む領域の板厚がそれ以外の領域のアウターリー
ドの板厚に比べて薄く構成され、このアウターリードの
最先端の板厚の薄い領域が実装基板の端子に接続される
面から離れる方向に曲げられる。(2) In a semiconductor device in which a solder-plated layer is formed on the surface of a gull wing-shaped or flat-shaped outer lead except for the region of the tip end face on the side where the outer lead is connected to a terminal of a mounting board, The thickness of the region of the outer lead including the end face on which the most advanced solder plating layer is not formed is thinner than the thickness of the outer lead of the other region, and the thickness of the most advanced thickness of the outer lead is The thin region is bent in a direction away from the surface of the mounting substrate that is connected to the terminals.
【００２０】（３）前記手段（１）又は手段（２）のい
ずれかの半導体装置は、そのアウターリードの最先端の
領域と実装基板の端子との間を半田ペーストを介在して
電気的かつ機械的に接続した後に、前記アウターリード
の最先端の端面に半田ペーストが付着しているか否かを
自動的に検出する不良品検査が行われる。(3) In the semiconductor device according to any one of the means (1) and the means (2), the solder paste is interposed between the tip end region of the outer lead and the terminal of the mounting substrate to electrically and electrically. After mechanical connection, a defective product inspection is automatically performed to automatically detect whether or not the solder paste is attached to the tip end face of the outer lead.
【００２１】[0021]
【作用】上述した手段（１）によれば、前記半導体装置
のアウターリードを半田ペーストを介在して実装基板の
端子に電気的かつ機械的に接続する場合、半導体装置の
アウターリードの最先端側の表面の半田メッキ層に濡れ
た半田ペーストが、表面張力に基づき、アウターリード
の最先端の半田メッキ層が形成されていない端面を被覆
するので（周囲の半田ペーストがアウターリードの最先
端の端面において相互に連結されるので）、見かけ上、
アウターリードの最先端の端面に濡れ性を確保できる。According to the above-mentioned means (1), when the outer leads of the semiconductor device are electrically and mechanically connected to the terminals of the mounting substrate through the solder paste, the most distal side of the outer leads of the semiconductor device is obtained. Because the solder paste wet to the solder plating layer on the surface of the outer lead covers the end surface of the outer lead where the leading edge solder plating layer is not formed (the surrounding solder paste is the leading edge surface of the outer lead). Since they are connected to each other in), apparently,
The wettability can be secured on the end face of the outer lead.
【００２２】また、前記アウターリードの最先端の端面
に半田ペーストを付着でき、アウターリードと端子との
間の半田ペースト量を増加できるので、このアウターリ
ードと端子との接合強度を向上できる。Further, since the solder paste can be attached to the tip end face of the outer lead and the amount of the solder paste between the outer lead and the terminal can be increased, the joint strength between the outer lead and the terminal can be improved.
【００２３】上述した手段（２）によれば、前記半導体
装置のアウターリードの最先端の領域の機械的剛性が他
の領域に比べて緩和され、このアウターリードの最先端
の領域を曲げ易くでき、しかも、前記半導体装置のアウ
ターリードを半田ペーストを介在して実装基板の端子に
電気的かつ機械的に接続する場合、半導体装置のアウタ
ーリードの最先端側の曲げられた部分の半田メッキ層と
実装基板の端子との間に隙間が形成され、この隙間に半
田ペーストが溜り易くなるので、見かけ上、アウターリ
ードの最先端の端面に濡れ性を確保できるとともに、ア
ウターリードの最先端の領域の板厚が薄い分、前記作用
効果（１）と同様に、アウターリードの最先端の半田メ
ッキ層が形成されていない端面を半田ペーストで被覆で
きるので、より一層、アウターリードの最先端の端面に
濡れ性を確保できる。また、前記作用効果（１）と同様
に、接合強度を向上できる。According to the above-mentioned means (2), the mechanical rigidity of the tip region of the outer lead of the semiconductor device is relaxed as compared with other regions, and the tip region of the outer lead can be easily bent. Moreover, in the case where the outer leads of the semiconductor device are electrically and mechanically connected to the terminals of the mounting board through the solder paste, a solder plating layer on the bent portion of the outermost lead of the semiconductor device is formed. A gap is formed between the mounting board and the terminal, and the solder paste easily accumulates in this gap, so that it is possible to secure wettability to the tip end face of the outer lead and to improve the appearance of the tip region of the outer lead. Since the thickness of the plate is thin, the end surface of the outer lead on which the most advanced solder plating layer is not formed can be covered with the solder paste as in the case of the above-mentioned function and effect (1). , The wettability can be secured on the cutting edge end surface of the outer lead. In addition, the bonding strength can be improved as in the case of the above-mentioned function and effect (1).
【００２４】上述した手段（３）によれば、前記半導体
装置のアウターリードと実装基板の端子との間が半田ペ
ーストを介在して接続されていれば、アウターリードの
最先端の端面（半田メッキ層が形成されていない面）に
確実に半田ペーストが付着するので、接続されているに
もかかわらず、接続されていないと検出される、自動化
に基づく誤検査を低減できる。According to the above-mentioned means (3), if the outer lead of the semiconductor device and the terminal of the mounting substrate are connected via the solder paste, the most end face of the outer lead (solder plating) Since the solder paste surely adheres to the surface (on which the layer is not formed), it is possible to reduce erroneous inspection based on automation, which is detected as being not connected despite being connected.
【００２５】以下、本発明の構成について、ガルウィン
グ形状のアウターリードを有する半導体装置、組立技
術、実装技術及び外観検査技術に本発明を適用した一実
施例とともに説明する。The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a semiconductor device having a gull wing-shaped outer lead, an assembly technique, a mounting technique, and an appearance inspection technique.
【００２６】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００２７】[0027]
【実施例】本発明の一実施例であるガルウィング形状の
アウターリードを有する樹脂封止型半導体装置及びそれ
を実装した実装基板の構成を図１（部分断面側面図）で
示す。FIG. 1 (partial cross-sectional side view) shows the structure of a resin-sealed semiconductor device having a gull wing-shaped outer lead and a mounting board on which the same is mounted according to an embodiment of the present invention.
【００２８】図１に示すように、樹脂封止型半導体装置
１は、タブ２Ａ上に搭載された半導体ペレット４の外部
端子（ボンディングパッド）４Ｐとインナーリード２Ｃ
の一端とがボンディングワイヤ５で電気的に接続され、
このタブ２Ａ、インナーリード２Ｃ及び半導体ペレット
４が樹脂封止体９で封止される。As shown in FIG. 1, the resin-encapsulated semiconductor device 1 includes an external terminal (bonding pad) 4P of a semiconductor pellet 4 mounted on a tab 2A and an inner lead 2C.
Is electrically connected with one end of the bonding wire 5.
The tab 2A, the inner lead 2C and the semiconductor pellet 4 are sealed with a resin sealing body 9.
【００２９】前記半導体ペレット４は、その詳細な断面
構造を示していないが、例えば単結晶珪素基板で形成さ
れ、その素子形成面（図１中、上側表面）に所定の回路
システムが搭載される。外部端子４Ｐは、半導体ペレッ
ト４の素子形成面上に複数個配置され、例えば回路シス
テムを構成する半導体素子間を結線する配線（例えばア
ルミニウム合金）と同一層で形成される。Although the semiconductor pellet 4 does not show its detailed sectional structure, it is formed of, for example, a single crystal silicon substrate, and a predetermined circuit system is mounted on the element formation surface (the upper surface in FIG. 1). . A plurality of external terminals 4P are arranged on the element formation surface of the semiconductor pellet 4, and are formed in the same layer as, for example, a wiring (for example, an aluminum alloy) that connects between semiconductor elements forming a circuit system.
【００３０】半導体ペレット４、タブ２Ａの夫々は、両
者間に接着層３例えばＡｇペーストを介在し、固着され
る。ボンディングワイヤ５としては例えばＡｕワイヤが
使用される。The semiconductor pellet 4 and the tab 2A are fixed to each other with an adhesive layer 3 such as Ag paste interposed therebetween. As the bonding wire 5, for example, an Au wire is used.
【００３１】樹脂封止体９は、トランスファモールド法
で成型され、例えばフェノール硬化型エポキシ系樹脂が
使用される。The resin encapsulant 9 is molded by the transfer molding method and, for example, phenol-curable epoxy resin is used.
【００３２】前記インナーリード２Ｃの他端は、図１及
び図４（組立プロセスの半導体ペレット４の搭載及びボ
ンディングワイヤ５がボンディングされた工程が完了し
た時点のリードフレームの平面図）に示すように、アウ
ターリード２Ｄの一端に一体に構成されかつ電気的に接
続される。インナーリード２Ｃ及びアウターリード２Ｄ
は、図４に示すように、リードフレームの切断成型工程
前において、タイバー２Ｆを介在して枠体２Ｇに連結さ
れており、結果的に同一リードフレームに連結され支持
される。アウターリード２Ｄは、リードフレームから切
断され切り離されるとともに、ガルウィング形状に成型
される。同様に、タブ２Ａはタブ吊りリード２Ｂを介在
してリードフレームに連結され支持される。The other end of the inner lead 2C is as shown in FIGS. 1 and 4 (plan view of the lead frame at the time when the steps of mounting the semiconductor pellet 4 and bonding the bonding wire 5 are completed in the assembly process). , Is integrally configured and electrically connected to one end of the outer lead 2D. Inner lead 2C and outer lead 2D
As shown in FIG. 4, the lead frame is connected to the frame body 2G through the tie bar 2F before the lead frame cutting and molding process, and as a result, is connected to and supported by the same lead frame. The outer lead 2D is cut and separated from the lead frame and molded into a gull wing shape. Similarly, the tab 2A is connected to and supported by the lead frame via the tab suspension lead 2B.
【００３３】リードフレームは、例えばＦｅ−Ｎｉ合金
（Ｎｉ含有量４２又は５０［％］）、Ｃｕ、Ｃｕ合金の
いずれかの板材で形成され、この板材にエッチング加工
又はプレス加工を施すことにより、インナーリード２Ｃ
等のパターンが形成される。The lead frame is made of, for example, a plate material of Fe-Ni alloy (Ni content 42 or 50 [%]), Cu, or Cu alloy, and by subjecting this plate material to etching or pressing, Inner lead 2C
And the like are formed.
【００３４】リードフレームのうち少なくともインナー
リード２Ｃの一端側のボンディング領域（ボンディング
ワイヤ５がボンディングされる領域）は、図１に示すよ
うに、Ａｇメッキ層６が形成される。このＡｇメッキ層
６は、インナーリード２Ｃにボンディングワイヤ６をボ
ンディングする際に、ボンダビリティを向上できる。As shown in FIG. 1, an Ag plating layer 6 is formed in at least the bonding region (region where the bonding wire 5 is bonded) on one end side of the inner lead 2C in the lead frame. The Ag plated layer 6 can improve bondability when the bonding wire 6 is bonded to the inner lead 2C.
【００３５】また、リードフレームのうち少なくともア
ウターリード２Ｄの表面には半田メッキ（例えばＰｂ−
Ｓｎ）層７が形成される。半田メッキ層７は、後述する
実装基板（１０）の実装面に配置された端子（１１）に
半田ペースト（８）を介在して電気的かつ機械的にアウ
ターリード２Ｄを接続する場合、アウターリード２Ｄの
表面の半田ペースト（８）の濡れ性を向上できる。半田
メッキ層７は、この数値に限定されないが、例えば １.
５〜１０［μｍ］の膜厚で形成される。Further, at least the surface of the outer lead 2D of the lead frame is plated with solder (for example, Pb-
Sn) layer 7 is formed. When the outer lead 2D is electrically and mechanically connected to the terminal (11) arranged on the mounting surface of the mounting substrate (10) described later by interposing the solder paste (8), the solder plating layer 7 is an outer lead. The wettability of the solder paste (8) on the 2D surface can be improved. The solder plating layer 7 is not limited to this value, for example, 1.
It is formed with a film thickness of 5 to 10 [μm].
【００３６】この半田メッキ層７は、所謂半田後付け方
法を使用する本実施例の場合、樹脂封止体９による樹脂
封止工程が終了した後、リードフレームからアウターリ
ード２Ｄ等を切断し成型する工程前において形成され
る。結果的に、半田メッキ層７は樹脂封止体９の外部に
引出されるアウターリード２Ｄのすべての表面に形成さ
れる（基本的には実装基板１０側の一部の表面に形成さ
れてもよい）。また、半田メッキ層７は、半田先付け方
法を使用する場合、前述のエッチング加工、プレス加工
のいずれかでリードフレームを形成する工程の後、樹脂
封止体９による樹脂封止工程前において形成される。In the case of the present embodiment using the so-called solder post-mounting method, the solder plating layer 7 is formed by cutting the outer lead 2D and the like from the lead frame after the resin sealing step by the resin sealing body 9 is completed. It is formed before the process. As a result, the solder plating layer 7 is formed on the entire surface of the outer lead 2D that is drawn out of the resin encapsulation body 9 (basically, even if formed on a part of the surface of the mounting substrate 10 side). Good). Further, when the solder pre-attachment method is used, the solder plating layer 7 is formed after the step of forming the lead frame by any of the above-described etching processing and pressing processing and before the resin sealing step by the resin sealing body 9. It
【００３７】前記図１及び図２（アウターリードの実装
状態における要部拡大図）に示すように、アウターリー
ド２Ｄの他端すなわち実装基板（１０）の端子（１１）
に接続される側の最先端の領域２Ｅは、それ以外の他の
領域のアウターリード２Ｄ若しくはインナーリード２Ｃ
の板厚に比べて部分的に薄い板厚で構成される。例え
ば、リードフレームとしてＦｅ−Ｎｉ合金を使用し、リ
ードフレーム（アウターリード２Ｄの最先端の領域２Ｅ
以外）の板厚が ０.１５［μｍ］の場合、アウターリー
ド２Ｄの最先端の領域２Ｅは、約０.０７〜０.０８［μ
ｍ］の板厚で形成され、約半分の板厚に形成される。ま
た、アウターリード２Ｄの最先端の領域２Ｅは、リード
フレームから切り離す際の切断領域を兼ね、この切断領
域の寸法及び板厚の薄い領域を確保するため、リード長
方向に約０.１〜０.２［μｍ］の長さで構成される。ア
ウターリード２Ｄの最先端の領域２Ｅは、基本的に最先
端の端面の断面積が他の断面積に比べて小さくされれば
よく、実装時、最先端の端面の周囲に存在する半田ペー
スト（８）が表面張力などにより相互に連結され、この
最先端の端面を半田ペースト（８）で被覆する形状で構
成される。As shown in FIGS. 1 and 2 (enlarged view of a main part in a mounted state of the outer lead), the other end of the outer lead 2D, that is, the terminal (11) of the mounting substrate (10).
The outermost region 2E on the side connected to the outer lead 2D or inner lead 2C of the other region is
The plate thickness is partially thin compared to the plate thickness. For example, an Fe-Ni alloy is used as the lead frame, and the lead frame (the outermost area 2E of the outer lead 2D is used).
(Except the other) is 0.15 [μm], the outermost region 2E of the outer lead 2D has a thickness of about 0.07 to 0.08 [μm].
m], and the plate thickness is about half. In addition, the frontmost region 2E of the outer lead 2D also serves as a cutting region when the lead frame is separated from the lead frame. It has a length of 0.2 [μm]. The tip end region 2E of the outer lead 2D basically needs to have a smaller cross-sectional area of the tip end face as compared with other cross-sectional areas, and the solder paste existing around the tip end face during mounting ( 8) are connected to each other by surface tension or the like, and the tip end face is covered with the solder paste (8).
【００３８】このように構成される樹脂封止型半導体装
置１は、図１及び図２に示すように、ＰＣＢ基板等の実
装基板１０に実装される。実装基板１０への樹脂封止型
半導体装置１の実装は実装基板１０の実装面に配置され
た端子１１に半田ペースト８を介在してアウターリード
２Ｄを電気的かつ機械的に接続することで行われる。こ
のとき、アウターリード２Ｄの最先端の領域２Ｅが薄い
板厚で形成され、このアウターリード２Ｄの最先端の端
面の断面積が小さくされているので、この最先端の端面
の周囲の半田メッキ層７で濡れた半田ペースト８が表面
張力などで相互に連結され、アウターリード２Ｄの最先
端の端面に半田ペースト８が付着する。つまり、アウタ
ーリード２Ｄの最先端の端面は、見かけ上、濡れ性が確
保される。この結果、アウターリード２Ｄと端子１１と
の接続部分での半田ペースト８の量が、アウターリード
２Ｄの最先端の端面に半田ペースト８が付着する分、増
加できるので、アウターリード２Ｄと端子１１との接続
強度が向上できる。The resin-encapsulated semiconductor device 1 thus constructed is mounted on a mounting substrate 10 such as a PCB substrate, as shown in FIGS. The resin-encapsulated semiconductor device 1 is mounted on the mounting board 10 by electrically and mechanically connecting the outer leads 2D to the terminals 11 arranged on the mounting surface of the mounting board 10 with the solder paste 8 interposed. Be seen. At this time, the tip end region 2E of the outer lead 2D is formed with a thin plate thickness, and the cross-sectional area of the tip end face of the outer lead 2D is reduced, so that the solder plating layer around the tip end face is formed. The solder pastes 8 wetted by 7 are connected to each other by surface tension or the like, and the solder pastes 8 adhere to the end faces of the outer leads 2D. That is, the tip end face of the outer lead 2D is apparently wettable. As a result, the amount of the solder paste 8 at the connecting portion between the outer lead 2D and the terminal 11 can be increased by the amount of the solder paste 8 attached to the tip end face of the outer lead 2D. The connection strength of can be improved.
【００３９】一方、前記アウターリード２Ｄと端子１１
との接続部分において、アウターリード２Ｄの最先端の
端面に半田ペースト８が付着されるので、外観不良検査
を自動的に行う場合に、アウターリード２Ｄと端子１１
とが確実に接続されていれば、アウターリード２Ｄの最
先端の端面に半田ペースト８が付着し、誤った検査結果
の出力が低減できる。On the other hand, the outer lead 2D and the terminal 11
Since the solder paste 8 is attached to the tip end face of the outer lead 2D at the connection portion with the outer lead 2D and the terminal 11 when the visual defect inspection is automatically performed.
If the and are securely connected, the solder paste 8 adheres to the tip end face of the outer lead 2D, and the output of an erroneous inspection result can be reduced.
【００４０】また、図３（アウターリードの実装状態に
おける要部拡大図）に示すように、樹脂封止型半導体装
置１において、アウターリード２Ｄの最先端の領域２Ｅ
の板厚を薄くし、この最先端の領域２Ｅを端子１１との
接続面から離れる方向に曲げてもよい。この場合、アウ
ターリード２Ｄの最先端の領域２Ｅと端子１１との間に
隙間が形成され、この隙間に半田ペースト８を溜めるこ
とができるので、アウターリード２Ｄと端子１１との接
続強度が向上でき、さらに、前述と同様に、アウターリ
ード２Ｄの最先端の領域２Ｅの板厚が薄いので、最先端
の端面などに半田ペースト８が付着し、より接続強度を
向上できる。Further, as shown in FIG. 3 (enlarged view of a main part in a mounted state of the outer lead), in the resin-sealed semiconductor device 1, the most advanced region 2E of the outer lead 2D.
It is also possible to reduce the plate thickness of and to bend this front end region 2E in the direction away from the connection surface with the terminal 11. In this case, a gap is formed between the tip end region 2E of the outer lead 2D and the terminal 11, and the solder paste 8 can be stored in this gap, so that the connection strength between the outer lead 2D and the terminal 11 can be improved. Further, similarly to the above, since the plate thickness of the tip region 2E of the outer lead 2D is thin, the solder paste 8 adheres to the tip end face or the like, and the connection strength can be further improved.
【００４１】この図３に示すアウターリード２Ｄの最先
端の領域２Ｅの加工は、図５、図６（切断成型装置での
切断工程、成型工程毎に示す概略図）の夫々に示す以下
の順序で行われる。The processing of the frontmost region 2E of the outer lead 2D shown in FIG. 3 is performed in the following order shown in each of FIGS. 5 and 6 (cutting process by a cutting and molding apparatus, a schematic diagram showing each molding process). Done in.
【００４２】まず、図５に示すように、樹脂封止体９を
形成した後の樹脂封止型半導体装置１をダイ２０に装着
し、併せてリードフレームをダイ２１及びストッパ２２
で挟持する。リードフレームの挟持はダイ２１及びスト
ッパ２２の外部にアウターリード２Ｄの最先端の領域２
Ｅを突出して（この領域が切断個所となる）行う。First, as shown in FIG. 5, the resin-encapsulated semiconductor device 1 on which the resin encapsulant 9 has been formed is mounted on the die 20, and the lead frame is also attached to the die 21 and the stopper 22.
Sandwich with. The lead frame is sandwiched between the die 21 and the stopper 22 by cutting the outer lead 2D at the most advanced area 2
E is projected (this area is the cutting point).
【００４３】次に、前記アウターリード２Ｄの最先端の
領域２Ｅの一部をパンチ２４で切断する。このパンチ２
４の先端の切断刃は図５に示すように傾斜面が構成さ
れ、この切断刃の傾斜面の形状は前述の図３に示すアウ
ターリード２Ｄの最先端の領域２Ｅの曲げられた形状に
相当する。つまり、アウターリード２Ｄの最先端の領域
２Ｅを切断する工程において、このアウターリード２Ｄ
の最先端の領域２Ｅを曲げることができる。Next, a part of the leading edge region 2E of the outer lead 2D is cut by the punch 24. This punch 2
The cutting blade at the tip of No. 4 has an inclined surface as shown in FIG. 5, and the shape of the inclined surface of this cutting blade corresponds to the bent shape of the frontmost region 2E of the outer lead 2D shown in FIG. To do. That is, in the step of cutting the outermost region 2E of the outer lead 2D, the outer lead 2D
It is possible to bend the most advanced region 2E of the.
【００４４】次に、図６に示すように、切断されたアウ
ターリード２Ｄは、ノックアウト２３で押し下げられる
とともに、ダイ２０の金型に沿って成型され、ガルウィ
ング形状に形成される。Next, as shown in FIG. 6, the cut outer lead 2D is pushed down by the knockout 23 and is molded along the mold of the die 20 to form a gull wing shape.
【００４５】このように、本実施例によれば、以下の作
用効果が得られる。As described above, according to this embodiment, the following operational effects can be obtained.
【００４６】（１）ガルウィング形状のアウターリード
２Ｄの表面にこのアウターリード２Ｄが実装基板１０の
端子１１に接続される側の最先端の端面の領域を除き半
田メッキ層７が形成される樹脂封止型半導体装置１にお
いて、前記アウターリード２Ｄの最先端の端面の半田メ
ッキ層７が形成されていない領域の断面積がそれ以外の
領域のアウターリード２Ｄの断面積に比べて小さく構成
される。前記アウターリード２Ｄの最先端の端面は、そ
れ以外の領域のアウターリード２Ｄの板厚に比べて薄く
構成され、断面積が小さく構成される。この構成によ
り、前記樹脂封止型半導体装置１のアウターリード２Ｄ
を半田ペースト８を介在して実装基板１０の端子１１に
電気的かつ機械的に接続する場合、樹脂封止型半導体装
置１のアウターリード２Ｄの最先端側の表面の半田メッ
キ層７に濡れた半田ペースト８が、表面張力に基づき、
アウターリード２Ｄの最先端の半田メッキ層７が形成さ
れていない端面を被覆するので（周囲の半田ペースト８
がアウターリード２Ｄの最先端の端面において相互に連
結されるので）、見かけ上、アウターリード２Ｄの最先
端の端面に濡れ性を確保できる。また、前記アウターリ
ード２Ｄの最先端の端面に半田ペースト８を付着でき、
アウターリード２Ｄと端子１１との間の半田ペースト８
量を増加できるので、このアウターリード２Ｄと端子１
１との接合強度を向上できる。(1) A resin sealing in which the solder plating layer 7 is formed on the surface of the gull wing-shaped outer lead 2D except for the region of the tip end face on the side where the outer lead 2D is connected to the terminal 11 of the mounting substrate 10. In the static semiconductor device 1, the cross-sectional area of the region where the solder plating layer 7 is not formed on the tip end face of the outer lead 2D is smaller than the cross-sectional area of the outer lead 2D in the other regions. The tip end face of the outer lead 2D is made thinner than the plate thickness of the outer lead 2D in other regions, and the cross-sectional area is made smaller. With this configuration, the outer lead 2D of the resin-sealed semiconductor device 1
Is electrically and mechanically connected to the terminals 11 of the mounting substrate 10 with the solder paste 8 interposed, the solder plating layer 7 on the tip end surface of the outer lead 2D of the resin-sealed semiconductor device 1 gets wet. Based on the surface tension, the solder paste 8
Since the end surface of the outer lead 2D on which the most advanced solder plating layer 7 is not formed is covered (the surrounding solder paste 8
Are connected to each other at the tip end surface of the outer lead 2D), so that the tip end surface of the outer lead 2D can be apparently wetted. Further, the solder paste 8 can be attached to the most end face of the outer lead 2D,
Solder paste 8 between outer lead 2D and terminal 11
Since the quantity can be increased, this outer lead 2D and terminal 1
The joint strength with No. 1 can be improved.
【００４７】（２）ガルウィング形状のアウターリード
２Ｄの表面にこのアウターリード２Ｄが実装基板１０の
端子１１に接続される側の最先端の端面の領域を除き半
田メッキ層７が形成される樹脂封止型半導体装置１にお
いて、前記アウターリード２Ｄの最先端の半田メッキ層
７が形成されていない端面を含む領域（２Ｅに相当す
る）の板厚がそれ以外の領域のアウターリード２Ｄの板
厚に比べて薄く構成され、このアウターリード２Ｄの最
先端の板厚の薄い領域が実装基板１０の端子１１に接続
される面から離れる方向に曲げられる。この構成によ
り、前記樹脂封止型半導体装置１のアウターリード２Ｄ
の最先端の領域の機械的剛性が他の領域に比べて緩和さ
れ、このアウターリード２Ｄの最先端の領域を曲げ易く
でき、しかも、前記樹脂封止型半導体装置１のアウター
リード２Ｄを半田ペースト８を介在して実装基板１０の
端子１１に電気的かつ機械的に接続する場合、樹脂封止
型半導体装置１のアウターリード２Ｄの最先端側の曲げ
られた部分の半田メッキ層７と実装基板１０の端子１１
との間に隙間が形成され、この隙間に半田ペースト８が
溜り易くなるので、見かけ上、アウターリード２Ｄの最
先端の端面に濡れ性を確保できるとともに、アウターリ
ード２Ｄの最先端の領域の板厚が薄い分、前記作用効果
（１）と同様に、アウターリード２Ｄの最先端の半田メ
ッキ層７が形成されていない端面を半田ペースト８で被
覆できるので、より一層、アウターリード２Ｄの最先端
の端面に濡れ性を確保できる。また、前記作用効果
（１）と同様に、接合強度を向上できる。(2) A resin seal in which the solder plating layer 7 is formed on the surface of the gull wing-shaped outer lead 2D except for the region of the most end face on the side where the outer lead 2D is connected to the terminal 11 of the mounting substrate 10. In the static semiconductor device 1, the plate thickness of a region (corresponding to 2E) including the end face of the outer lead 2D where the frontmost solder plating layer 7 is not formed is equal to the plate thickness of the outer lead 2D in other regions. Compared with this, the outermost lead thin region of the outer lead 2D is bent in a direction away from the surface of the mounting substrate 10 connected to the terminal 11. With this configuration, the outer lead 2D of the resin-sealed semiconductor device 1
Of the outer lead 2D can be easily bent, and the outer lead 2D of the resin-sealed semiconductor device 1 can be solder-pasted. 8 is electrically and mechanically connected to the terminal 11 of the mounting substrate 10 with the solder plating layer 7 and the mounting substrate of the bent portion of the outer lead 2D of the resin-encapsulated semiconductor device 1 on the most distal side thereof. Terminal 11 of 10
Since a gap is formed between the outer lead 2D and the solder paste 8 and the solder paste 8 easily accumulates in the gap, it is possible to apparently ensure wettability on the end face of the outer lead 2D and the plate in the end region of the outer lead 2D. Since the thickness is thin, the end face of the outer lead 2D where the leading edge solder plating layer 7 is not formed can be covered with the solder paste 8 as in the case of the above-described function and effect (1). The wettability can be secured on the end surface of. In addition, the bonding strength can be improved as in the case of the above-mentioned function and effect (1).
【００４８】（３）前記樹脂封止型半導体装置１は、そ
のアウターリード２Ｄの最先端の領域と実装基板１０の
端子１１との間を半田ペースト８を介在して電気的かつ
機械的に接続した後に、前記アウターリード２Ｄの最先
端の端面に半田ペースト８が付着しているか否かを自動
的に検出する不良品検査が行われる。この構成により、
前記樹脂封止型半導体装置１のアウターリード２Ｄと実
装基板１０の端子１１との間が半田ペースト８を介在し
て接続されていれば、アウターリード２Ｄの最先端の端
面（半田メッキ層７が形成されていない面）に確実に半
田ペースト８が付着するので、接続されているにもかか
わらず、接続されていないと検出される、自動化に基づ
く誤った検査結果を低減できる。(3) The resin-encapsulated semiconductor device 1 electrically and mechanically connects the leading edge region of the outer lead 2D and the terminal 11 of the mounting substrate 10 with the solder paste 8 interposed therebetween. After that, a defective product inspection is automatically performed to automatically detect whether or not the solder paste 8 is attached to the end face of the outer lead 2D. With this configuration,
If the outer lead 2D of the resin-encapsulated semiconductor device 1 and the terminal 11 of the mounting substrate 10 are connected via the solder paste 8, the most end face of the outer lead 2D (the solder plating layer 7 is Since the solder paste 8 surely adheres to the non-formed surface), it is possible to reduce erroneous inspection results based on automation, which are detected as being not connected even though they are connected.
【００４９】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００５０】例えば、本発明は、前記樹脂封止型半導体
装置１のアウターリード２Ｄの最先端の領域の角部を面
取りし、部分的にリード幅寸法を小さくしてもよい。For example, according to the present invention, the lead width dimension may be partially reduced by chamfering the corners of the outermost lead 2D of the resin-sealed semiconductor device 1 at the tip end region.
【００５１】また、本発明は、フラット形状のアウター
リードを有する樹脂封止型半導体装置に適用できる。Further, the present invention can be applied to a resin-sealed semiconductor device having a flat outer lead.
【００５２】また、本発明は、樹脂封止型半導体装置に
限らず、ガルウィング形状、フラット形状等所謂面実装
タイプのセラミック封止型（ガラス封止型）半導体装置
に適用できる。The present invention can be applied not only to the resin-sealed semiconductor device but also to a so-called surface mounting type ceramic-sealed (glass-sealed) semiconductor device such as a gull wing shape or a flat shape.
【００５３】[0053]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００５４】（Ａ）ガルウィング形状又はフラット形状
のアウターリードの表面に最先端の端面を除き半田メッ
キ層が形成される半導体装置において、前記アウターリ
ードの最先端の端面の濡れ性を向上できる。(A) In a semiconductor device in which a solder-plated layer is formed on the surface of a gull wing-shaped or flat outer lead except the tip end face, the wettability of the tip end face of the outer lead can be improved.
【００５５】（Ｂ）前記半導体装置を実装基板に実装し
た際の接合強度を向上できる。(B) The bonding strength when the semiconductor device is mounted on a mounting substrate can be improved.
【００５６】（Ｃ）前記半導体装置を実装基板に実装し
た後に行われる外観不良検査の自動化において、誤検査
を低減し、外観不良検査の精度を向上できる。(C) In the automation of the appearance defect inspection performed after the semiconductor device is mounted on the mounting substrate, it is possible to reduce the erroneous inspection and improve the accuracy of the appearance defect inspection.
【図１】本発明の一実施例であるガルウィング形状のア
ウターリードを有する樹脂封止型半導体装置及びそれを
実装した実装基板の構成を示す部分断面側面図。FIG. 1 is a partial cross-sectional side view showing a configuration of a resin-sealed semiconductor device having a gull wing-shaped outer lead according to an embodiment of the present invention and a mounting substrate on which the resin-sealed semiconductor device is mounted.
【図２】前記樹脂封止型半導体装置のアウターリードの
実装状態における要部拡大図。FIG. 2 is an enlarged view of a main part of the resin-sealed semiconductor device in a mounted state of outer leads.
【図３】前記アウターリードの実装状態における他の例
を示す要部拡大図。FIG. 3 is an enlarged view of a main part showing another example of a mounted state of the outer lead.
【図４】前記樹脂封止型半導体装置で使用されるリード
フレームの平面図。FIG. 4 is a plan view of a lead frame used in the resin-sealed semiconductor device.
【図５】前記リードフレームの切断工程を示す概略図。FIG. 5 is a schematic view showing a cutting process of the lead frame.
【図６】前記リードフレームの成型工程を示す概略図。FIG. 6 is a schematic view showing a molding process of the lead frame.
１…樹脂封止型半導体装置、２Ａ…タブ、２Ｃ…インナ
ーリード、２Ｄ…アウターリード、２Ｅ…最先端の領
域、４…半導体ペレット、７…半田メッキ層、８…半田
ペースト、９…樹脂封止体、１０…実装基板、１１…端
子、２０，２１…ダイ、２２…ストッパ、２３…ノック
アウト、２４…パンチ。DESCRIPTION OF SYMBOLS 1 ... Resin-sealed semiconductor device, 2A ... Tab, 2C ... Inner lead, 2D ... Outer lead, 2E ... Cutting edge area, 4 ... Semiconductor pellet, 7 ... Solder plating layer, 8 ... Solder paste, 9 ... Resin seal Stop body, 10 ... Mounting substrate, 11 ... Terminal, 20, 21 ... Die, 22 ... Stopper, 23 ... Knockout, 24 ... Punch.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田中 茂樹 北海道亀田郡七飯町字中島145番地 日立 北海セミコンダクタ株式会社内 (72)発明者 明山 健二 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 大塚 憲一 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 増田 正親 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 鈴木 博通 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 (72)発明者 木本 良輔 東京都小平市上水本町５丁目22番１号 株 式会社日立マイコンシステム内 (72)発明者 寺田 和弘 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所武蔵工場内 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Shigeki Tanaka Hitachi, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside North Sea Semiconductor Co., Ltd. (72) Inventor Kenji Akiyama 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Kenichi Otsuka 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Masachika Masuda 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Hiromichi Suzuki 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony company Hitachi Ltd. Musashi factory (72) Inventor Ryosuke Kimoto 5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Inside the Hitachi Microcomputer System (72) Inventor Kazuhiro Terada 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony company Hitachi Ltd. Musashi factory
Claims (4)
ウターリードの表面にこのアウターリードが実装基板の
端子に接続される側の最先端の端面の領域を除き半田メ
ッキ層が形成される半導体装置において、前記アウター
リードの最先端の端面の半田メッキ層が形成されていな
い領域の断面積がそれ以外の領域のアウターリードの断
面積に比べて小さく構成されたことを特徴とする半導体
装置。1. A semiconductor device in which a solder-plated layer is formed on the surface of a gull wing-shaped or flat-shaped outer lead except for the region of the tip end face on the side where the outer lead is connected to a terminal of a mounting substrate. A semiconductor device characterized in that a cross-sectional area of a region where a solder plating layer is not formed on a tip end face of the outer lead is smaller than a cross-sectional area of the outer lead in other regions.
最先端の端面は、それ以外の領域のアウターリードの板
厚に比べて薄く構成され、又はそれ以外の領域のアウタ
ーリードのリード幅寸法に比べて小さく構成され、断面
積が小さく構成されたことを特徴とする。2. The outermost end face of the outer lead according to claim 1 is configured to be thinner than the plate thickness of the outer lead in the other region, or the lead width dimension of the outer lead in the other region. It is characterized in that it has a smaller cross-sectional area and a smaller cross-sectional area.
ウターリードの表面にこのアウターリードが実装基板の
端子に接続される側の最先端の端面の領域を除き半田メ
ッキ層が形成される半導体装置において、前記アウター
リードの最先端の半田メッキ層が形成されていない端面
を含む領域の板厚がそれ以外の領域のアウターリードの
板厚に比べて薄く構成され、このアウターリードの最先
端の板厚の薄い領域が実装基板の端子に接続される面か
ら離れる方向に曲げられたことを特徴とする半導体装
置。3. A semiconductor device in which a solder plating layer is formed on the surface of a gull wing-shaped or flat-shaped outer lead except for a region of the most end face on the side where the outer lead is connected to a terminal of a mounting board. The thickness of the outer lead including the end surface where the solder plating layer is not formed is thinner than the thickness of the outer lead in other areas, and the outer lead is thin. A semiconductor device, wherein the region is bent in a direction away from a surface of the mounting substrate that is connected to the terminal.
記載の半導体装置は、そのアウターリードの最先端の領
域と実装基板の端子との間を半田ペーストを介在して電
気的かつ機械的に接続した後に、前記アウターリードの
最先端の端面に半田ペーストが付着しているか否かを自
動的に検出する不良品検査が行われることを特徴とす
る。4. The semiconductor device according to claim 1, wherein the semiconductor device is electrically and mechanically disposed with a solder paste interposed between the tip end region of the outer lead and the terminal of the mounting substrate. After the electrical connection, a defective product inspection is automatically performed to automatically detect whether or not the solder paste is attached to the tip end face of the outer lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3152881A JPH053277A (en) | 1991-06-25 | 1991-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3152881A JPH053277A (en) | 1991-06-25 | 1991-06-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH053277A true JPH053277A (en) | 1993-01-08 |
Family
ID=15550162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3152881A Withdrawn JPH053277A (en) | 1991-06-25 | 1991-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH053277A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2927953A2 (en) | 2014-03-13 | 2015-10-07 | Renesas Electronics Corporation | Semiconductor device |
| EP4124678A1 (en) | 2021-07-28 | 2023-02-01 | Mitsui High-Tec, Inc. | Metal component |
-
1991
- 1991-06-25 JP JP3152881A patent/JPH053277A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2927953A2 (en) | 2014-03-13 | 2015-10-07 | Renesas Electronics Corporation | Semiconductor device |
| US10032700B2 (en) | 2014-03-13 | 2018-07-24 | Renesas Electronics Corporation | Positional relationship among components of semiconductor device |
| US10461020B2 (en) | 2014-03-13 | 2019-10-29 | Renesas Electronics Corporation | Positional relationship among components of semiconductor device |
| US10796983B2 (en) | 2014-03-13 | 2020-10-06 | Renesas Electronics Corporation | Positional relationship among components of semiconductor device |
| EP4124678A1 (en) | 2021-07-28 | 2023-02-01 | Mitsui High-Tec, Inc. | Metal component |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980903 |