JP2003188332A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost. <P>SOLUTION: A lead frame 1 is provided with a tab 1b, a lifting tab 1e extending to the outside, and a plurality leads, and it is worked to lower the tab. After a semiconductor chip 2 is mounted to the tab 1b of the lead frame 1, the surface electrode of the semiconductor chip 2 is connected with the corresponding lead by a wire, and the semiconductor chip 2 is packaged by resin so that the rear surface 1d of the tab 1 and a part of the lead may expose on the rear surface. Thus, resin molding can be applied in such a state that the tab 1b is closely in contact with a lower mold 7, resulting in exposing the tab 1b on the rear surface of the packaged part surely. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly, to a technique effectively applied to cost reduction of a peripheral type semiconductor device.

[0002]

2. Description of the Related Art The techniques described below are for studying the present invention,
The present invention was studied by the present inventors upon completion, and its outline is as follows.

A CSP (Chip Scale Package) or a QFN is used as a resin-encapsulated semiconductor device which is miniaturized.
A small semiconductor package called a (Quad Flat Non-leaded Package) with a chip size or slightly larger than a semiconductor chip has been developed.

In QFN, the back surface of the sealing portion (the surface on the mounting side)
A plurality of leads are arranged on the peripheral edge of the so as to expose the connection surface, and the semiconductor package having such a structure is called a peripheral type.

Further, the QFN has a structure in which a tab for supporting a semiconductor chip is exposed on the back surface of the sealing portion (hereinafter referred to as a tab exposure structure), and a structure in which the tab is embedded and not exposed in the sealing portion ( Hereinafter, this is referred to as a tab embedding structure).

[0006] Among them, in the QFN having the tab exposed structure, the following two types of methods are generally known as the tab exposing method in the assembling.

In the first method, an adhesive tape is attached to the back surface of the lead frame in advance, and in this state, die bonding, wire bonding, and resin sealing are performed. After resin molding, the adhesive tape is peeled off to remove the tab. It is a method of exposing.

The second method is a resin molding method called laminate molding, in which film tapes are arranged on the front and back surfaces of the lead frame in the molding die, and the lead frame is bitten into the tape for molding. Is the method of exposing the tab.

A semiconductor device having a tab exposed structure is described in, for example, Japanese Patent Application Laid-Open No. 8-83870.

[0010]

However, since the adhesive tape or the film tape is used in the assembly of the semiconductor device having the tab exposed structure, there is a problem that the manufacturing cost of the semiconductor device is increased.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the manufacturing cost.

Another object of the present invention is to provide a semiconductor device in which the thickness of a semiconductor chip can be increased without changing the package height and a method for manufacturing the same.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, a sealing portion in which a semiconductor chip is sealed with a resin, a tab that supports the semiconductor chip and is exposed on a mounting side surface of the sealing portion, and the tab are integrally formed from the tab. A suspension lead extending outward, a plurality of leads partially exposed at the peripheral portion of the mounting side surface of the sealing portion, and a wire connecting the surface electrode of the semiconductor chip and the lead. And a recessed portion that engages with the sealing portion is formed on the surface of the suspension lead opposite to the mounting surface.

Further, the present invention has a lead frame having a tab, a suspension lead extending outward from the tab, and a plurality of leads, and the tab being arranged in a surface direction on the mounting side of the suspension lead. , A step of mounting the semiconductor chip on the tab, a step of connecting the surface electrode of the semiconductor chip and the lead with a wire, a surface of the tab opposite to the chip supporting surface and the lead. A step of resin-sealing the semiconductor chip so that a part of it is exposed to the mounting side surface of the sealing portion, and a step of separating the lead from the lead frame.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view showing an example of the structure of a semiconductor device (QFN) according to Embodiment 1 of the present invention through a sealing portion, and FIG. 2 is AA of FIG. Sectional drawing which shows the structure of the cross section cut | disconnected along the line, FIG. 3 is QFN shown in FIG.
FIG. 4 is a bottom view showing the structure of FIG. 1 through a sealing portion, FIG. 4 is a manufacturing process flow chart showing an example of an assembly procedure of the QFN shown in FIG. 1, and FIG. 5 is a lead frame used for assembling the QFN shown in FIG. Side view showing an example of the structure, FIG. 6, FIG.
FIG. 8 is a side view, a partial cross-sectional view and a cross-sectional view showing an example of a structure after die bonding, during resin molding and after resin molding of the assembly of the QFN shown in FIG. 1, and FIG. 9 shows assembly of the modified QFN. FIG. 1 is a side view showing an example of the structure of a lead frame used.
0, FIG. 11 and FIG. 12 are, respectively, after the die bonding of the assembly of the QFN of the modified example, at the time of resin molding,
A side view, a partial cross-sectional view and a cross-sectional view showing an example of the structure after resin molding, FIG. 12 is a cross-sectional view showing an example of the structure after resin molding in assembly of a QFN of a modified example, and FIG. 13 is a lead frame of a modified example. FIG. 14 is a side view showing a structure, and FIG. 14 is a side view showing a structure of a modified lead frame.

The semiconductor device according to the first embodiment is a resin-sealed and surface-mount type small semiconductor package. Here, QFN5 will be described as an example of the semiconductor device.

As shown in FIG. 3, the QFN 5 has a surface (part) 1g to be connected (partial) to the leads 1a which are a plurality of external terminals.
Is a peripheral type semiconductor package that is arranged and exposed side by side with a peripheral portion of a mounting side surface (hereinafter referred to as a back surface 3a) of the sealing portion 3 formed by resin molding, and each lead 1a is sealed. It also functions as both the inner lead embedded in the stopper 3 and the outer lead exposed on the back surface 3 a of the sealing portion 3.

Further, the tab 1b on which the semiconductor chip 2 is mounted is exposed on the back surface 3a of the sealing portion 3 so that the tab is exposed.

The detailed structure of the QFN 5 will be described with reference to FIGS. 1 to 3. A tab 1b in the form of a thin plate that supports the semiconductor chip 2 and a sealing portion 3 formed by resin-sealing the semiconductor chip 2 are described. , The suspension lead 1e that integrally supports the tab 1b and extends straight from the tab 1b toward the outside, and the connected surface 1g are arranged so as to be exposed at the peripheral edge of the back surface 3a of the sealing portion 3. Leads 1a that are a plurality of external terminals
And a bonding wire 4 for connecting the pad (surface electrode) 2a of the semiconductor chip 2 and the lead 1a corresponding thereto.

The tab 1b for supporting the semiconductor chip 2
The chip supporting surface 1c is the main surface 2b of the semiconductor chip 2.
Larger, and therefore QFN5 of the first embodiment
Is a large tab type, but the size and planar shape of the tab 1b are not particularly limited.

Further, the tab 1b is supported by the suspension leads 1e at the four corners thereof, but the number of suspension leads 1e and the supporting points thereof are not particularly limited.

The leads 1a, the suspension leads 1e and the tabs 1b are made of a metal material such as copper and have a thickness of, for example, about 0.2 mm.

Further, as shown in FIG. 2, the semiconductor chip 2 is fixed to the chip supporting surface 1c of the tab 1b by a die bonding material such as silver paste.

The bonding wire 4 for connecting the pad 2a of the semiconductor chip 2 and the corresponding lead 1a is, for example, a gold wire.

Further, the sealing portion 3 is formed by resin sealing by a molding method, and the sealing resin (molding resin) used at that time is, for example, a thermosetting epoxy resin.

Further, although solder-plating for solder connection at the time of mounting on a mounting board or the like is formed on the connected surface 1g of each lead 1a exposed at the peripheral portion of the back surface 3a of the sealing portion 3, As an alternative to the solder plating, palladium (P
d) Plating or the like may be formed.

Next, the manufacturing method of the QFN 5 of the first embodiment will be described with reference to the manufacturing process flow chart shown in FIG.

First, a thin plate-shaped tab 1b on which the semiconductor chip 2 can be mounted, a suspension lead 1e that integrally supports the tab 1b and extends straight from the tab 1b toward the outside, and the periphery of the tab 1b. A lead frame 1 shown in FIG. 5 having a plurality of leads 1a arranged in the above is prepared (step S1).

Incidentally, in the lead frame 1, as shown in FIG. 6, the tab 1b is more than the suspension lead 1e.
Are arranged in the surface direction on the mounting side of. That is, it is the lead frame 1 that has been subjected to the tab lowering process. The tab lowering amount (T) at that time is the plate thickness of the lead frame 1 (for example,
The bending amount is such that the composition can be deformed by about 0.2 mm) or slightly less.

The tab lowering process is a process for surely exposing the back surface 1d of the tab 1b to the back surface 3a of the sealing portion 3 after the resin molding, as shown in FIG.

On the other hand, after the semiconductor chip 2 having the semiconductor integrated circuit formed on the main surface 2b shown in FIG. 2 is prepared, the semiconductor chip 2 is supplied and, as shown in FIG.
The die bonding shown in step S2 for mounting the semiconductor chip 2 on the tab 1b is performed.

Here, the chip supporting surface 1c of the tab 1b of the lead frame 1 and the back surface 2c of the semiconductor chip 2 are bonded together. That is, a die bond material (for example, silver paste) is attached to the chip supporting surface 1c of the tab 1b of the lead frame 1.
The semiconductor chip 2 is fixed (mounted) with the main surface 2b facing upward via.

Then, wire bonding is performed to connect the pad 2a of the semiconductor chip 2 and the corresponding lead 1a of the lead frame 1 with the wire 4 such as a gold wire (step S3).

After that, as shown in step S4, resin molding of the semiconductor chip 2 is performed by molding (here, transfer molding).

Here, the sealing portion 3 is formed so that the back surface 1d of the tab 1b and the connection surface 1g of each lead 1a are exposed on the back surface 3a of the sealing portion 3.

At this time, as shown in FIG. 7, the lead frame 1 having the tab lowering process is sandwiched between the upper mold 6 and the lower mold 7 for clamping and clamped, and in this state, the upper mold 6 is held. Molding is performed by filling the cavity 6a with a sealing resin.

Since the lead frame 1 is subjected to the tab lowering process, the tab 1b is lower than the tab 1b during clamping by the upper mold 6 and the lower mold 7.
The stress acts in the direction of being pressed against.

Therefore, during the filling of the sealing resin, the tab 1
b is firmly adhered to the lower mold 7, and as a result, the tab 1b
It is possible to reliably prevent the sealing resin from entering between the lower mold 7 and the lower mold 7.

After the filling of the sealing resin into the cavity 6a is completed, the sealing resin is cured and then the mold is opened to take out the lead frame 1.

After that, cutting (singulation) shown in step S5 is performed.

Here, each lead 1a and each suspension lead 1
e is cut and separated from the lead frame 1 to separate each package into individual pieces.

As a result, the QFN shown in step S6 is completed.

In the first embodiment, by assembling the QFN 5 using the lead frame 1 having the tab lowering process, the tab 1b can be surely exposed on the back surface 3a of the sealing portion 3.

At this time, in the molding step, since resin molding is performed without using a tape material such as a film tape or an adhesive tape, the tape material is not required, and the manufacturing cost of the QFN 5 can be reduced.

The assembly process of QFN5 is as follows.
Since only the lead frame 1 that has been subjected to the tab lowering process is used, the assembly can be performed using the conventional assembly method as it is, and the conventional manufacturing method can be used without requiring a special manufacturing method. Is.

Therefore, since there is no change in the size of each member of the QFN 5, it is possible to stably supply the material.

Next, a modification of the first embodiment will be described.

FIG. 9 shows a modified lead frame 1.
In the lead frame 1 used for assembling the QFN 5, tab lowering processing is performed as shown in FIG. 10, and the chip support surface 1c of the tab 1b and the surface of the suspension lead 1e connected thereto are the end portions of the suspension lead 1e. It is formed so as to be recessed and thinner than the surface of 1 h.

That is, as shown in FIG. 9 and FIG. 10, the tab 1 starts from the region inside the end 1h of the suspension lead 1e.
The region extending over the entire chip support surface 1c of b is the suspension lead 1e.
The recess 1f is recessed from the end 1h of the
Is thinner than the thickness of the end 1h of the suspension lead 1e.

Further, a tab lowering process is also applied.

The end portion 1h of the suspension lead 1e means a region from the end of the suspension lead 1e to a region having a length equivalent to the length of the lead 1a, and the suspension lead 1e is bent to lower the tab. The location where is performed is a thinned area inside the end 1h.

Further, the thickness of the thinned portion of the bottom of the recess 1f is, for example, the thickness of the end 1h of the suspension lead 1e.
If it is 0.2 mm, it is about half that, and the processing method for thinning is, for example, etching, but press processing such as coining other than the etching may be used for thinning.

In performing the tab lowering, by thinning the bending portion for lowering the tab of the suspension lead 1e, the composition deformation (bending process) for lowering the tab can be easily performed. That is, the lead frame 1 shown in FIG.
9 and the lead frame 1 shown in FIG. 9, the lead frame 1 shown in FIG. 9 has a thinner frame thickness at the bent portion for lowering the tab.
The composition can be easily modified.

Therefore, the lead frame 1 shown in FIG.
With the lead frame 1 shown in FIG. 9, the lead frame 1 shown in FIG. 9 requires a smaller amount of tab lowering (T> S at the tab lowering amounts shown in FIGS. 6 and 10).

As a result, FIG. 6 after wire bonding is performed.
In the structure shown in FIG. 10 and the structure shown in FIG. 10, respectively, the lead frame 1 shown in FIG. Peeling off and disconnection are unlikely to occur.

After the lead frame 1 shown in FIG. 9 is prepared, the semiconductor chip 2 is mounted on the tab 1b as shown in FIG. 10, and wire bonding is further performed.
Resin molding is performed using the upper mold 6 and the lower mold 7 for molding as shown in FIG.

After that, the resin is hardened and leads are cut (divided into individual pieces) to complete the QFN 5 as shown in FIG.

Although the lead frame 1 shown in FIG. 9 has a structure in which the chip mounting side is recessed to be thin, like the lead frame 1 of the modified example shown in FIG.
The back surface 1d side of the tab 1b may be recessed to be thin, or, as in the modification shown in FIG. 14, both the chip mounting side and the back surface side of the tab 1b may be recessed to be thin. .

Lead frame 1 shown in FIGS. 9 and 14.
Then, since at least the chip mounting side of the tab 1b is recessed, as shown in FIG.
The arrangement height of the semiconductor chip 2 can be set to a low position.

Thus, if the thickness of the semiconductor chip 2 is not changed and is considered as a reference, the height (thickness) of the QFN 5 can be lowered (thinned), while the height of the QFN 5 is not changed. Considering this as a reference, the height (thickness) of the semiconductor chip 2 can be increased (thickened).

That is, the thickness of the semiconductor chip 2 can be increased without changing the package height.

(Embodiment 2) FIG. 15 is a plan view showing an example of the structure of a semiconductor device (QFN) according to Embodiment 2 of the present invention through the sealing portion, and FIG. 16 is BB of FIG. FIG. 17 is a cross-sectional view showing the structure of a cross section taken along the line, FIG. 17 is a bottom view showing an example of the structure of the QFN shown in FIG. 15 through the sealing portion, and FIG. 18 is taken along the line CC of FIG. 19 and 20 are cross-sectional views showing the structure of the QFN of the modified example of the second embodiment of the present invention.

Q of the second embodiment shown in FIGS.
The FN8 has a tab exposure structure similar to the QFN5 of the first embodiment, but there is no tab lowering process, and the suspension lead 1 is used.
The surface opposite to the mounting surface of e, that is, the suspension lead 1e
The recess 1i as shown in FIGS. 18, 19 and 20 is formed on at least one of the surface (front surface) on the chip mounting side or the chip supporting surface 1c of the tab 1b.

That is, one or both of the chip support surface 1c of the tab 1b and the surface of the suspension lead 1e connected to this chip support surface 1c or both of them is formed thinner than the end portion 1h of the suspension lead 1e. Recess 1i
Are formed.

Therefore, in FIG. 18, the entire chip support surface 1c of the tab 1b and a part of the surface of the suspension lead 1e are recessed to form the recess 1
FIG. 19 shows that the entire chip support surface 1c of the tab 1b and the region inside the end 1h of the suspension lead 1e connected to the tab 1b are recessed to form a recess 1i. FIG. 20 shows a case where the recess 1i is formed in the region inside the end 1h of the suspension lead 1e.

These recesses 1i are formed by applying residual strain during the rolling process of the lead frame 1 to form a region where the surface of the suspension lead 1e including the tab 1b on the chip mounting side is thinned to form the tab 1b. The tab 1b and the suspension lead 1e region thereof are bent so that the tab 1b becomes convex in the surface direction on the mounting side, and the tab 1b is surely exposed on the back surface 3a of the sealing portion 3.

In the QFN 8 shown in FIGS. 19 and 20, the recess 1i formed in the inner region of the end 1h of the suspension lead 1e meshes with the sealing portion 3, and the recess 1i and the sealing portion 3 are connected to each other. Since the relationship of the joint surface of is uneven, it is possible to lengthen the infiltration route of moisture from the outside, and as a result,
The moisture resistance of QFN8 can be improved.

Therefore, for example, the QFN shown in FIG.
In the case of No. 8, by forming the recesses 1i formed in the suspension lead 1e by a plurality of finer recesses 1i, it is possible to further lengthen the water entry path, and thus it is possible to further improve the moisture resistance. .

Next, the strain during material processing (rolling) of a thin plate material of metal such as copper will be described.

In the case of a metal material such as a copper plate, the plate material still has distortion during material processing, and when only one side of the plate material is cut by half etching or the like, the distortion is unbalanced, resulting in the thickness of the plate material. Deformation such as warpage occurs in the direction. At that time, if one side of the plate material is thinned by cutting about 1/2 of the plate thickness, the plate material warps so as to be convex on the other surface side opposite to the scraped side of the plate material. It has been known.

Applying this to the lead frame 1,
For example, the tab 1b of the lead frame 1 or a part of the surface of the suspension lead 1e on the chip mounting side is formed and thinned by half etching or the like to reduce the thickness of the tab 1b.
Lead frame 1 so that b is convex on the back surface 1d side
Can be warped.

Therefore, in the QFN 8 of the second embodiment, by using this technique, the QFN of the tab exposed structure is used.
At N8, the tab 1b can be reliably exposed on the back surface 3a of the sealing portion 3.

That is, since the back surface 1d of the tab 1b can be brought into close contact with the lower mold 7 shown in FIG. 7 during the mold clamping in the molding step, a sealing resin is provided between the tab 1b and the lower mold 7. Can be prevented from entering, and as a result, the tab 1b can be surely exposed.

The method of assembling the QFN 8 of the second embodiment shown in FIGS. 18, 19 and 20 is as follows.
It is the same as the QFN 5 of the first embodiment and can be assembled according to the manufacturing process flow chart shown in FIG.

Therefore, in the second embodiment, the recess 1i is formed in a part of the surface of the tab 1b or the suspension lead 1e on the chip mounting side to make it thinner, so that the tab 1b can be clamped during the mold clamping in the molding process. The back surface 1d can be brought into close contact with the lower mold 7 to prevent the sealing resin from entering between the tab 1b and the lower mold 7. As a result, the back surface 1d of the tab 1b can be fixed to the back surface 3a of the sealing portion 3. It can be surely exposed.

Further, the QFN shown in FIG. 18 and FIG.
In FIG. 8, since the semiconductor chip 2 is arranged at a lower position as the tab 1b becomes thinner, the volume on the main surface of the semiconductor chip 2 is increased, and the sealing resin disposed on the main surface of the semiconductor chip 2 is increased. The amount also increases.

As a result, a force that pushes the semiconductor chip 2 toward the tab 1b (lower side) acts when the sealing resin is filled in the resin molding.

Therefore, when the resin is filled, the back surface 1d of the tab 1b can be brought into close contact with the lower mold 7 to prevent the sealing resin from entering between the tab 1b and the lower mold 7. 1b can be reliably exposed.

Further, in the QFN 8 shown in FIG. 19, since the tab 1b and the inner region of the end 1h of the suspension lead 1e connected to the tab 1b are thinned, the chip size of the semiconductor chip 2 mounted on the tab 1b is increased. can do.

Since the other effects of the second embodiment are the same as those described in the first embodiment, duplicate description thereof will be omitted.

Further, in the QFN 8 of the second embodiment, as shown in FIGS. 18, 19 and 20, the suspension lead 1 is used.
A back side recess 1j is formed on the mounting side surface of e. The back surface side recessed portion 1j is for preventing contact between the terminal on the substrate side corresponding to the lead 1a adjacent to the suspension lead 1e and the suspension lead 1e when the QFN 8 is mounted on the mounting substrate. The suspension lead 1e is embedded in the sealing portion 3 as much as possible to reduce the area of the suspension lead 1e exposed on the back surface 3a of the sealing portion 3.

As a result, the appearance quality of the QFN 8 can be improved.

However, the back surface side concave portion 1j does not necessarily have to be formed.

Although the invention made by the present inventor has been specifically described based on the embodiments of the invention, the invention is not limited to the embodiments of the invention, and does not depart from the scope of the invention. It goes without saying that various changes can be made with.

For example, the concave portion 1f described in the first embodiment.
The recess 1i described in the second embodiment may be provided in common.

That is, with the structure shown in FIG. 10, it is possible to have both the tab exposure effect due to the tab lowering and the tab exposure effect due to the residual stress of the material of the lead frame 1.

In the first and second embodiments, the tab 1
The case of using the large tab structure in which the chip supporting surface 1c of b is larger than the main surface 2b of the semiconductor chip 2 has been described, but it may be a QFN 5 having a small tab structure as shown in the modification of FIG.

[0091]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

By assembling the semiconductor device having the tab exposed structure using the lead frame subjected to the tab lowering process, the tab can be surely exposed, and a tape material such as a film tape or an adhesive tape is not used. Since the semiconductor device can be assembled in the same manner, the manufacturing cost of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a semiconductor device (QFN) according to a first embodiment of the present invention.
FIG. 3 is a plan view showing an example of the structure of FIG.

FIG. 2 is a cross-sectional view showing a structure of a cross section taken along line AA of FIG.

FIG. 3 is a bottom view showing the structure of the QFN shown in FIG. 1 through a sealing portion.

4 is a manufacturing process flow chart showing an example of an assembly procedure of the QFN shown in FIG. 1. FIG.

5 is a side view showing an example of the structure of a lead frame used for assembling the QFN shown in FIG. 1. FIG.

6 is a side view showing an example of a structure after die bonding in assembling the QFN shown in FIG.

7 is a partial cross-sectional view showing an example of a structure at the time of resin molding in assembling the QFN shown in FIG.

8 is a cross-sectional view showing an example of a structure after resin molding in assembling the QFN shown in FIG.

FIG. 9 is a side view showing an example of the structure of a lead frame used for assembling the QFN according to the modified example of the first embodiment of the present invention.

FIG. 10 is a side view showing an example of a structure after die bonding in assembling the QFN according to the modified example of the first embodiment of the present invention.

FIG. 11 is a partial cross-sectional view showing an example of a structure at the time of resin molding in assembling the QFN of the modified example of the first embodiment of the present invention.

FIG. 12 is a cross-sectional view showing an example of a structure after resin molding in assembling the QFN according to the modified example of the first embodiment of the present invention.

FIG. 13 is a side view showing the structure of the lead frame of the modification of the first embodiment of the present invention.

FIG. 14 is a side view showing a structure of a lead frame of a modified example of the first embodiment of the present invention.

FIG. 15 shows a semiconductor device (QF according to the second embodiment of the present invention.
It is a top view which shows an example of the structure of N) by seeing through a sealing part.

16 is a sectional view showing a structure of a section taken along line BB in FIG.

FIG. 17 is a bottom view showing an example of the structure of the QFN shown in FIG. 15 through the sealing portion.

18 is a cross-sectional view showing a structure of a cross section taken along line CC of FIG.

FIG. 19 is a cross-sectional view showing the structure of a QFN according to a modified example of the second embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the structure of a QFN according to a modified example of the second embodiment of the present invention.

FIG. 21 is a bottom view showing the structure of a modified QFN with respect to the QFN shown in FIG.

[Explanation of symbols]

1 lead frame 1a lead 1b tab 1c Chip support surface 1d Back side (opposite side) 1e Hanging lead 1f recess 1g Connected surface (part) 1h end 1i recess 1j Back side recess 2 semiconductor chips 2a Pad (surface electrode) 2b Main surface 2c back side 3 Sealing part 3a Back surface (mounting side surface) 4 wires 5 QFN (semiconductor device) 6 Upper mold 6a cavity 7 Lower mold 8 QFN (semiconductor device)

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Claims (5)

[Claims] 1. A semiconductor device in which a semiconductor chip is resin-sealed, wherein a sealing portion formed by resin-sealing the semiconductor chip, and a mounting of the sealing portion supporting the semiconductor chip. A tab exposed on the side surface, a suspension lead that is integral with the tab and extends outward from the tab, and a part of the suspension lead is disposed on the peripheral portion of the mounting side surface of the sealing portion. A plurality of leads, a surface electrode of the semiconductor chip and a wire connecting the leads corresponding thereto, and a recess that engages with the sealing portion is formed on the surface opposite to the mounting side surface of the suspension lead. A semiconductor device characterized by being formed. 2. A tab having a semiconductor chip mountable thereon, a suspension lead which is integral with the tab and extends outward from the tab, and a plurality of leads arranged around the tab. A step of preparing a lead frame in which tabs are arranged in a surface direction on the mounting side of the suspension leads; a step of mounting the semiconductor chip on the tabs of the lead frame; and a surface electrode of the semiconductor chip and corresponding thereto The step of connecting the lead with a wire, and forming the sealing portion such that the surface of the tab opposite to the chip supporting surface and a part of the lead are exposed to the surface of the mounting side of the sealing portion. And a step of sealing the semiconductor chip with a resin, and a step of separating the lead from the lead frame. 3. A semiconductor chip mountable tab, a suspension lead that is integral with the tab and extends outward from the tab, and a plurality of leads that are arranged around the tab. The tab is arranged in the surface direction on the mounting side of the suspension lead, and the chip support surface of the tab and the surface of the suspension lead connected to the tab are recessed from the end of the suspension lead and formed thinly. A step of preparing a frame; a step of mounting the semiconductor chip on the tab of the lead frame; a step of connecting a surface electrode of the semiconductor chip and the lead corresponding thereto by a wire; chip support of the tab A step of resin-sealing the semiconductor chip by forming the sealing portion so that a surface opposite to the surface and a part of the lead are exposed at a mounting-side surface of the sealing portion, The method of manufacturing a semiconductor device characterized by a step of separating the serial read from the lead frame. 4. A tab on which a semiconductor chip can be mounted, a suspension lead which is integral with the tab and extends outward from the tab, and a plurality of leads arranged around the tab, A step of preparing a lead frame in which any one of the chip support surface of the tab or the surface of the suspension lead connected to the chip support surface is recessed from the end portion of the suspension lead and thinly formed; and the tab of the lead frame. A step of mounting the semiconductor chip on, a step of connecting the surface electrode of the semiconductor chip and the lead corresponding thereto with a wire, and a surface of the tab opposite to the chip supporting surface and a part of the lead. A step of forming the sealing portion so as to be exposed at the mounting side surface of the sealing portion and resin-sealing the semiconductor chip; and separating the lead from the lead frame. The method of manufacturing a semiconductor device characterized by having a degree. 5. A tab having a semiconductor chip mountable thereon, a suspension lead that is integral with the tab and extends outward from the tab, and a plurality of leads arranged around the tab. A step of preparing a lead frame in which the chip supporting surface of the tab and the surface of the suspension lead connected to the tab are formed to be thinner than the end portion of the suspension lead; and the semiconductor chip is mounted on the tab of the lead frame. A step of connecting a surface electrode of the semiconductor chip and the lead corresponding thereto with a wire; And a step of resin-sealing the semiconductor chip by forming the sealing portion so as to be exposed on the surface, and a step of separating the lead from the lead frame. Method of manufacturing a conductor arrangement.