JP2927066B2 - Method for manufacturing resin-encapsulated semiconductor device - Google Patents
Method for manufacturing resin-encapsulated semiconductor deviceInfo
- Publication number
- JP2927066B2 JP2927066B2 JP20617091A JP20617091A JP2927066B2 JP 2927066 B2 JP2927066 B2 JP 2927066B2 JP 20617091 A JP20617091 A JP 20617091A JP 20617091 A JP20617091 A JP 20617091A JP 2927066 B2 JP2927066 B2 JP 2927066B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- resin
- back surface
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置
(以下、半導体装置という)に関し、特に半導体装置が
受ける熱ストレスによるモールド樹脂のクラックを防止
した半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device (hereinafter, referred to as a semiconductor device), and more particularly to a method of manufacturing a semiconductor device in which cracks in a mold resin due to thermal stress applied to the semiconductor device are prevented.
【0002】[0002]
【従来の技術】近年における電子機器の小型化に伴い、
これら電子機器に用いられる半導体装置では半導体チッ
プの高集積化による大チップ化が進む一方、パッケージ
の形状が小型化、薄型化され、DIPのみならずQFP
やSOPといった半導体装置が提案されている。従来の
この種の半導体装置の一例として、QFPを示す。図5
は一部破断平面図、図6は図5のB−B線断面図であ
る。この半導体装置は半導体チップ1をリードフレーム
2のダイパッド3の表面上に搭載し、この半導体チップ
1の電極パッド4と前記リードフレーム2のインナーリ
ード5とをボンディングワイヤ6でボンディングした
後、リードフレーム2のアウターリード8を残してモー
ルド樹脂7でモールディングした構成としている。2. Description of the Related Art With the recent miniaturization of electronic equipment,
In semiconductor devices used in these electronic devices, the size of packages has been reduced and thinned while the integration of semiconductor chips has been increasing, and the package size has been reduced.
Semiconductor devices such as SOPs and SOPs have been proposed. A QFP is shown as an example of this type of conventional semiconductor device. FIG.
6 is a partially cutaway plan view, and FIG. 6 is a sectional view taken along line BB of FIG. In this semiconductor device, a semiconductor chip 1 is mounted on a surface of a die pad 3 of a lead frame 2, and an electrode pad 4 of the semiconductor chip 1 and an inner lead 5 of the lead frame 2 are bonded by bonding wires 6. The second outer lead 8 is left and molded with the molding resin 7.
【0003】この半導体装置は、一般にはリードフレー
ムに42アロイ(Fe−Ni42)の合金が使用されて
おり、半導体チップはダイパッドにAgペーストの接着
剤でり固定される。又、ボンディングワイヤとしては、
30μm程度のAu線が用いられ、更にモールド樹脂に
はエポキシ樹脂が用いられる。尚、アウターリードは下
方に曲げ形成している。In this semiconductor device, an alloy of 42 alloy (Fe-Ni42) is generally used for a lead frame, and a semiconductor chip is fixed to a die pad with an Ag paste adhesive. Also, as a bonding wire,
An Au wire of about 30 μm is used, and an epoxy resin is used as a mold resin. The outer leads are bent downward.
【0004】[0004]
【発明が解決しようとする課題】上述した従来の半導体
装置では、リードフレーム2に用いられるニッケル系の
合金と、モールド樹脂7に用いられる熱液化性エポキシ
樹脂の熱膨張係数が違うので密着性が良好ではない。こ
のため熱ストレスを受けるとリードフレーム2とモール
ド樹脂7との間に剥離が生じ易く、この剥離は特に半導
体装置の内部で特に大きな平面積を必要とするダイパッ
ド3の裏面で顕著となる。このような剥離が生じると、
この剥離した部分に水分が吸湿され、この状態でプリン
ト基板上に半導体装置を実装する際のリフロー半田付け
の温度約 240°程度の熱が急激に半導体装置に加えられ
ると、吸湿した水分が気化膨張して樹脂への圧力が急激
に増加され、ダイパッド3の周辺に大きな応力を発生す
る。この応力によりダイパッド3の裏面側のモールド樹
脂7にクラックが発生することになる。In the above-mentioned conventional semiconductor device, the nickel-based alloy used for the lead frame 2 and the thermo-liquefiable epoxy resin used for the molding resin 7 have different coefficients of thermal expansion, so that the adhesion is poor. Not good. For this reason, when subjected to thermal stress, peeling tends to occur between the lead frame 2 and the mold resin 7, and this peeling becomes remarkable especially on the back surface of the die pad 3 requiring a particularly large flat area inside the semiconductor device. When such peeling occurs,
Moisture is absorbed by the peeled portion, and in this state, when the heat of about 240 ° of reflow soldering when the semiconductor device is mounted on the printed circuit board is suddenly applied to the semiconductor device, the absorbed moisture is vaporized. When expanded, the pressure on the resin is rapidly increased, and a large stress is generated around the die pad 3. This stress causes cracks in the mold resin 7 on the back surface side of the die pad 3.
【0005】このことにより、半導体装置の耐湿性はさ
らに劣化し、半導体チップ1は作動時に熱を発生するこ
とから作動毎に熱ストレスが繰り返しリードフレーム2
とモールド樹脂7に加わることになり、モールド樹脂7
のクラックが更に進み半導体装置が劣化してしまうとい
う問題がある。このモールド樹脂7のクラックはダイパ
ッド3の面積が大きいほど、またダイパッド3の裏面の
モールド樹脂7が薄いほど発生しやすい。このためモー
ルド樹脂7内の水分をプリベークで減少させても大きな
チップサイズの半導体チップを樹脂厚 1.0mm程度の薄型
のパッケージにすることには問題があった。本発明の目
的は、熱ストレスによるリードフレームとモールド樹脂
との剥離を防いで信頼性を改善した半導体装置の製造方
法を提供することにある。As a result, the moisture resistance of the semiconductor device is further degraded, and the semiconductor chip 1 generates heat during operation.
And the mold resin 7.
There is a problem that the cracks are further advanced and the semiconductor device is deteriorated. The cracks in the mold resin 7 are more likely to occur as the area of the die pad 3 increases and the thickness of the mold resin 7 on the back surface of the die pad 3 decreases. Therefore, even if the moisture in the mold resin 7 is reduced by pre-baking, there is a problem in forming a semiconductor chip having a large chip size into a thin package having a resin thickness of about 1.0 mm. An object of the present invention is to provide a method of manufacturing a semiconductor device having improved reliability by preventing separation of a lead frame and a mold resin due to thermal stress.
Is to provide a law .
【0006】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップを搭載するリードフレームのダイパッドの
端部を外方向に延長する工程と、前記端部を部分エッチ
ングしてこの端部の厚さのみ薄くする工程と、前記端部
をダイパッドの裏面側に向けて曲げ形成する工程を含ん
でいる。例えば、ダイパッドの四周囲に端部を形成し、
この端部を円弧状に湾曲する工程を含んでいる。 According to the present invention, there is provided a semiconductor device comprising:
Extending an end of a die pad of a lead frame for mounting a semiconductor chip in an outward direction; and partially etching the end.
And a step of bending the end toward the back side of the die pad.
In. For example, forming edges around the four sides of the die pad ,
The method includes a step of bending the end portion into an arc shape .
【0007】[0007]
【作用】本発明によれば、半導体装置のダイパッド裏面
側のモールド樹脂はダイパッドの端部を曲げ形成した部
分の内側でダイパッド裏面に押さえ付けられて保持さ
れ、熱膨張が拘束されてダイパッド裏面との剥離が防止
される。According to the present invention, the mold resin on the back surface of the die pad of the semiconductor device is held by being pressed against the back surface of the die pad inside the portion formed by bending the end of the die pad, the thermal expansion is restrained, and Is prevented from peeling off.
【0008】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図2は本発明の半導体装置の一実施例の一部破断平
面図であり、図1は図2のA−A線断面図である。この
半導体装置は半導体チップ1をリードフレーム2のダイ
パッド3の上面に搭載した上で、半導体チップ1の電極
パッド4とリードフレーム2のインナーリード5をボン
ディングワイヤ6で電気接続し、これを樹脂成形金型に
入れてモールド樹脂7で樹脂封止する。又、リードフレ
ーム2のアウターリード8を図外のプリント基板上に実
装し易い形に曲げ加工している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 2 is a partially cutaway plan view of one embodiment of the semiconductor device of the present invention, and FIG. 1 is a sectional view taken along line AA of FIG. In this semiconductor device, the semiconductor chip 1 is mounted on the upper surface of the die pad 3 of the lead frame 2, and the electrode pads 4 of the semiconductor chip 1 and the inner leads 5 of the lead frame 2 are electrically connected by bonding wires 6, and this is resin-molded. It is placed in a mold and sealed with a mold resin 7. The outer leads 8 of the lead frame 2 are bent so as to be easily mounted on a printed circuit board (not shown).
【0009】前記リードフレーム2のダイパッド3は、
図3に裏面側から見た斜視図を示すように、略正方形に
形成され、その四周囲の各辺の端部9を外側に向けて突
出するように延長しており、かつこの端部9をダイパッ
ド3の裏面側に向けて円弧状に湾曲させている。尚、こ
の実施例では、リードフレーム2は42合金を用い、ダ
イパッド3は半導体チップを搭載固定するための強度を
保持させるために厚さを 150μmとしているが、端部9
は強度的には問題がないことから加工しやすいように部
分エッチングしダイパッド3の略2/3 程度の厚さにして
ある。このリードフレーム2はパターンをエッチングま
たはプレスで作製したあとダイパッド3の端部9を前述
の加工をすることにより作製する。The die pad 3 of the lead frame 2
As shown in the perspective view of FIG. 3 as viewed from the back side, it is formed in a substantially square shape, and the end 9 of each side around the four sides is extended so as to protrude outward. Are curved in an arc toward the back surface of the die pad 3. In this embodiment, the lead frame 2 is made of 42 alloy, and the die pad 3 has a thickness of 150 μm to maintain the strength for mounting and fixing the semiconductor chip.
Since there is no problem in strength, the die pad 3 is partially etched to a thickness of about 2/3 to facilitate processing. The lead frame 2 is manufactured by etching or pressing a pattern and then processing the end 9 of the die pad 3 by the above-described processing.
【0010】このように形成した半導体装置では、ダイ
パッド3の裏面に密着するモールド樹脂7はダイパッド
3の円弧状に湾曲された端部9の内側で保持されること
になり、ダイパッド3の裏面に押さえ付けられる状態と
される。したがって、プリント基板上にこの半導体装置
を赤外線リフロー等により半田付け実装する際に、約23
0 ℃の熱ストレスをうけても、ダイパッド3の裏面側の
樹脂の熱膨張を端部9の内側で拘束しているため、ダイ
パッド3の裏面においてモールド樹脂7が全面にわたっ
て剥離することが防止される。したがって、ダイパッド
裏面とモールド樹脂との界面に水分が吸湿されることが
なく、熱ストレスによる気化膨張によるモールド樹脂7
への圧力もなくなるので、リフロー半田付けの際の樹脂
クラックの発生を防止することが可能となり半導体装置
の劣化を防止することができる。In the semiconductor device formed in this manner, the mold resin 7 that is in close contact with the back surface of the die pad 3 is held inside the arc-shaped curved end portion 9 of the die pad 3, It is in a state where it can be held down. Therefore, when this semiconductor device is soldered and mounted on a printed circuit board by infrared reflow or the like, about 23
Even when subjected to a thermal stress of 0 ° C., since the thermal expansion of the resin on the back surface side of the die pad 3 is restrained inside the end portion 9, the mold resin 7 is prevented from peeling over the entire back surface of the die pad 3. You. Therefore, moisture is not absorbed at the interface between the back surface of the die pad and the mold resin, and the mold resin 7 due to vaporization and expansion due to thermal stress is prevented.
Therefore, the occurrence of resin cracks during reflow soldering can be prevented, and deterioration of the semiconductor device can be prevented.
【0011】さらに、この半導体装置では、半導体チッ
プ1のチップサイズが大きくなってダイパッド3の面積
が大きくなっても、又、ダイパッド3の裏面側のモール
ド樹脂7の厚みを薄くしてもダイパッド裏面と樹脂との
剥離が防止されることから水分の吸湿などがなく、従来
より大きなチップサイズの半導体チップを樹脂の厚みの
薄い(TSOPで1mm厚)パッケージで形成した半導体
装置を得ることが可能となる。Further, in this semiconductor device, even if the chip size of the semiconductor chip 1 is increased and the area of the die pad 3 is increased, or if the thickness of the mold resin 7 on the back surface side of the die pad 3 is reduced, the die pad back surface is not damaged. A semiconductor device in which a semiconductor chip having a larger chip size than a conventional semiconductor chip is formed in a thin resin package (1 mm thick in TSOP) without the absorption of moisture and the like is prevented because separation of the resin from the resin is prevented. Become.
【0012】次に本発明の第2実施例を図4に示す。図
4は図3と同様にダイパッドを裏面側から見た斜視図で
ある。この実施例では、ダイパッド3の四周囲に設ける
端部9Aを辺方向に複数個、ここでは2個に分割形成し
た上で、各端部9Aをダイパッド3の裏面側に向けて円
弧状に湾曲形成したものである。このように構成する
と、各端部9Aはダイパッド3の裏面側のモールド樹脂
をダイパッド裏面に押さえ付けるように保持し、ダイパ
ッド3の裏面からモールド樹脂7が剥離されることを防
止できるとともに、モールディングに際しては分割され
た各端部9Aの間隙からモールド樹脂をダイパッド3の
裏面側に流入し易くすることができ、ダイパッドの裏面
側にボイド(空気溜まり)が生じることはない。ここ
で、前記各実施例ではQFP型の半導体装置に本発明を
適用しているが、本発明はこれに限定されずにSOPや
PLCCの半導体装置についても適用することができ
る。Next, a second embodiment of the present invention is shown in FIG. FIG. 4 is a perspective view of the die pad as viewed from the back side, similarly to FIG. In this embodiment, a plurality of end portions 9A provided around the four sides of the die pad 3 are formed in the side direction, here, divided into two, and each end portion 9A is curved in an arc shape toward the back surface side of the die pad 3. It is formed. With this configuration, each end 9A holds the mold resin on the back surface of the die pad 3 so as to press it against the back surface of the die pad. The mold resin can easily flow into the back surface of the die pad 3 from the gap between the divided end portions 9A, and no void (air pool) is generated on the back surface of the die pad. Here, in each of the above embodiments, the present invention is applied to a QFP type semiconductor device. However, the present invention is not limited to this and can be applied to an SOP or PLCC semiconductor device.
【0013】[0013]
【発明の効果】以上説明したように本発明は、半導体チ
ップを搭載するダイパッドの端部を延長する工程と、前
記端部を部分エッチングしてこの端部の厚さのみ薄くす
る工程と、前記端部をダイパッドの裏面側に曲げ形成す
る工程を含んでいるので、製造される半導体装置は、ダ
イパッドの裏面とモールド樹脂との密着性を改善し、熱
ストレスによる樹脂の剥離を防ぐことができる。これに
より、プリント基板上へ半導体装置を半田付け実装する
際等の急激な熱ストレスからモールド樹脂のクラック発
生が防止でき、半導体装置の信頼性を向上することがで
きる効果がある。また、本発明では、部分エッチングに
より端部を薄くして曲げ形成しているため、端部を湾曲
する加工を容易に行うことができる。 As described above, according to the present invention, there are provided a step of extending an end of a die pad on which a semiconductor chip is mounted ;
Partially etch the end to reduce the thickness of this end only
And forming the end portion on the back side of the die pad, so that the manufactured semiconductor device improves the adhesion between the back surface of the die pad and the mold resin, and peels off the resin due to thermal stress. Can be prevented. Thus, cracks in the mold resin can be prevented from occurring due to rapid thermal stress when the semiconductor device is soldered and mounted on a printed circuit board, and the reliability of the semiconductor device can be improved. In the present invention, the partial etching
Since the end is thinner and bent, the end is curved
Can be easily performed.
【図1】本発明の半導体装置の第1実施例を示し、図2
のA−A線断面図である。FIG. 1 shows a first embodiment of a semiconductor device of the present invention, and FIG.
3 is a sectional view taken along line AA of FIG.
【図2】本発明の半導体装置の第1実施例の一部破断平
面図である。FIG. 2 is a partially broken plan view of a first embodiment of the semiconductor device of the present invention.
【図3】本発明のリードフレームのダイパッドを裏面側
から見た斜視図である。FIG. 3 is a perspective view of the die pad of the lead frame of the present invention as viewed from the back surface side.
【図4】本発明の第2実施例におけるダイパッドを裏面
側から見た斜視図である。FIG. 4 is a perspective view of a die pad according to a second embodiment of the present invention as viewed from the back surface side.
【図5】従来の半導体装置の一例の一部破断平面図であ
る。FIG. 5 is a partially broken plan view of an example of a conventional semiconductor device.
【図6】図5のB−B線断面図である。FIG. 6 is a sectional view taken along line BB of FIG. 5;
1 半導体チップ 2 リードフレーム 3 ダイパッド 4 電極パッド 5 インナーリード 6 ボンディングワイヤ 7 モールド樹脂 8 アウターリード 9,9A 端部 Reference Signs List 1 semiconductor chip 2 lead frame 3 die pad 4 electrode pad 5 inner lead 6 bonding wire 7 molding resin 8 outer lead 9, 9A end
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭64−57651(JP,A) 特開 平2−133951(JP,A) 特開 平2−174149(JP,A) 特開 平1−181450(JP,A) 実開 昭62−5644(JP,U) 実開 昭64−341(JP,U) 実願 昭63−11433号(実開 平1− 116461号)の願書に添付した明細書及び 図面の内容を撮影したマイクロフィルム (JP,U) (58)調査した分野(Int.Cl.6,DB名) H01L 21/56 H01L 23/28 - 23/30 H01L 23/50 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-57651 (JP, A) JP-A-2-133951 (JP, A) JP-A-2-174149 (JP, A) JP-A-1- 181450 (JP, A) Japanese Utility Model Application Sho 62-5644 (JP, U) Japanese Utility Model Application No. 64-341 (JP, U) Japanese Utility Application No. 63-11433 (Japanese Utility Model Application No. 1-1116461) Microfilms of documents and drawings (JP, U) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/56 H01L 23/28-23/30 H01L 23/50
Claims (2)
半導体チップを搭載し、少なくとも前記ダイパッドと半
導体チップとを樹脂封止してなる樹脂封止型半導体装置
において、前記ダイパッドの端部を外方向に延長する工
程と、前記端部を部分エッチングしてこの端部の厚さの
み薄くする工程と、前記端部をダイパッドの裏面側に向
けて曲げ形成する工程を含むことを特徴とする樹脂封止
型半導体装置の製造方法。1. A resin-sealed semiconductor device having a semiconductor chip mounted on a surface of a die pad of a lead frame and resin-sealing at least the die pad and the semiconductor chip, wherein an end of the die pad is directed outward. Work to extend
And partially etching the end to reduce the thickness of the end.
A method of manufacturing a resin-encapsulated semiconductor device , comprising: a step of thinning ; and a step of bending and forming the end portion toward a back surface of a die pad.
し、かつこの端部を円弧状に曲げ形成する工程を含む請
求項1に記載の樹脂封止型半導体装置の製造方法。2. The end is formed around four sides of a die pad.
The method for manufacturing a resin-encapsulated semiconductor device according to claim 1 , further comprising a step of forming the end portion into an arc shape.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20617091A JP2927066B2 (en) | 1991-07-24 | 1991-07-24 | Method for manufacturing resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20617091A JP2927066B2 (en) | 1991-07-24 | 1991-07-24 | Method for manufacturing resin-encapsulated semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0529493A JPH0529493A (en) | 1993-02-05 |
JP2927066B2 true JP2927066B2 (en) | 1999-07-28 |
Family
ID=16518970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20617091A Expired - Lifetime JP2927066B2 (en) | 1991-07-24 | 1991-07-24 | Method for manufacturing resin-encapsulated semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2927066B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6101101A (en) * | 1998-05-28 | 2000-08-08 | Sampo Semiconductor Corporation | Universal leadframe for semiconductor devices |
-
1991
- 1991-07-24 JP JP20617091A patent/JP2927066B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0529493A (en) | 1993-02-05 |
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