JP3145892B2 - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JP3145892B2 JP3145892B2 JP6812495A JP6812495A JP3145892B2 JP 3145892 B2 JP3145892 B2 JP 3145892B2 JP 6812495 A JP6812495 A JP 6812495A JP 6812495 A JP6812495 A JP 6812495A JP 3145892 B2 JP3145892 B2 JP 3145892B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- wiring
- forming surface
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プリント基板にボール
状の外部端子を設けた樹脂封止型半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having a ball-shaped external terminal provided on a printed circuit board.
【０００２】[0002]
【従来の技術】図３（ａ）は従来のプリント基板にボー
ル状の外部端子を設けた樹脂封止型半導体装置（ＢＡＬ
Ｌ ＧＲＩＤ ＡＲＲＡＹ、以下「ＢＧＡ」とする。）
の表面図、同（ｂ）は同ＢＧＡの断面図、同（ｃ）は同
ＢＧＡの裏面図を示し、図４は図３（ｂ）の一部拡大図
である。2. Description of the Related Art FIG. 3A shows a conventional resin-encapsulated semiconductor device (BAL) in which ball-shaped external terminals are provided on a printed circuit board.
L GRID ARRAY, hereinafter referred to as “BGA”. )
(B) is a cross-sectional view of the BGA, and (c) is a cross-sectional view of the same .
FIG. 4 shows a rear view of the BGA , and FIG. 4 is a partially enlarged view of FIG.
【０００３】尚、図３及び図４において、１は半導体チ
ップ、２はプリント基板、３は半導体チップ表面及び金
又はアルミニウムを主成分とした極細のワイヤー５を保
護する保護用樹脂、４は鉛、錫等の合金によるボール状
電極、６は半導体チップとプリント基板とを接合する接
着剤、８はスルーホールを示す。但し、ボール状電極４
及びワイヤー５はこれらに限定されるものではない。In FIGS. 3 and 4, reference numeral 1 denotes a semiconductor chip, 2 denotes a printed board, 3 denotes a protective resin for protecting the surface of the semiconductor chip and a fine wire 5 mainly composed of gold or aluminum, and 4 denotes lead. , A ball-shaped electrode made of an alloy of tin or the like, 6 denotes an adhesive for joining the semiconductor chip and the printed board, and 8 denotes a through hole. However, the ball-shaped electrode 4
The wire 5 is not limited to these.
【０００４】従来のＢＧＡは、図３及び図４に示すよう
に、半導体チップ１の回路形成面の外周部に形成された
電極とプリント基板２に形成された配線とをワイヤーに
てボンディンク化、プリント基板２の半導体チップ１と
接合された面と反対面において、プリント基板２に形成
された配線と電気的に接続されたボール状電極を形成す
る。また、プリント基板２に設けられたスルーホール８
にて、プリント基板の両面の導通を確保している。In a conventional BGA, as shown in FIGS. 3 and 4, an electrode formed on an outer peripheral portion of a circuit forming surface of a semiconductor chip 1 and a wiring formed on a printed circuit board 2 are formed into wires.
Bo Te Ndinku reduction in the surface opposite to the semiconductor chip 1 and bonded to the surface of the printed circuit board 2, a wiring electrically connected to the ball-shaped electrode formed on the printed circuit board 2. Further, through holes 8 provided in printed circuit board 2 are provided.
Thus, conduction between both sides of the printed circuit board is ensured.
【０００５】[0005]
【発明が解決しようとする課題】しかし、上述の従来技
術においては、比較的入出力信号数の少ない半導体装置
において、半導体チップの電極から全ての電極とも外周
方向にワイヤーにてプリント基板と電気的接続する際、
図４に示すように、ワイヤー５が半導体チップ１に接触
し、電気的短絡が生じないように、ループを形成する必
要があった。そのため、ループが形成されたワイヤー５
を封止するため樹脂封止型半導体装置の薄型化に制限が
あった。However, in the above-mentioned prior art, in a semiconductor device having a relatively small number of input / output signals, all the electrodes from the electrodes of the semiconductor chip are electrically connected to the printed circuit board by wires in the outer peripheral direction. When connecting
As shown in FIG. 4, it was necessary to form a loop so that the wire 5 did not contact the semiconductor chip 1 and an electrical short circuit did not occur. Therefore, the looped wire 5
Therefore, there is a limitation in reducing the thickness of the resin-encapsulated semiconductor device.
【０００６】また、プリント基板２の両面を電気的に接
続するためのスルーホール８を形成する領域を確保する
必要がある。Further, it is necessary to secure an area for forming a through hole 8 for electrically connecting both sides of the printed circuit board 2.
【０００７】本発明は、スルーホールの形成が必要な
い、従来より薄型化が可能な樹脂封止型半導体装置を提
供することを目的とするものである。An object of the present invention is to provide a resin-encapsulated semiconductor device which does not require the formation of through holes and can be made thinner than before.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に、本発明の樹脂封止型半導体装置は、外周部に電極が
形成された半導体チップの回路形成面と該半導体チップ
より小さいプリント基板の配線形成面の裏面とが、上記
半導体チップに形成された電極が露出するように接合さ
れ、且つ、上記半導体チップの外周部に形成された電極
と上記プリント基板に形成された配線とが、上記半導体
チップ側から上記プリント基板側にボンディングが行わ
れたワイヤーにより電気的に接続され、且つ、上記プリ
ント基板の配線形成面に該配線と電気的に接続されたボ
ール状の電極を設けたことを特徴とするものである。ま
た、本発明の樹脂封止型半導体装置は、外周部に電極が
形成された半導体チップの回路形成面と該半導体チップ
より面積の小さいプリント基板の配線形成面の裏面と
が、上記半導体チップに形成された電極が露出するよう
に接合され、且つ、上記半導体チップの外周部に形成さ
れた電極と上記プリント基板に形成された配線とがボン
ディングにより電気的に接続され、且つ、上記プリント
基板の配線形成面に該配線と電気的に接続されたボール
状の電極を設けた樹脂封止型半導体装置であって、上記
半導体チップの回路形成面及び上記ボンディングに用い
られるワイヤーを保護する保護材としてエポキシ樹脂を
用い、且つ、プリント基板の、ボール状電極が形成され
る領域及びワイヤーとの接続領域以外の配線形成面を保
護する保護材としてフッ素系樹脂、又はシリコーン系樹
脂、又はフッ素系樹脂又はシリコーン系樹脂を含むエポ
キシ樹脂を用いることを特徴とするものである。さら
に、本発明の樹脂封止型半導体装置は、外周部に電極が
形成された半導体チップの回路形成面と該半導体チップ
より面積の小さいプリント基板の配線形成面の裏面と
が、熱可塑性の接着剤により、上記半導体チップに形成
された電極が露出するように接合され、且つ、上記半導
体チップの外周部に形成された電極と上記プリント基板
に形成された配線とがボンディングにより電気的に接続
され、且つ、上記プリント基板の配線形成面に該配線と
電気的に接続されたボール状の電極を設けたことを特徴
とするものである。また、本発明の樹脂封止型半導体装
置は、上記半導体チップの回路形成面及び上記ボンディ
ングに用いられるワイヤーを保護する保護材としてエポ
キシ樹脂を用い、且つ、プリント基板の、ボール状電極
が形成される領域及びワイヤーとの接続領域以外の配線
形成面を保護する保護材としてフッ素系樹脂、又はシリ
コーン系樹脂、又はフッ素系樹脂又はシリコーン系樹脂
を含むエポキシ樹脂を用いることを特徴とするものであ
る。さらに、本発明の樹脂封止型半導体装置は、上記半
導体チップの外周部に形成された電極と上記プリント基
板に形成された配線 とが、上記半導体チップ側から上
記プリント基板にボンディングが行われたワイヤーによ
り電気的に接続されたことを特徴とするものである。[Means for Solving the Problems] In order to solve the above-mentioned problems
In the resin-encapsulated semiconductor device of the present invention, the circuit forming surface of the semiconductor chip having electrodes formed on the outer periphery and the back surface of the wiring forming surface of the printed circuit board smaller than the semiconductor chip are formed on the semiconductor chip. The electrodes formed on the outer peripheral part of the semiconductor chip and the wiring formed on the printed board were bonded from the semiconductor chip side to the printed board side. A ball-shaped electrode which is electrically connected by a wire and is electrically connected to the wiring is provided on the wiring forming surface of the printed circuit board. Further, in the resin-encapsulated semiconductor device of the present invention, the circuit-formed surface of the semiconductor chip having electrodes formed on the outer peripheral portion and the back surface of the wiring-formed surface of the printed circuit board having a smaller area than the semiconductor chip are formed. Bonding the electrodes formed on the semiconductor chip to be exposed, and electrically connecting the electrodes formed on the outer peripheral portion of the semiconductor chip and the wiring formed on the printed board by bonding; and A resin-encapsulated semiconductor device provided with a ball-shaped electrode electrically connected to the wiring on a wiring forming surface of the printed board, wherein a wire used for the circuit forming surface of the semiconductor chip and the bonding is provided. Protective material that uses epoxy resin as a protective material to protect, and protects the wiring-formed surface of the printed circuit board other than the area where the ball-shaped electrodes are formed and the connection area with the wire And it is characterized in that an epoxy resin containing a fluorine-based resin, or silicone resin, or fluorine resin or silicone resin is. Further
In addition, the resin-encapsulated semiconductor device of the present invention is characterized in that the circuit forming surface of a semiconductor chip having electrodes formed on the outer peripheral portion and the back surface of a wiring forming surface of a printed circuit board having a smaller area than the semiconductor chip have thermoplastic adhesive. The electrodes are joined so that the electrodes formed on the semiconductor chip are exposed, and the electrodes formed on the outer peripheral portion of the semiconductor chip and the wires formed on the printed board are electrically connected by bonding. and and is characterized in that a wiring electrically connected to the ball-shaped electrodes on the wiring formation surface of the printed circuit board. Further , the resin-encapsulated semiconductor device of the present invention uses an epoxy resin as a protective material for protecting a circuit forming surface of the semiconductor chip and a wire used for the bonding, and has a ball-shaped electrode formed on a printed circuit board. and it is characterized in the use of fluorine-based resin, or silicone resin, or fluorine resin or epoxy resin containing a silicone resin as a protective material for protecting the that region and the wiring formation surface other than the connection region of the wire . Further, in the resin-encapsulated semiconductor device of the present invention, the electrodes formed on the outer peripheral portion of the semiconductor chip and the wires formed on the printed board are bonded to the printed board from the semiconductor chip side. it is characterized in that which is electrically connected by a wire.
【０００９】[0009]
【００１０】[0010]
【００１１】[0011]
【作用】本発明によると、ワイヤーはループ高さが従来
より低くても、半導体チップのエッジではなく、絶縁材
料で形成されたプリント基板のエッジと接触することに
なるため、ワイヤーのループを従来より低くすることが
でき、また、プリント基板の厚さ又はワイヤーを保護す
る保護用樹脂の厚さの内、薄いほうの厚さ分だけ従来よ
り薄型にすることができる。 According to the present invention, even if the wire has a lower loop height than the conventional one, the wire will not contact the edge of the semiconductor chip but the edge of the printed circuit board made of an insulating material. The thickness can be made lower, and the thickness can be made thinner by the thinner of the thickness of the printed circuit board or the thickness of the protective resin for protecting the wires.
【００１２】また、本発明によると、半導体チップ表面
とワイヤーとの保護膜材料としてのエポキシ樹脂と、プ
リント基板のワイヤーボンディング部及びボール状電極
形成部以外の配線形成面の保護膜材料としてのフッ素系
樹脂、又はシリコーン系樹脂、又はフッ素系樹脂又はシ
リコーン系樹脂を含むエポキシ樹脂とは互いに撥水性を
有するので、プリント基板に形成されたボール状電極が
設けられる領域及びワイヤーとプリント基板に形成され
た配線との接続領域に、ワイヤー及び半導体チップ表面
の保護用樹脂が流れ込むことを防ぐことができる。Further , according to the present invention, an epoxy resin is used as a protective film material for a surface of a semiconductor chip and a wire, and a fluorine is used as a protective film material for a wiring forming surface other than a wire bonding portion and a ball-shaped electrode forming portion of a printed circuit board. since system resin, or water-repellent to each other with an epoxy resin containing a silicone resin, or fluorine resin or silicone resin, formed on the region and wires and printed circuit board in which the ball-shaped electrode formed on the printed circuit board is provided It is possible to prevent the wire and the resin for protecting the surface of the semiconductor chip from flowing into the connection region with the formed wiring.
【００１３】さらに、本発明によると、半導体チップ上
にプリント基板を貼り付けた後、ワイヤーを接続する際
に不良が生じた場合、熱を加えることによって、半導体
チップからプリント基板を剥がすことができ、プリント
基板のみを取り替えることができる。 Further, according to the present invention, if a failure occurs when connecting a wire after attaching a printed board to a semiconductor chip, the printed board can be peeled from the semiconductor chip by applying heat. Only the printed circuit board can be replaced.
【００１４】[0014]
【実施例】以下、一実施例に基づいて本発明について詳
細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on an embodiment.
【００１５】図１（ａ）は本発明の一実施例のプリント
基板にボール状の外部端子を設けた樹脂封止型半導体装
置の表面図、同（ｂ）は同断面図、図２は図１（ｂ）の
一部拡大図である。尚、図１におけるＡ部は保護用樹脂
３を剥がした状態を示している。FIG. 1A is a resin-sealed semiconductor device having a ball-shaped external terminal provided on a printed circuit board according to an embodiment of the present invention.
Surface view of the location, the (b) is ditto view, FIG. 2 is a partially enlarged view of FIG. 1 (b). In addition, part A in FIG. 1 shows a state where the protective resin 3 is peeled off.
【００１６】図１及び図２において、１は半導体チッ
プ、２はプリント基板、３は半導体チップ表面及び金又
はアルミニウムを主成分とした極細のワイヤー５を保護
する保護用樹脂、４は鉛、錫等の合金によるボール状電
極、６は半導体チップとプリント基板とを接合する接着
剤、７はプリント基板２に形成された配線を保護する保
護用樹脂を示す。尚、ボール状電極４及びワイヤー５は
これらに限定されるものではない。1 and 2, reference numeral 1 denotes a semiconductor chip, 2 denotes a printed board, 3 denotes a protective resin for protecting the surface of the semiconductor chip and a fine wire 5 mainly composed of gold or aluminum, and 4 denotes lead and tin. A ball-shaped electrode made of an alloy such as an alloy; 6, an adhesive for joining the semiconductor chip to the printed board; and 7, a protective resin for protecting the wiring formed on the printed board 2. The ball-shaped electrode 4 and the wire 5 are not limited to these.
【００１７】本発明は、図１及び図２に示すように、半
導体チップ１の面積はプリント基板２の面積より大き
く、且つ、半導体チップ１の回路形成面とプリント基板
２の配線形成面と反対面とを接着剤６で接合し、且つ、
半導体チップ１の外周部に設けられた外部電極とプリン
ト基板２に形成された配線とをワイヤー５で電気的に接
続し、且つ、プリント基板２に形成された配線と電気的
に接続されたボール状電極４を設けたことを特徴とする
ものである。According to the present invention, as shown in FIGS. 1 and 2, the area of the semiconductor chip 1 is larger than the area of the printed circuit board 2 and opposite to the circuit forming surface of the semiconductor chip 1 and the wiring forming surface of the printed circuit board 2. Surface and an adhesive 6 and,
External electrodes provided on the outer peripheral portion of the semiconductor chip 1 are electrically connected to wires formed on the printed board 2 by wires 5, and balls are electrically connected to the wires formed on the printed board 2. It is characterized in that the shape electrode 4 is provided.
【００１８】以下に、本発明の一実施例の樹脂封止型半
導体装置の製造工程を説明する。The manufacturing steps of the resin-sealed semiconductor device according to one embodiment of the present invention will be described below.
【００１９】まず、予め配線パターンが形成されたプリ
ント基板２を用意し、配線パターン上の金又はアルミニ
ウムを主材料とした極細のワイヤー５が接続される領域
及び、鉛、錫等の合金からなるボール状電極４が形成さ
れる領域を除いた、プリント基板２の配線形成面に、保
護用樹脂７としてフッ素系樹脂若しくはシリコーン系樹
脂を直接印刷し、又は、フッ素系樹脂若しくはシリコー
ン系樹脂を少量加えたエポキシ樹脂を塗布する。これら
の保護用樹脂７は、後の工程で塗布されるエポキシ樹脂
に対して撥水性を有するので、プリント基板２に形成さ
れたボール状電極４が形成される領域及びプリント基板
２に形成された配線とワイヤー５との接続領域に、ワイ
ヤー５及び半導体チップ表面の保護用樹脂３が流れ込む
ことを防ぐことができる。First, a printed board 2 on which a wiring pattern is formed in advance is prepared, and a region on the wiring pattern to which a fine wire 5 mainly made of gold or aluminum is connected, and an alloy of lead, tin, or the like. A fluorine resin or a silicone resin is directly printed as a protective resin 7 on the wiring forming surface of the printed circuit board 2 excluding a region where the ball-shaped electrode 4 is formed, or a small amount of the fluorine resin or the silicone resin is used. Apply the added epoxy resin. Since these protective resins 7 have water repellency to the epoxy resin applied in a later step, they are formed on the printed board 2 in the area where the ball-shaped electrodes 4 are formed and on the printed board 2. The wire 5 and the protective resin 3 on the surface of the semiconductor chip can be prevented from flowing into the connection region between the wiring and the wire 5.
【００２０】次に、半導体チップ１の回路形成面とプリ
ント基板２の配線形成面の裏面とを接合させるために、
熱可塑性の接着剤にて、半導体チップ１とプリント基板
２とを接合させる。Next, in order to join the circuit forming surface of the semiconductor chip 1 and the back surface of the wiring forming surface of the printed circuit board 2 to each other,
A thermoplastic adhesive, to bond the semiconductor chip 1 and the printed board 2.
【００２１】次に、半導体チップ１の電極とプリント基
板２の電極とを金又はアルミニウムを主材料とした極細
のワイヤー５によってワイヤーボンディングする。その
後、プリント基板２と接合していない半導体チップ１の
回路形成面及びワイヤー５を保護するために保護用樹脂
３として、エポキシ系樹脂を塗布し、硬化させる。この
際、半導体チップ１に形成されているパッシベーション
膜（図示せず。）との接着性が良好であることから、半
導体チップ１の保護膜としてエポキシ樹脂を用いること
が望ましい。このため、フッ素系樹脂、シリコーン系樹
脂、若しくは、フッ素系樹脂又はシリコーン系樹脂を少
量加えたエポキシ樹脂とエポキシ樹脂との撥水性を利用
する場合、半導体チップ１の保護用樹脂３として、エポ
キシ樹脂が用いられる。Next, the electrodes of the semiconductor chip 1 and the electrodes of the printed circuit board 2 are wire-bonded with an ultrafine wire 5 mainly composed of gold or aluminum. Thereafter, an epoxy resin is applied and cured as a protective resin 3 for protecting the circuit forming surface of the semiconductor chip 1 and the wires 5 which are not joined to the printed board 2. At this time, it is desirable to use an epoxy resin as the protective film of the semiconductor chip 1 because the adhesiveness with a passivation film (not shown) formed on the semiconductor chip 1 is good. For this reason, when utilizing the water repellency of a fluorine-based resin, a silicone-based resin, or an epoxy resin to which a small amount of a fluorine-based resin or a silicone-based resin is added, the epoxy resin is used as the protective resin 3 of the semiconductor chip 1. Is used.
【００２２】次に、プリント基板２の配線形成面のボー
ル状電極４を形成する領域にボール状電極材料を活性化
させるためのフラックスを塗布し、その後、鉛、錫等の
合金によるボールを所定の位置に搭載し、全体を１８０
℃〜２３０℃で加熱昇温し、ボール状電極４をプリント
基板２に取り付け、樹脂封止型半導体装置が完成する。Next, a flux for activating the ball-shaped electrode material is applied to a region of the printed circuit board 2 where the ball-shaped electrode 4 is to be formed on the wiring formation surface, and then a ball made of an alloy of lead, tin or the like is applied. At the position of 180
The temperature is raised to a temperature of from 230C to 230C, and the ball-shaped electrode 4 is mounted on the printed circuit board 2 to complete a resin-sealed semiconductor device.
【００２３】[0023]
【発明の効果】以上詳細に説明したように、本発明を用
いることにより、ワイヤーのループを従来より低くする
ことができ、また、プリント基板の厚さ又はワイヤーを
保護する保護用樹脂の厚さの内、薄いほうの厚さ分だけ
従来より薄型の樹脂封止型半導体装置を提供することが
できる。As described above in detail, by using the present invention, the wire loop can be made lower than before, and the thickness of the printed circuit board or the thickness of the protective resin for protecting the wire can be reduced. Among them, it is possible to provide a resin-encapsulated semiconductor device which is thinner than the conventional one by the thickness of the thinner one.
【００２４】例えば、半導体チップサイズを１０．０ｍ
ｍ×１５．０ｍｍの上に、短辺片側に２５端子、対面の
短辺に２５端子の計５０個の電極を従来法にて、ＢＡＧ
パッケージ実装した場合と本発明による実施例を比較し
た場合、従来のパッケージ外形寸法（幅Ｗ×長さＤ×高
さＨ）は、Ｗ＝１５．０ｍｍ、Ｄ＝２１．０ｍｍ、Ｈ＝
２．２ｍｍであるのに対して、本発明による実施例のパ
ッケージ外形寸法は、Ｗ＝１０．０ｍｍ、Ｄ＝１５．０
ｍｍ、Ｈ＝１．５ｍｍとなる。このように、従来技術に
比べて、マザーボード実装体積が約１／３となり、薄型
化、小型化ができるとともに、軽量化が図れる。For example, if the semiconductor chip size is 10.0 m
A total of 50 electrodes, 25 terminals on one side of the short side and 25 terminals on the short side opposite to each other, are placed on the mx 15.0 mm by a conventional method.
When the package mounting and the embodiment according to the present invention are compared, the conventional package outer dimensions (width W × length D × height H) are W = 15.0 mm, D = 21.0 mm, and H =
In contrast to 2.2 mm, the package external dimensions of the embodiment according to the present invention are W = 10.0 mm and D = 15.0.
mm, H = 1.5 mm. As described above, the mounting volume of the motherboard is reduced to about 1/3 as compared with the related art, so that the thickness and the size can be reduced and the weight can be reduced.
【００２５】また、従来のようにスルホールを設ける必
要がなくなり、更に小型化が図れる。In addition, there is no need to provide a through hole as in the prior art, and the size can be further reduced.
【００２６】また、本発明を用いることにより、半導体
チップ表面とワイヤーとの保護膜材料としてのエポキシ
樹脂と、プリント基板のワイヤーボンディング部及びボ
ール状電極形成部以外の配線形成面の保護膜材料として
のフッ素系樹脂、又はシリコーン系樹脂、又はフッ素系
樹脂又はシリコーン系樹脂を含むエポキシ樹脂とは互い
に撥水性を有するので、プリント基板に形成された、ボ
ール状電極が形成される領域とワイヤーとの接続領域と
にワイヤー及び半導体チップ表面の保護用樹脂が流れ込
み、ボール状電極がプリント基板に形成された配線と電
気的接続できなくなることを防ぐことができる。Further, by using the present invention, an epoxy resin as a protective film material for a semiconductor chip surface and a wire, and a protective film material for a wiring forming surface other than a wire bonding portion and a ball-shaped electrode forming portion of a printed circuit board. Since the fluorine-based resin, or the silicone-based resin, or the epoxy resin containing the fluorine-based resin or the silicone-based resin has water repellency, the region formed with the ball-shaped electrode on the printed circuit board and the wire It is possible to prevent the wire and the resin for protecting the surface of the semiconductor chip from flowing into the connection region and preventing the ball-shaped electrode from being electrically connected to the wiring formed on the printed circuit board.
【００２７】さらに、本発明を用いることにより、半導
体チップ上にプリント基板を貼り付けた後、ワイヤーを
接続する際に生じた不良をプリント基板を貼り替えるこ
とにより、半導体チップを破棄することなく、再利用が
可能となり、不良発生時の損失を小さくすることが可能
となった。 Further, by using the present invention, after a printed circuit board is pasted on a semiconductor chip, defects that occur when connecting wires are replaced by replacing the printed circuit board without discarding the semiconductor chip. Reuse becomes possible, and loss at the time of occurrence of a defect can be reduced.
【図１】（ａ）は本発明の一実施例のプリント基板にボ
ール状の外部端子を設けた樹脂封止型半導体装置の表面
図、（ｂ）は同（ａ）の樹脂封止型半導体装置の断面図
である。1 (a) is a surface view of a resin sealed semiconductor device provided external terminals shaped ball on a printed circuit board of an embodiment of the present invention, (b) a resin-encapsulated semiconductor of the same (a) Sectional view of the device
It is.
【図２】図１（ｂ）の一部拡大図である。FIG. 2 is a partially enlarged view of FIG. 1 (b).
【図３】（ａ）は従来のプリント基板にボール状の外部
端子を設けた樹脂封止型半導体装置の表面図、（ｂ）は
同（ａ）の樹脂封止型半導体装置の断面図、（ｃ）は同
（ａ）の樹脂封止型半導体装置の裏面図である。3 (a) is a surface view of a conventional resin-sealed semiconductor device provided with external terminals like the ball on a printed circuit board, (b) is a sectional view of a resin sealed semiconductor device of the (a), (C) is the same
FIG . 3A is a back view of the resin-encapsulated semiconductor device .
【図４】図３（ｂ）の一部拡大図である。FIG. 4 is a partially enlarged view of FIG. 3 (b).
１ 半導体チップ ２ プリント基板 ３ 半導体チップ表面及びワイヤーを保護する保護用樹
脂 ４ ボール状電極 ５ ワイヤー ６ 半導体チップとプリント基板とを接合する接着剤 ７ プリント基板に形された配線を保護する保護用樹脂DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Printed circuit board 3 Protective resin which protects a semiconductor chip surface and a wire 4 Ball-shaped electrode 5 Wire 6 Adhesive which joins a semiconductor chip and a printed circuit board 7 Protective resin which protects a wiring formed in a printed circuit board
Claims (2)
の回路形成面と該半導体チップより面積の小さいプリン
ト基板の配線形成面の裏面とが、上記半導体チップに形
成された電極が露出するように接合され、 且つ、上記半導体チップの外周部に形成された電極と上
記プリント基板に形成された配線とがボンディングによ
り電気的に接続され、 且つ、上記プリント基板の配線形成面に該配線と電気的
に接続されたボール状の電極を設けた樹脂封止型半導体
装置であって、 上記半導体チップの回路形成面及び上記ボンディングに
用いられるワイヤーを保護する保護材としてエポキシ樹
脂を用い、 且つ、プリント基板の、ボール状電極が形成される領域
及びワイヤーとの接続領域以外の配線形成面を保護する
保護材としてフッ素系樹脂、又はシリコーン系樹脂、又
はフッ素系樹脂又はシリコーン系樹脂を含むエポキシ樹
脂を用いることを特徴とする樹脂封止型半導体装置。1. A circuit forming surface of a semiconductor chip having electrodes formed on an outer periphery thereof and a back surface of a wiring forming surface of a printed circuit board having a smaller area than the semiconductor chip so that the electrodes formed on the semiconductor chip are exposed. And an electrode formed on the outer peripheral portion of the semiconductor chip and a wiring formed on the printed board are electrically connected by bonding, and the wiring is electrically connected to a wiring forming surface of the printed board. A resin-encapsulated semiconductor device provided with electrically connected ball-shaped electrodes, wherein an epoxy resin is used as a protective material for protecting a circuit forming surface of the semiconductor chip and wires used for the bonding, and printed. As a protective material for protecting the wiring forming surface of the substrate other than the area where the ball-shaped electrodes are formed and the area where the wiring is connected to the wire, a fluororesin or silicon is used. Corn-based resin, or a resin-sealed semiconductor device, which comprises using an epoxy resin containing a fluorine-based resin or a silicone resin.
の回路形成面と該半導体チップより面積の小さいプリン
ト基板の配線形成面の裏面とが、熱可塑性の接着剤によ
り、上記半導体チップに形成された電極が露出するよう
に接合され、 且つ、上記半導体チップの外周部に形成された電極と上
記プリント基板に形成された配線とがボンディングによ
り電気的に接続され、 且つ、上記プリント基板の配線形成面に該配線と電気的
に接続されたボール状の電極を設けた樹脂封止型半導体
装置であって、 上記半導体チップの回路形成面及び上記ボンディングに
用いられるワイヤーを保護する保護材としてエポキシ樹
脂を用い、 且つ、プリント基板の、ボール状電極が形成される領域
及びワイヤーとの接続領域以外の配線形成面を保護する
保護材としてフッ素系樹脂、又はシリコーン系樹脂、又
はフッ素系樹脂又はシリコーン系樹脂を含むエポキシ樹
脂を用いることを特徴とする樹脂封止型半導体装置。2. A semiconductor chip having electrodes formed on an outer peripheral portion.
Circuit forming surface and a pudding smaller in area than the semiconductor chip
The back side of the wiring formation surface of the
So that the electrodes formed on the semiconductor chip are exposed.
It is joined to, and, the semiconductor chip periphery portion formed electrodes and above the
The wiring formed on the printed circuit board is
And electrically connected to the wiring on the wiring forming surface of the printed circuit board.
Encapsulated semiconductor with ball-shaped electrodes connected to
An apparatus, wherein an epoxy resin is used as a protective material for protecting a circuit forming surface of the semiconductor chip and a wire used for the bonding, and a region where a ball-shaped electrode is formed and a connection region with the wire on a printed circuit board. A resin-encapsulated semiconductor device using a fluorine-based resin, a silicone-based resin, or an epoxy resin containing a fluorine-based resin or a silicone-based resin as a protective material for protecting a wiring forming surface other than the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812495A JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812495A JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264678A JPH08264678A (en) | 1996-10-11 |
| JP3145892B2 true JP3145892B2 (en) | 2001-03-12 |
Family
ID=13364693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6812495A Expired - Fee Related JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3145892B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4702157B2 (en) * | 2006-04-17 | 2011-06-15 | パナソニック株式会社 | IC component mounting method and die bonding apparatus |
-
1995
- 1995-03-27 JP JP6812495A patent/JP3145892B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08264678A (en) | 1996-10-11 |
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