JPH08264678A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH08264678A JPH08264678A JP6812495A JP6812495A JPH08264678A JP H08264678 A JPH08264678 A JP H08264678A JP 6812495 A JP6812495 A JP 6812495A JP 6812495 A JP6812495 A JP 6812495A JP H08264678 A JPH08264678 A JP H08264678A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- circuit board
- printed circuit
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プリント基板にボール
状の外部端子を設けた樹脂封止型半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device having a printed board provided with ball-shaped external terminals.
【０００２】[0002]
【従来の技術】図３（ａ）に従来のプリント基板にボー
ル状の外部端子を設けた樹脂封止型半導体装置（ＢＡＬ
Ｌ ＧＲＩＤ ＡＲＲＡＹ、以下「ＢＧＡ」とする。）
の表面図、同（ｂ）に同ＢＧＡの断面図を示し、図４は
図３（ｂ）の一部拡大図である。2. Description of the Related Art FIG. 3A shows a conventional resin-sealed semiconductor device (BAL) in which ball-shaped external terminals are provided on a conventional printed circuit board.
L GRID ARRAY, hereinafter referred to as "BGA". )
3B is a sectional view of the BGA, and FIG. 4 is a partially enlarged view of FIG. 3B.
【０００３】尚、図３及び図４において、１は半導体チ
ップ、２はプリント基板、３は半導体チップ表面及び金
又はアルミニウムを主成分とした極細のワイヤー５を保
護する保護用樹脂、４は鉛、錫等の合金によるボール状
電極、６は半導体チップとプリント基板とを接合する接
着剤、８はスルーホールを示す。但し、ボール状電極４
及びワイヤー５はこれらに限定されるものではない。In FIGS. 3 and 4, 1 is a semiconductor chip, 2 is a printed circuit board, 3 is a protective resin for protecting the surface of the semiconductor chip and an ultrafine wire 5 mainly composed of gold or aluminum, and 4 is lead. , A ball-shaped electrode made of an alloy such as tin, 6 is an adhesive for joining the semiconductor chip and the printed board, and 8 is a through hole. However, the ball-shaped electrode 4
The wire 5 is not limited to these.
【０００４】従来のＢＧＡは、図３及び図４に示すよう
に、半導体チップ１の回路形成面の外周部に形成された
電極とプリント基板２に形成された配線とをワイヤーに
てワイヤーボンディングし、プリント基板２の半導体チ
ップ１と接合された面と反対面において、プリント基板
２に形成された配線と電気的に接続されたボール状電極
を形成する。また、プリント基板２に設けられたスルー
ホール８にて、プリント基板の両面の導通を確保してい
る。In the conventional BGA, as shown in FIGS. 3 and 4, the electrodes formed on the outer peripheral portion of the circuit forming surface of the semiconductor chip 1 and the wiring formed on the printed board 2 are wire-bonded with a wire. A ball-shaped electrode electrically connected to the wiring formed on the printed board 2 is formed on the surface of the printed board 2 opposite to the surface bonded to the semiconductor chip 1. The through holes 8 provided in the printed circuit board 2 ensure electrical continuity on both sides of the printed circuit board.
【０００５】[0005]
【発明が解決しようとする課題】しかし、上述の従来技
術においては、比較的入出力信号数の少ない半導体装置
において、半導体チップの電極から全ての電極とも外周
方向にワイヤーにてプリント基板と電気的接続する際、
図４に示すように、ワイヤー５が半導体チップ１に接触
し、電気的短絡が生じないように、ループを形成する必
要があった。そのため、ループが形成されたワイヤー５
を封止するため樹脂封止型半導体装置の薄型化に制限が
あった。However, in the above-mentioned prior art, in a semiconductor device having a relatively small number of input / output signals, all electrodes from the electrodes of the semiconductor chip are electrically connected to the printed circuit board by wires in the outer peripheral direction. When connecting,
As shown in FIG. 4, it was necessary to form a loop so that the wire 5 did not contact the semiconductor chip 1 and an electrical short circuit did not occur. Therefore, the wire 5 with the loop formed
Therefore, there is a limitation in reducing the thickness of the resin-encapsulated semiconductor device for sealing.
【０００６】また、プリント基板２の両面を電気的に接
続するためのスルーホール８を形成する領域を確保する
必要がある。In addition, it is necessary to secure a region for forming a through hole 8 for electrically connecting both surfaces of the printed board 2.
【０００７】本発明は、スルーホールの形成が必要な
い、従来より薄型化が可能な樹脂封止型半導体装置を提
供することを目的とするものである。It is an object of the present invention to provide a resin-sealed semiconductor device which does not require the formation of through holes and can be made thinner than before.
【０００８】[0008]
【課題を解決するための手段】請求項１記載の本発明の
樹脂封止型半導体装置は、外周部に電極が形成された半
導体チップの回路形成面と該半導体チップより面積の小
さいプリント基板の配線形成面の裏面とが、上記半導体
チップに形成された電極が露出するように接合され、且
つ、上記半導体チップの外周部に形成された電極と上記
プリント基板に形成された配線とがボンディングにより
電気的に接続され、且つ、上記プリント基板の配線形成
面に該配線と電気的に接続されたボール状の電極を設け
たことを特徴とするものである。According to a first aspect of the present invention, there is provided a resin-encapsulated semiconductor device comprising: a circuit forming surface of a semiconductor chip having electrodes formed on an outer periphery thereof; and a printed circuit board having an area smaller than that of the semiconductor chip. The back surface of the wiring forming surface is joined so that the electrodes formed on the semiconductor chip are exposed, and the electrodes formed on the outer peripheral portion of the semiconductor chip and the wiring formed on the printed board are bonded by bonding. It is characterized in that a ball-shaped electrode that is electrically connected and that is electrically connected to the wiring is provided on the wiring forming surface of the printed board.
【０００９】また、請求項２記載の本発明の樹脂封止型
半導体装置は、上記半導体チップの回路形成面及び上記
ボンディングに用いられるワイヤ−を保護する保護膜と
してエポキシ樹脂を用い、且つ、プリント基板の、ボー
ル状電極が形成される領域及びワイヤーとの接続領域以
外の配線形成面を保護する保護膜としてフッ素系樹脂、
又はシリコーン系樹脂、又はフッ素系樹脂又はシリコー
ン系樹脂を含むエポキシ樹脂を用いることを特徴とす
る、請求項１記載の樹脂封止型半導体装置である。According to a second aspect of the present invention, in the resin-encapsulated semiconductor device, an epoxy resin is used as a protective film for protecting the circuit forming surface of the semiconductor chip and the wire used for the bonding, and a print is used. Fluorine-based resin as a protective film for protecting the wiring formation surface of the substrate, except for the region where the ball-shaped electrode is formed and the connection region with the wire,
Alternatively, the resin-encapsulated semiconductor device according to claim 1, wherein a silicone-based resin, or an epoxy resin containing a fluorine-based resin or a silicone-based resin is used.
【００１０】更に、請求項３記載の本発明の樹脂封止型
半導体装置は、上記半導体チップと上記プリント基板と
の接合を熱可塑性の接着剤を用いることを特徴をする、
請求項１又は請求項２記載の樹脂封止型半導体装置であ
る。Further, the resin-encapsulated semiconductor device of the present invention according to claim 3 is characterized in that a thermoplastic adhesive is used to bond the semiconductor chip and the printed board.
The resin-sealed semiconductor device according to claim 1 or 2.
【００１１】[0011]
【作用】上記請求項１記載の構成により、ワイヤーはル
ープ高さが従来より低くても、半導体チップのエッジで
はなく、絶縁材料で形成されたプリント基板のエッジと
接触することになるため、ワイヤーのループを従来より
低くすることができ、また、プリント基板の厚さ又はワ
イヤーを保護する保護用樹脂の厚さの内、薄いほうの厚
さ分だけ従来より薄型にすることができる。According to the structure described in claim 1, even if the wire has a loop height lower than that of the prior art, the wire is not in contact with the edge of the semiconductor chip but with the edge of the printed circuit board formed of an insulating material. Can be made lower than before, and can be made thinner than before by the thinner one of the thickness of the printed circuit board or the protective resin that protects the wires.
【００１２】また、請求項２記載の構成により、半導体
チップ表面とワイヤーとの保護膜材料としてのエポキシ
樹脂と、プリント基板のワイヤーボンディング部及びボ
ール状電極形成部以外の配線形成面の保護膜材料として
のフッ素系樹脂、又はシリコーン系樹脂、又はフッ素系
樹脂又はシリコーン系樹脂を含むエポキシ樹脂とは互い
に撥水性を有するので、プリント基板に形成されたボー
ル状電極が設けられる領域及びワイヤーとプリント基板
２に形成された配線との接続領域に、ワイヤー及び半導
体チップ表面の保護用樹脂が流れ込むことを防ぐことが
できる。According to the second aspect of the present invention, an epoxy resin as a protective film material for the surface of the semiconductor chip and the wire, and a protective film material for the wiring forming surface other than the wire bonding portion and the ball-shaped electrode forming portion of the printed board. Since the fluorine-based resin or the silicone-based resin as described above or the epoxy resin containing the fluorine-based resin or the silicone-based resin have water repellency with each other, the area where the ball-shaped electrode formed on the printed board and the wire and the printed board are formed. It is possible to prevent the wires and the protective resin on the surface of the semiconductor chip from flowing into the connection area with the wiring formed in 2.
【００１３】更に、請求項３記載の構成により、半導体
チップ上にプリント基板を貼り付けた後、ワイヤーを接
続する際に不良が生じた場合、熱を加えることによっ
て、半導体チップからプリント基板を剥がすことがで
き、プリント基板のみを取り替えることができる。Further, according to the third aspect of the present invention, after the printed circuit board is attached on the semiconductor chip, if a defect occurs in connecting the wires, the printed circuit board is peeled from the semiconductor chip by applying heat. It is possible to replace only the printed circuit board.
【００１４】[0014]
【実施例】以下、一実施例に基づいて本発明について詳
細に説明する。The present invention will be described in detail below based on an example.
【００１５】図１（ａ）は本発明の一実施例のプリント
基板にボール状の外部端子を設けた樹脂封止型半導体装
置（以下「ＢＧＡ」とする。）の表面図、同（ｂ）に同
ＢＧＡの断面図、同（ｃ）に同ＢＧＡの裏面図であり、
図２は図１（ｂ）の一部拡大図である。尚、図１におけ
るＡ部は保護用樹脂３を剥がした状態を示している。FIG. 1A is a front view of a resin-sealed semiconductor device (hereinafter referred to as "BGA") in which a ball-shaped external terminal is provided on a printed circuit board according to an embodiment of the present invention, and FIG. Fig. 3 is a sectional view of the BGA, and Fig. 3C is a back view of the BGA.
FIG. 2 is a partially enlarged view of FIG. The portion A in FIG. 1 shows a state in which the protective resin 3 is peeled off.
【００１６】図１及び図２において、１は半導体チッ
プ、２はプリント基板、３は半導体チップ表面及び金又
はアルミニウムを主成分とした極細のワイヤー５を保護
する保護用樹脂、４は鉛、錫等の合金によるボール状電
極、６は半導体チップとプリント基板とを接合する接着
剤、７はプリント基板２に形成された配線を保護する保
護用樹脂を示す。尚、ボール状電極４及びワイヤー５は
これらに限定されるものではない。In FIGS. 1 and 2, 1 is a semiconductor chip, 2 is a printed circuit board, 3 is a protective resin for protecting the surface of the semiconductor chip and an extremely fine wire 5 mainly composed of gold or aluminum, and 4 is lead, tin. A ball-shaped electrode made of an alloy such as 6 is an adhesive for joining the semiconductor chip and the printed board, and 7 is a protective resin for protecting the wiring formed on the printed board 2. The ball-shaped electrode 4 and the wire 5 are not limited to these.
【００１７】本発明は、図１及び図２に示すように、半
導体チップ１の面積はプリント基板２の面積より大き
く、且つ、半導体チップ１の回路形成面とプリント基板
２の配線形成面と反対面とを接着剤６で接合し、且つ、
半導体チップ１の外周部に設けられた外部電極とプリン
ト基板２に形成された配線とをワイヤー５で電気的に接
続し、且つ、プリント基板２に形成された配線と電気的
に接続されたボール状電極４を設けたことを特徴とする
ものである。According to the present invention, as shown in FIGS. 1 and 2, the area of the semiconductor chip 1 is larger than the area of the printed board 2, and the circuit forming surface of the semiconductor chip 1 and the wiring forming surface of the printed board 2 are opposite to each other. Bonded to the surface with an adhesive 6, and
A ball electrically connecting an external electrode provided on the outer peripheral portion of the semiconductor chip 1 to a wiring formed on the printed board 2 by a wire 5, and electrically connected to a wiring formed on the printed board 2. It is characterized in that the electrode 4 is provided.
【００１８】以下に、本発明の一実施例の樹脂封止型半
導体装置の製造工程を説明する。The manufacturing process of the resin-sealed semiconductor device of one embodiment of the present invention will be described below.
【００１９】まず、予め配線パターンが形成されたプリ
ント基板２を用意し、配線パターン上の金又はアルミニ
ウムを主材料とした極細のワイヤー５が接続される領域
及び、鉛、錫等の合金からなるボール状電極４が形成さ
れる領域を除いた、プリント基板２の配線形成面に、保
護用樹脂８としてフッ素系樹脂若しくはシリコーン系樹
脂を直接印刷し、又は、フッ素系樹脂若しくはシリコー
ン系樹脂を少量加えたエポキシ樹脂を塗布する。これら
の保護用樹脂８は、後の工程で塗布させるエポキシ樹脂
に対して撥水性を有するので、プリント基板２に形成さ
れたボール状電極４が形成される領域及びプリント基板
２に形成された配線とワイヤー５との接続領域に、ワイ
ヤー及び半導体チップ表面の保護用樹脂３が流れ込むこ
とを防ぐことができる。First, a printed circuit board 2 on which a wiring pattern is formed in advance is prepared, and the area on the wiring pattern to which the ultrafine wire 5 having gold or aluminum as a main material is connected and an alloy such as lead or tin are formed. Fluorine-based resin or silicone-based resin is directly printed as the protective resin 8 on the wiring formation surface of the printed circuit board 2 excluding the area where the ball-shaped electrode 4 is formed, or a small amount of fluorine-based resin or silicone-based resin is used. Apply the added epoxy resin. Since these protective resins 8 have water repellency with respect to the epoxy resin applied in a later step, the area formed with the ball-shaped electrodes 4 on the printed circuit board 2 and the wiring formed on the printed circuit board 2 will be described. It is possible to prevent the protective resin 3 on the surface of the wire and the semiconductor chip from flowing into the connection region between the wire 5 and the wire 5.
【００２０】次に、半導体チップ１の回路形成面とプリ
ント基板２の配線形成面の裏面とを接合させるために、
熱可塑性の接着剤を塗布し、半導体チップ１とプリント
基板２とを接合させる。Next, in order to join the circuit forming surface of the semiconductor chip 1 and the back surface of the wiring forming surface of the printed board 2,
A thermoplastic adhesive is applied to bond the semiconductor chip 1 and the printed board 2 together.
【００２１】次に、半導体チップ１の電極とプリント基
板２の電極とを金又はアルミニウムを主材料とした極細
のワイヤー５によってワイヤーボンディングする。その
後、プリント基板２と接合していない半導体チップ１の
回路形成面及びワイヤー５を保護するために保護用樹脂
３として、エポキシ系樹脂を塗布し、硬化させる。この
際、半導体チップ１に形成されているパッシベーション
膜（図示せず。）との接着性が良好であることから、半
導体チップ１の保護膜としてエポキシ樹脂を用いること
が望ましい。このため、フッ素系樹脂、シリコーン系樹
脂、若しくは、フッ素系樹脂又はシリコーン系樹脂を少
量加えたエポキシ樹脂とエポキシ樹脂との撥水性を利用
する場合、半導体チップ１の保護用樹脂３として、エポ
キシ樹脂が用いられる。Next, the electrodes of the semiconductor chip 1 and the electrodes of the printed circuit board 2 are wire-bonded with an ultrafine wire 5 whose main material is gold or aluminum. After that, an epoxy resin is applied and cured as a protective resin 3 for protecting the circuit formation surface of the semiconductor chip 1 not bonded to the printed board 2 and the wires 5. At this time, it is desirable to use an epoxy resin as a protective film for the semiconductor chip 1 because it has good adhesion to a passivation film (not shown) formed on the semiconductor chip 1. Therefore, when the water repellency of the fluororesin, the silicone resin, or the epoxy resin containing a small amount of the fluororesin or the silicone resin and the epoxy resin is used, the epoxy resin is used as the protective resin 3 for the semiconductor chip 1. Is used.
【００２２】次に、プリント基板２の配線形成面のボー
ル状電極４を形成する領域にボール状電極材料を活性化
させるためのフラックスを塗布し、その後、鉛、錫等の
合金によるボールを所定の位置に搭載し、全体を１８０
℃〜２３０℃で加熱昇温し、ボール状電極４をプリント
基板２に取り付け、樹脂封止型半導体装置が完成する。Next, a flux for activating the ball-shaped electrode material is applied to a region where the ball-shaped electrode 4 is to be formed on the wiring formation surface of the printed board 2, and then a ball made of an alloy such as lead or tin is predetermined. Mounted at the position of 180
The ball-shaped electrode 4 is attached to the printed circuit board 2 by heating and raising the temperature at ℃ to 230 ℃, the resin-sealed semiconductor device is completed.
【００２３】[0023]
【発明の効果】以上詳細に説明したように、請求項１記
載の本発明を用いることにより、ワイヤーのループを従
来より低くすることができ、また、プリント基板の厚さ
又はワイヤーを保護する保護用樹脂の厚さの内、薄いほ
うの厚さ分だけ従来より薄型の樹脂封止型半導体装置を
提供することができる。As described above in detail, by using the present invention as set forth in claim 1, the loop of the wire can be made lower than before, and the thickness of the printed circuit board or the protection for protecting the wire can be improved. It is possible to provide a resin-encapsulated semiconductor device that is thinner than the conventional one by the thinner thickness of the resin for use.
【００２４】例えば、半導体チップサイズを１０．０ｍ
ｍ×１５．０ｍｍの上に、短辺片側に２５端子、対面の
短辺に２５端子の計５０個の電極を従来法にて、ＢＡＧ
パッケージ実装した場合と本発明による実施例を比較し
た場合、従来のパッケージ外形寸法（幅Ｗ×長さＤ×高
さＨ）は、Ｗ＝１５．０ｍｍ、Ｄ＝２１．０ｍｍ、Ｈ＝
２．２ｍｍであるのに対して、本発明による実施例のパ
ッケージ外形寸法は、Ｗ＝１０．０ｍｍ、Ｄ＝１５．０
ｍｍ、Ｈ＝１．５ｍｍとなる。このように、従来技術に
比べて、マザーボード実装体積が約１／３となり、薄型
化、小型化ができるとともに、軽量化が図れる。For example, if the semiconductor chip size is 10.0 m
A total of 50 electrodes, 25 terminals on one side of the short side and 25 terminals on the opposite short side, were placed on m × 15.0 mm by the conventional method.
When the package mounting is compared with the embodiment according to the present invention, the conventional package outer dimensions (width W × length D × height H) are W = 15.0 mm, D = 21.0 mm, H =
The external dimensions of the package of the embodiment according to the present invention are 2.2 mm, W = 10.0 mm, and D = 15.0.
mm, H = 1.5 mm. As described above, the mounting volume of the motherboard is about ⅓ of that of the conventional technique, which enables reduction in thickness and size as well as reduction in weight.
【００２５】また、従来のようにスルホールを設ける必
要がなくなり、更に小型化が図れる。Further, unlike the conventional case, it is not necessary to provide through holes, and the size can be further reduced.
【００２６】また、請求項２記載の本発明を用いること
により、半導体チップ表面とワイヤーとの保護膜材料と
してのエポキシ樹脂と、プリント基板のワイヤーボンデ
ィング部及びボール状電極形成部以外の配線形成面の保
護膜材料としてのフッ素系樹脂、又はシリコーン系樹
脂、又はフッ素系樹脂又はシリコーン系樹脂を含むエポ
キシ樹脂とは互いに撥水性を有するので、プリント基板
に形成された、ボール状電極が形成される領域とワイヤ
ーとの接続領域とにワイヤ−及び半導体チップ表面の保
護用樹脂が流れ込み、ボール状電極がプリント基板に形
成された配線と電気的接続できなくなることを防ぐこと
ができる。Further, by using the present invention according to claim 2, an epoxy resin as a protective film material for the surface of the semiconductor chip and the wire, and a wiring forming surface other than the wire bonding portion and the ball-shaped electrode forming portion of the printed board. The ball-shaped electrodes formed on the printed circuit board are formed because they have water repellency with the fluorine-based resin, the silicone-based resin, or the epoxy resin containing the fluorine-based resin or the silicone-based resin as the protective film material. It is possible to prevent the protective resin on the surface of the wire and the semiconductor chip from flowing into the area and the connection area between the wire and the ball-shaped electrode from being unable to be electrically connected to the wiring formed on the printed board.
【００２７】更に、請求項３記載の本発明を用いること
により、半導体チップ上にプリント基板を貼り付けた
後、ワイヤーを接続する際に生じた不良をプリント基板
を貼り替えることにより、半導体チップを破棄すること
なく、再利用が可能となり、不良発生時の損失を小さく
することが可能となった。Further, by using the present invention as set forth in claim 3, the semiconductor chip can be formed by attaching the printed circuit board on the semiconductor chip and then re-attaching the printed circuit board to the defects caused when the wires are connected. It became possible to reuse without discarding, and it became possible to reduce the loss when a defect occurred.
【図１】（ａ）は本発明の一実施例のプリント基板にボ
ール状の外部端子を設けた樹脂封止型半導体装置の表面
図、同（ｂ）に同樹脂封止型半導体装置の断面図、同
（ｃ）に同樹脂封止型半導体装置の裏面図である。FIG. 1A is a front view of a resin-encapsulated semiconductor device in which a ball-shaped external terminal is provided on a printed circuit board according to an embodiment of the present invention, and FIG. 1B is a cross-section of the resin-encapsulated semiconductor device. FIG. 3C is a back view of the same resin-sealed semiconductor device.
【図２】図１（ｂ）の一部拡大図である。FIG. 2 is a partially enlarged view of FIG. 1 (b).
【図３】（ａ）は従来のプリント基板にボール状の外部
端子を設けた樹脂封止型半導体装置の表面図であり、同
（ｂ）は同樹脂封止型半導体装置の断面図である。3A is a front view of a resin-sealed semiconductor device in which a ball-shaped external terminal is provided on a conventional printed circuit board, and FIG. 3B is a cross-sectional view of the resin-sealed semiconductor device. .
【図４】図３（ｂ）の一部拡大図である。FIG. 4 is a partially enlarged view of FIG.
１ 半導体チップ ２ プリント基板 ３ 半導体チップ表面及びワイヤーを保護する保護用樹
脂 ４ ボール状電極 ５ ワイヤー ６ 半導体チップとプリント基板とを接合する接着剤 ７ プリント基板に形された配線を保護する保護用樹脂1 Semiconductor Chip 2 Printed Circuit Board 3 Protective Resin for Protecting Semiconductor Chip Surface and Wire 4 Ball Electrode 5 Wire 6 Adhesive for Joining Semiconductor Chip and Printed Circuit Board 7 Protective Resin for Protecting Wiring Formed on Printed Circuit Board
Claims (3)
の回路形成面と該半導体チップより面積の小さいプリン
ト基板の配線形成面の裏面とが、上記半導体チップに形
成された電極が露出するように接合され、 且つ、上記半導体チップの外周部に形成された電極と上
記プリント基板に形成された配線とがボンディングによ
り電気的に接続され、 且つ、上記プリント基板の配線形成面に該配線と電気的
に接続されたボール状の電極を設けたことを特徴とする
樹脂封止型半導体装置。1. An electrode formed on the semiconductor chip is exposed on a circuit forming surface of a semiconductor chip having electrodes formed on its outer periphery and a back surface of a wiring forming surface of a printed circuit board having a smaller area than the semiconductor chip. And the electrodes formed on the outer peripheral portion of the semiconductor chip and the wiring formed on the printed circuit board are electrically connected by bonding, and the wiring is electrically connected to the wiring formation surface of the printed circuit board. A resin-encapsulated semiconductor device having electrically connected ball-shaped electrodes.
ボンディングに用いられるワイヤ−を保護する保護膜と
してエポキシ樹脂を用い、 且つ、プリント基板の、ボール状電極が形成される領域
及びワイヤーとの接続領域以外の配線形成面を保護する
保護膜としてフッ素系樹脂、又はシリコーン系樹脂、又
はフッ素系樹脂又はシリコーン系樹脂を含むエポキシ樹
脂を用いることを特徴とする、請求項１記載の樹脂封止
型半導体装置。2. An epoxy resin is used as a protective film for protecting a circuit forming surface of the semiconductor chip and a wire used for the bonding, and the printed board is connected to a region where a ball-shaped electrode is formed and the wire. 2. The resin-sealed mold according to claim 1, wherein a fluorine-based resin, a silicone-based resin, or an epoxy resin containing a fluorine-based resin or a silicone-based resin is used as a protective film for protecting the wiring formation surface other than the region. Semiconductor device.
の接合を熱可塑性の接着剤を用いることを特徴をする、
請求項１又は請求項２記載の樹脂封止型半導体装置。3. A thermoplastic adhesive is used to bond the semiconductor chip and the printed circuit board together,
The resin-sealed semiconductor device according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812495A JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6812495A JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264678A true JPH08264678A (en) | 1996-10-11 |
| JP3145892B2 JP3145892B2 (en) | 2001-03-12 |
Family
ID=13364693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6812495A Expired - Fee Related JP3145892B2 (en) | 1995-03-27 | 1995-03-27 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3145892B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007287927A (en) * | 2006-04-17 | 2007-11-01 | Matsushita Electric Ind Co Ltd | Ic component mounting method, die bonding apparatus, and electronic component |
-
1995
- 1995-03-27 JP JP6812495A patent/JP3145892B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007287927A (en) * | 2006-04-17 | 2007-11-01 | Matsushita Electric Ind Co Ltd | Ic component mounting method, die bonding apparatus, and electronic component |
| JP4702157B2 (en) * | 2006-04-17 | 2011-06-15 | パナソニック株式会社 | IC component mounting method and die bonding apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3145892B2 (en) | 2001-03-12 |
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