JP2000286375A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000286375A JP2000286375A JP11089251A JP8925199A JP2000286375A JP 2000286375 A JP2000286375 A JP 2000286375A JP 11089251 A JP11089251 A JP 11089251A JP 8925199 A JP8925199 A JP 8925199A JP 2000286375 A JP2000286375 A JP 2000286375A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- island
- semiconductor chip
- frame
- connection
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、リードフレームの如き、Ｃｕフレームを用いたＣＳ
Ｐ型の半導体装置に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly, to a CS device using a Cu frame such as a lead frame.
The present invention relates to a P-type semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置は、周知事項ではあるが、ウ
ェハの状態でマトリックス状にＩＣが作り込まれ、この
ＩＣを囲み格子状にダイシングライン部が設けられ、こ
のダイシングライン部に沿って個々にダイシングされ、
個々の半導体装置（半導体チップ）に分離形成される。
そしてリードフレームに実装し、ＩＣとリードとをワイ
ヤボンディングしパッケージされる。2. Description of the Related Art In a semiconductor device, as is well known, ICs are formed in a matrix in a wafer state, and a dicing line portion is provided in a grid shape surrounding the IC, and individual ICs are formed along the dicing line portion. Is diced into
Separately formed on individual semiconductor devices (semiconductor chips).
Then, it is mounted on a lead frame, and the IC and the lead are wire-bonded and packaged.
【０００３】しかし携帯電話やディジタルカメラ等の軽
薄短小化を受けて、半導体装置も益々小型化が要求さ
れ、最近は限りなくチップサイズに近づく技術としてＣ
ＳＰ、ウェハスケールＣＳＰが開発されている。However, with the miniaturization of mobile phones, digital cameras, and the like, semiconductor devices have been required to be more and more miniaturized.
SPs and wafer scale CSPs have been developed.
【０００４】半導体チップを基板に実装し、ワイヤボン
ディングを採用してチップサイズを小さくするＣＳＰと
しては、例えば、特開平１０―９２９７９号公報や特開
昭５８−２０１３４７号公報がある。As CSPs in which a semiconductor chip is mounted on a substrate and the chip size is reduced by employing wire bonding, there are, for example, JP-A-10-92979 and JP-A-58-201347.
【０００５】これらの技術は、接続として信頼性の高い
金属細線接続を採用しつつ、金属細線から先のリードフ
レームの延在長を限りなく少なくするため、セラミック
基板を採用し、チップサイズを小さくしたものである。[0005] These techniques employ a ceramic substrate to minimize the extension length of the lead frame beyond the metal thin wire while employing a highly reliable thin metal wire connection as a connection, and thereby reduce the chip size. It was done.
【０００６】図７と図８は、その概要を説明したもので
ある。図７に於いて、セラミック基板１には、半導体チ
ップ２が固着され、半導体チップ２のボンディングパッ
ドとセラミック基板１上のパッド電極３は、金属細線を
介して接続される。そしてセラミック基板１は、必要に
よりスルーホールや多層配線が施され、ロウ材を介して
実装基板と半田付けされるパッド４がセラミック基板１
裏面に設けられている。半導体チップ２のボンディング
パッドは、金属細線、パッド電極３、スルーホールまた
は多層配線を介して裏面のパッド４と電気的に接続され
る。FIG. 7 and FIG. 8 explain the outline. In FIG. 7, a semiconductor chip 2 is fixed to a ceramic substrate 1, and a bonding pad of the semiconductor chip 2 and a pad electrode 3 on the ceramic substrate 1 are connected via a thin metal wire. The ceramic substrate 1 is provided with through holes and multilayer wiring as necessary, and the pads 4 to be soldered to the mounting substrate via a brazing material are attached to the ceramic substrate 1.
It is provided on the back. The bonding pads of the semiconductor chip 2 are electrically connected to the pads 4 on the back surface through thin metal wires, pad electrodes 3, through holes or multilayer wiring.
【０００７】そして図８の如く、樹脂封止体５が形成さ
れ、矢印で示した部分でダイシングされる。このダイシ
ングは、セラミック基板の裏面側または表側どちらでも
良い。またセラミック基板には割り溝が設けられ、セラ
ミック基板の手前までダイシングし、セラミック基板は
割り溝を介してブレークされても良い。Then, as shown in FIG. 8, a resin sealing body 5 is formed, and diced at a portion indicated by an arrow. This dicing may be performed on either the back side or the front side of the ceramic substrate. Further, the ceramic substrate may be provided with a split groove, and the dicing may be performed up to the front of the ceramic substrate, and the ceramic substrate may be broken through the split groove.
【０００８】[0008]
【発明が解決しようとする課題】前述した構造は、リー
ドフレームを採用したパッケージと異なり、リードがパ
ッケージ内に取り込まれず、パッド電極が極めて小さい
ため、その分小さくすることができる。In the above-described structure, unlike the package using a lead frame, the lead is not taken into the package and the pad electrode is extremely small, so that the size can be reduced accordingly.
【０００９】しかしながらセラミック基板１は、スルー
ホールや多層配線を施したり、パッド電極３、パッド４
にＡｕメッキを必要とするため、コストが上昇する問題
があった。However, the ceramic substrate 1 is provided with through-holes and multi-layer wirings,
However, since Au plating is required, there is a problem that the cost increases.
【００１０】またセラミック基板１の電極は、一般には
印刷であり、実装基板との接続は、印刷電極の厚みが要
因で、接続強度がそれほど高くできない問題もあった。The electrodes of the ceramic substrate 1 are generally printed, and the connection with the mounting substrate has a problem that the connection strength cannot be so high because of the thickness of the printed electrodes.
【００１１】本発明は、前記問題点を解決するものであ
る。The present invention solves the above-mentioned problems.
【００１２】[0012]
【課題を解決するための手段】本発明は上記の課題に鑑
みてなされ、第１に、半導体装置裏面から連結体を取り
除き、接続片を個々に分離する事で解決するものであ
る。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is firstly solved by removing a connecting body from the back surface of a semiconductor device and separating connection pieces individually.
【００１３】第２に、半導体チップを、アイランドに固
着し、前記アイランドと前記連結体を、吊りリードで一
体化する事で解決するものである。Second, the problem is solved by fixing a semiconductor chip to an island and integrating the island and the connecting body with a suspension lead.
【００１４】第３に、接続片を、半導体チップの４側辺
に近接して設け、吊りリードをアイランドの４コーナー
から延在する事で解決するものである。Third, the problem is solved by providing connecting pieces close to the four sides of the semiconductor chip and extending the suspension leads from the four corners of the island.
【００１５】第４に、アイランドを、半導体チップより
小さくする事で解決するものである。Fourth, the problem is solved by making the island smaller than the semiconductor chip.
【００１６】第５に、アイランドを省略し、吊りリード
はＸの形状で、このＸ形状の吊りリードの上に前記半導
体チップを固着する事で解決するものである。Fifthly, the problem is solved by omitting the island, forming the suspension leads in the shape of X, and fixing the semiconductor chip on the suspension leads having the X shape.
【００１７】第６に、接続片と樹脂封止体を、同一面を
成すことで解決するものである。Sixth, the problem is solved by forming the connection piece and the resin sealing body on the same surface.
【００１８】第７に、半導体チップを、フェイスアップ
で実装し、手段を金属細線から成すことで解決するもの
である。Seventh, the problem is solved by mounting the semiconductor chip face-up and forming the means by a thin metal wire.
【００１９】第８に、アイランド、前記連結体および前
記接続片を、所望の厚みのＣｕから成し、前記半導体チ
ップを、フェイスダウンで実装し、手段をロウ材から成
すことで解決するものである。Eighth, the problem is solved by forming the island, the connecting body and the connecting piece from Cu having a desired thickness, mounting the semiconductor chip face down, and forming the means from brazing material. is there.
【００２０】第９に、連結体を、ダイシングにより取り
除くことで解決するものである。Ninth, the problem is solved by removing the connected body by dicing.
【００２１】例えば、Ｃｕより成るフレームは、従来か
らリードフレーム技術として確立されており、また封止
も従来のトランスファーモールド技術で実現できる。従
って封止した後、たんに連結体をダイシングやエッチン
グ等で取り除けば実現でき、より安価で、チップサイズ
に近づいた半導体装置を実現できる。For example, a frame made of Cu is conventionally established as a lead frame technology, and sealing can be realized by a conventional transfer molding technology. Therefore, it can be realized by simply removing the connected body by dicing, etching, or the like after sealing, and a semiconductor device that is less expensive and that is close to the chip size can be realized.
【００２２】また連結体を取り除くことで、この取り除
いた領域の接続片は、厚み方向に側壁が露出され、この
露出した側壁がロウ材に濡れることで接着強度を向上さ
せることができる。By removing the connecting body, the connection piece in the removed area has its side wall exposed in the thickness direction, and the exposed side wall is wetted by the brazing material, so that the adhesive strength can be improved.
【００２３】また、リードフレームのリードを接続片に
変えることで実現で、且つ金属細線も従来のワイヤーボ
ンディングで実現できるため、信頼性も高く、製造も容
易である。In addition, the present invention can be realized by changing the lead of the lead frame into a connecting piece, and a thin metal wire can be realized by conventional wire bonding, so that the reliability is high and the manufacture is easy.
【００２４】またリードフレームを採用して、チップサ
イズの半導体装置が実現できる。A semiconductor device having a chip size can be realized by using a lead frame.
【００２５】更には、連結体をダイシングにより取り除
くことで、接続片の側辺には、凹凸ができ、ロウ材との
接着性が向上する。Further, by removing the connected body by dicing, irregularities are formed on the side of the connection piece, and the adhesion to the brazing material is improved.
【００２６】[0026]
【発明の実施の形態】次に、本発明の第１の実施形態に
ついて図１〜図４を参照して説明する。図１の構成部品
は、あたかも一般的なリードフレームであり、リードフ
レームの厚みを有した金属材料（例えばＣｕを主材料と
する）から成るフレームである。これは、箔でも良い。
この場合、取り扱いの面を考慮して、フレキシブルシー
トにサンドウィッチしても良い。これについては後述す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. The components shown in FIG. 1 are a general lead frame, which is a frame made of a metal material having a thickness of the lead frame (for example, Cu is a main material). This may be foil.
In this case, the flexible sheet may be sandwiched in consideration of handling. This will be described later.
【００２７】まずフレーム１０は、半導体チップが固着
されるアイランド１１がその中央に設けられ、各コーナ
ーからは、吊りリード１２を介して連結体Ｒがアイラン
ド１１を囲むように形成されている。この連結体Ｒに
は、アイランド１１に向かう第１の接続片１３が実質的
に等間隔で一体配置されている。また連結体Ｒから外に
向かい第２の接続片１４が設けられている。First, in the frame 10, an island 11 to which a semiconductor chip is fixed is provided at the center thereof, and a linking body R is formed from each corner via a suspension lead 12 so as to surround the island 11. In this connector R, first connection pieces 13 facing the island 11 are integrally arranged at substantially equal intervals. A second connecting piece 14 is provided outward from the connecting body R.
【００２８】この接続片は、通常のリードフレームのリ
ードに対応し、従来のリードフレームでは、リードが樹
脂封止体から露出するものである。しかしこの接続片１
３、１４は、図３の如く、樹脂封止体１７と面いちで切
断されるか、または０．１〜０．２ｍｍ程度突出され
る。この突出により、実装時、接続片１３、１４の側面
に半田フィレットを作るためである。切断の方法は、ダ
イシング、またはＴ／Ｆ（トリム・アンド・フォーミン
グ）等が考えられる。This connection piece corresponds to the lead of a normal lead frame. In the conventional lead frame, the lead is exposed from the resin sealing body. However, this connecting piece 1
As shown in FIG. 3, 3 and 14 are cut at the same level as the resin sealing body 17 or protrude by about 0.1 to 0.2 mm. This projection is used to form solder fillets on the side surfaces of the connection pieces 13 and 14 during mounting. As a cutting method, dicing, T / F (trim and forming), or the like can be considered.
【００２９】またこの接続片の数は、ＩＣのボンディン
グパッドパッド数により決まる。つまりパッド数が少な
ければ、第１の接続片１３…を採用すれば良く、更に
は、この接続片は、連結体の１側辺〜４側辺を任意に選
択して、この連結体Ｒと一体で設ければよい。また数が
多い場合は、更に第２の接続片１４…を採用すればよ
い。更にパッド数が多ければ、図１３のように外側にリ
ング状に第３の接続片２２を設ければ良い。接続片のサ
イズにもよるが、連結体Ｒの外側に更に吊りリード１２
を介して別の連結体を形成し、アイランドに向いた接続
片、外側に向いた接続片を設ければ、接続片の数を増加
できる。The number of connection pieces is determined by the number of bonding pads of the IC. In other words, if the number of pads is small, the first connection pieces 13 may be employed, and the connection pieces may be arbitrarily selected from the first side to the fourth side of the connected body to be connected to the connected body R. What is necessary is just to provide integrally. If the number is large, the second connection pieces 14 may be further employed. If the number of pads is further increased, the third connection piece 22 may be provided on the outside in a ring shape as shown in FIG. Although it depends on the size of the connection piece, the suspension lead 12 is further provided outside the connection body R.
If another connecting member is formed through the connecting member and the connecting piece facing the island and the connecting piece facing the outside are provided, the number of connecting pieces can be increased.
【００３０】つまり接続片は、アイランド１１を囲むよ
うに第１の接続片郡１３…、第２の接続片郡１４…、…
が形成された形となる。That is, the connection pieces are divided into first connection piece groups 13, second connection piece groups 14,.
Is formed.
【００３１】続いて、図２に示すように、アイランド１
１には固着材を介して半導体チップ１５が固着される。
フレーム１０は、例えばＣｕを主材料とする金属でなる
ため、固着材としては半田等のロウ材で成るが、銀ペー
スト等のペースト材、接着剤でも良い。そして半導体チ
ップ１５の表面に露出されたボンディングパッドから接
続片１３、１４まで金属細線１６を介して接続される。
この金属細線１６は、Ａｕ、ＣｕまたはＡｌ等からな
り、通常はワイヤーボンディングで実現される。図２で
示したように、ＩＣのボンディングパッド数が多いた
め、第１の接続片１３…と第２の接続片１４…は、連結
体Ｒの側辺を中心に交互に突出して形成されている。別
の表現をすれば、隣り合う２つの第１の接続片１３、１
３の間に第２の接続片１４が入り、連結体Ｒを中心に所
定ピッチで左右に交互に飛び出している。この構造を採
用することにより金属細線のショート防止を実現してい
る。Subsequently, as shown in FIG.
The semiconductor chip 15 is fixed to 1 via a fixing material.
The frame 10 is made of, for example, a metal containing Cu as a main material. Therefore, the fixing material is made of a brazing material such as solder, but may be a paste material such as a silver paste or an adhesive. Then, the bonding pads exposed on the surface of the semiconductor chip 15 to the connection pieces 13 and 14 are connected via the thin metal wires 16.
The thin metal wires 16 are made of Au, Cu, Al, or the like, and are usually realized by wire bonding. As shown in FIG. 2, since the number of bonding pads of the IC is large, the first connection pieces 13 and the second connection pieces 14 are formed so as to protrude alternately around the side of the connector R. I have. In other words, two adjacent first connection pieces 13, 1
3, the second connecting piece 14 enters and alternately protrudes right and left at a predetermined pitch about the connected body R. By adopting this structure, short-circuit prevention of a thin metal wire is realized.
【００３２】続いて、図３の如く、樹脂封止体１７が設
けられる。この樹脂封止体１７は、一例としてトランス
ファーモールド、インジェクションモールド等で実現で
きる。但し、接続片１３、１４の裏面は、樹脂封止体１
７と同一面を成すか、あるいは樹脂封止体１７よりも若
干突出して設けられる。またこの際、アイランドの絶縁
を考慮する場合は、図３右図で見れば、アイランド１１
が接続片に対して若干上に押し上げられ、完全に埋め込
まれていても良い。Subsequently, as shown in FIG. 3, a resin sealing body 17 is provided. This resin sealing body 17 can be realized by transfer molding, injection molding, or the like, for example. However, the back surfaces of the connection pieces 13 and 14 are
7 are provided on the same plane as or slightly protruded from the resin sealing body 17. At this time, when considering island insulation, the island 11 can be seen from the right diagram of FIG.
May be slightly lifted up with respect to the connection piece and may be completely embedded.
【００３３】更に、図４で第１の接続片１３…、第２の
接続片１４…を個々に分離する。図４では、半導体装置
１８の裏面を示したものであり、ここでは第１の接続片
１３…、第２の接続片１４…、吊りリード１２およびア
イランド１１の裏面が露出している状態を示し、ハッチ
ングで示す所が除去領域と成っている。Further, in FIG. 4, the first connecting pieces 13 and the second connecting pieces 14 are individually separated. FIG. 4 shows the back surface of the semiconductor device 18, in which the first connection pieces 13, the second connection pieces 14, the suspension leads 12 and the back surface of the island 11 are exposed. And the hatched area is the removal area.
【００３４】ここでは連結体Ｒを取り除くことで接続片
１３…、１４…を個々に分離している。しかし本フレー
ムは、フレーム単位をマトリックス状に形成しているの
で、予定のチップパッケージ側辺で接続片が切断され
る。Here, the connection pieces 13..., 14. However, in the present frame, since the frame units are formed in a matrix, the connection pieces are cut at the side of the intended chip package.
【００３５】分離の簡単な方法として、ここではハッチ
ングで示す方向に、ハッチングで示すブレード幅のダイ
シングを施している。As a simple method of separation, here, dicing is performed in the direction indicated by hatching with a blade width indicated by hatching.
【００３６】このダイシングでは、フレーム１０の厚み
より若干深い溝を形成すれば簡単に分離でき、また少し
でも連結体Ｒが残るとショートの原因となるため、連結
体Ｒの幅よりも広い幅で除かれている。また他の除去方
法として、エッチングが考えられる。第２の接続片１４
は、樹脂封止体端まで、もしくは０．１〜０．２ｍｍ出
した位置で切断する。切断方法は、従来のＴ／Ｆまたは
連結体Ｒを切断するのと同じダイシングで行う。In this dicing, if a groove slightly deeper than the thickness of the frame 10 is formed, it can be easily separated, and even if the connecting body R remains even a little, it may cause a short circuit. Has been removed. As another removal method, etching can be considered. Second connection piece 14
Is cut to the end of the resin sealing body or at a position protruding from 0.1 to 0.2 mm. The cutting method is the same dicing as that for cutting the conventional T / F or the linked body R.
【００３７】生産性を考慮するなら、図１１、図１４お
よび図１５のように、マトリックス状に半導体チップ１
５が実装できるフレーム１０を用意し、まとめてダイシ
ングすればよい。この方法は、後述する。If the productivity is taken into consideration, the semiconductor chips 1 are arranged in a matrix as shown in FIGS.
A frame 10 on which the frame 5 can be mounted may be prepared and dicing may be performed collectively. This method will be described later.
【００３８】以上、本発明は、安価なフレーム１０を採
用し、最後にダイシング等で連結体Ｒを取り除けば、樹
脂封止体１７の裏面には、チップの側辺に接続片から成
る電極が形成されることになる。この接続片は、従来の
リードフレームを採用したパッケージと比較して、リー
ドに相当する接続片が短く、また外部に露出しない分全
体のサイズを小さくすることができる。As described above, the present invention employs an inexpensive frame 10 and finally removes the connecting member R by dicing or the like. Will be formed. As compared with a package using a conventional lead frame, the connecting piece is shorter than the connecting piece corresponding to the lead, and the entire size can be reduced because the connecting piece is not exposed to the outside.
【００３９】また接続片のサイズは、金属細線がボンデ
イングできるさいずであれば良いので、そのサイズも小
さくできる。また連結体Ｒの幅は、ダイシングブレード
のサイズおよび精度で決まるが、最近のダイシング装置
はブレードも薄く、非常に高精度であるため、前記幅も
狭くできる。従って半導体装置としてサイズの小さいも
のが簡単に実現できる。The size of the connecting piece may be any size as long as the thin metal wire can be bonded, so that the size can be reduced. Further, the width of the connector R is determined by the size and accuracy of the dicing blade. However, since recent dicing apparatuses have thin blades and extremely high accuracy, the width can be reduced. Therefore, a small-sized semiconductor device can be easily realized.
【００４０】またハッチングで示した溝には、接続片１
３、１４の切断面が露出される。このまま実装基板に半
田等のロウ材で固着した場合、この切断面がロウ材が濡
れてフィレットが形成されるため、接着強度も増強す
る。またダイシングでは、その切断面に細かい筋が形成
されるためロウ材との食いつきも向上する。The connecting pieces 1 are inserted into the grooves indicated by hatching.
The cut surfaces 3 and 14 are exposed. If the brazing material such as solder is fixed to the mounting board as it is, the cut surface wets the brazing material to form a fillet, so that the bonding strength is also enhanced. In the dicing, fine streaks are formed on the cut surface, so that the biting with the brazing material is also improved.
【００４１】一方、ダイシングにより形成される溝は、
別途樹脂で埋めても良い。特にダイシングにより形成さ
れた溝に於いて、半導体チップと連続している界面は、
吊りリードである。そのため、耐湿性が考慮されて、ダ
イシング溝のコーナー部分に樹脂が塗布されても良い。
また全ての溝を埋めても良い。この時もダイシングによ
る筋が切断面に細かく形成されるの樹脂の喰い付きが良
い。On the other hand, the groove formed by dicing is
It may be separately filled with resin. In particular, in the groove formed by dicing, the interface continuous with the semiconductor chip is:
It is a hanging lead. Therefore, resin may be applied to corner portions of the dicing grooves in consideration of moisture resistance.
Also, all grooves may be filled. Also at this time, the streak due to the dicing is finely formed on the cut surface, so that the resin biting is good.
【００４２】溝を絶縁樹脂で埋める場合には、接続片の
裏面を樹脂封止体１７よりも突出させることで、接続片
１３、１４と実装基板とのロウ付け強度が増強する。突
出させることで露出した側面にはフィレットが形成さ
れ、ロウ材の固着性強度が増す。When the groove is filled with an insulating resin, the back surface of the connection piece is made to protrude from the resin sealing body 17 so that the brazing strength between the connection pieces 13 and 14 and the mounting board is enhanced. By projecting, a fillet is formed on the exposed side surface, and the bonding strength of the brazing material is increased.
【００４３】図５、図６は、図１のフレーム１０を単位
とし、この単位がマトリックス状に形成されたものを示
している。FIGS. 5 and 6 show the frame 10 of FIG. 1 as a unit, and this unit is formed in a matrix.
【００４４】図５は、図３のパッケージ後を示し、マト
リックス状に形成されたフレームの各アイランドには半
導体チップが固着され、金属細線が接続されている。そ
して樹脂封止体は、マトリックス状のフレーム全域に設
けられている。ここでアイランドは、チップよりも大き
く形成されているが、小さくても良い。FIG. 5 shows a state after the package shown in FIG. 3. A semiconductor chip is fixed to each island of the frame formed in a matrix and a thin metal wire is connected thereto. The resin sealing body is provided over the entire area of the matrix-shaped frame. Here, the island is formed larger than the chip, but may be smaller.
【００４５】そして図６の２種類の矢印で示した所で、
ダイシングが施され、接続片の分離および半導体装置と
してフレームからの分離が実現される。Then, at the places indicated by the two types of arrows in FIG.
Dicing is performed to achieve separation of the connection piece and separation from the frame as a semiconductor device.
【００４６】図４で説明したように、フレーム全域にあ
る連結体の部分がダイシングにより削り取られる。この
場所を図６では４本の小さい矢印で示した。そしてフレ
ームから半導体装置を分離するために、フルカットを行
う。この場所は、３本の大きい矢印で示した。As described with reference to FIG. 4, the portion of the connected body over the entire frame is removed by dicing. This location is indicated by four small arrows in FIG. Then, a full cut is performed to separate the semiconductor device from the frame. This location is indicated by three large arrows.
【００４７】本方法は、通常のトランスファーモールド
の如く、マトリックス状にキャビティーが構成されるよ
うに金型を作っても良い。しかし本発明は、図５のよう
に、金型は１つのキャビティーにし、端から端までのフ
レーム単位が全て一体で連続してモールド形成され、後
にダイシングして個々に分離されている。ダイシング
は、ハーフカットとフルカットの２タイプを採用し、接
続片の分離と半導体装置の分離をしている。金型にマト
リックス状にキャビティを形成するとなると、金型側に
はキャビティとキャビティとの間にスペースが必要とな
る。しかしダイシングでフルカットをするならば、図６
で示したフルカット領域（大きい矢印）の領域は、ブレ
ードの間隔ですむため、その分単位フレームの実装密度
を増やすことができる。In the present method, a mold may be formed such that cavities are formed in a matrix, as in a normal transfer mold. However, in the present invention, as shown in FIG. 5, the mold is formed into one cavity, and the frame units from one end to the other are all integrally and continuously molded, and subsequently separated by dicing. Dicing employs two types of half-cut and full-cut, and separates connection pieces and separates semiconductor devices. When cavities are formed in a matrix in a mold, a space is required between the cavities on the mold side. However, if you make a full cut by dicing,
Since the area of the full cut area (large arrow) indicated by requires only the blade interval, the mounting density of the unit frame can be increased accordingly.
【００４８】ここでアイランドは省略し、Ｘリードでも
良い。Here, the islands may be omitted and X leads may be used.
【００４９】また図４の符号Ｆは、樹脂封止体の角部ま
たはその近傍に位置し、吊りリード１２の幅よりも広く
形成した固定手段である。この部分は、ダイシングによ
り完全に分離されるので、ここでは歪み吸収手段として
活用している。Reference numeral F in FIG. 4 is a fixing means located at or near a corner of the resin sealing body and formed wider than the width of the suspension lead 12. Since this portion is completely separated by dicing, it is utilized here as a strain absorbing means.
【００５０】つまり樹脂封止体の歪みの加わる部分は、
図４の４コーナーである。そのためこのＦの部分に対応
する第２の固定手段を実装基板に設け、この固定手段Ｆ
と実装基板の第２の固定手段を、ロウ材、銀ペースト、
接着剤等で固定する。その結果、半田ボールや半田バン
プにクラックが発生するような大きな歪みが加わって
も、まず固定手段にその応力が加わり、これ以外の接続
部分に応力が加わらない構造となっている。具体的に
は、Ｆは、リードであり、実装基板の第２の固定手段も
Ｃｕを主材料とするパターンが形成され、その間を半田
付けされている。That is, the portion of the resin sealing body to which the strain is applied is:
These are four corners in FIG. Therefore, a second fixing means corresponding to the portion of F is provided on the mounting substrate, and the fixing means F
And the second fixing means of the mounting board, a brazing material, a silver paste,
Fix with an adhesive or the like. As a result, even if a large distortion that causes cracks is applied to the solder balls and the solder bumps, the stress is first applied to the fixing means, and no stress is applied to the other connection parts. Specifically, F is a lead, and the second fixing means of the mounting board is also formed with a pattern mainly composed of Cu and soldered between them.
【００５１】続いて、第２の実施の形態を図９、図１０
を参照しながら説明する。ここでは、半導体チップ１５
をフレームに対してフェイスダウンで実装し、チップサ
イズと同じサイズの半導体装置を提供している。Next, the second embodiment will be described with reference to FIGS.
This will be described with reference to FIG. Here, the semiconductor chip 15
Is mounted face down on the frame to provide a semiconductor device having the same size as the chip size.
【００５２】半導体チップ１５は、表面に半田バンプま
たは半田ボールが形成され、これが黒丸の所で示され、
接続片１３、１４と接続されている。図２では、フェイ
スアップのため、アイランドが必要となり、また吊りリ
ードも必要となったが、図９では、フェイスダウンで実
現されるため、２点差線で示すアイランド、吊りリード
を省略しても良い。また半田は、他のロウ材でよい。ま
た銀ペースト等の導電ペーストでも良い。The semiconductor chip 15 has solder bumps or solder balls formed on the surface, which are indicated by black circles.
The connection pieces 13 and 14 are connected. In FIG. 2, an island and a suspension lead are required for face-up, but in FIG. 9, the island and suspension lead indicated by a two-dot line are omitted because the island and suspension lead are realized in a face-down manner. good. The solder may be another brazing material. Further, a conductive paste such as a silver paste may be used.
【００５３】またチップが実装された後に、半導体チッ
プとフレームの間に樹脂が充填されても良い。After the chip is mounted, a resin may be filled between the semiconductor chip and the frame.
【００５４】図１０は、前図の裏面を示したものであ
り、やはり点線で示す部分の連結体Ｒをダイシング等で
削除し、接続片１３、１４を個々に分離している。アイ
ランド１１や吊りリード１２は、省略も可能なので点線
で示してある。FIG. 10 shows the back surface of the previous figure, in which the connecting body R, also indicated by the dotted line, is removed by dicing or the like, and the connecting pieces 13 and 14 are separated from each other. The islands 11 and the suspension leads 12 are indicated by dotted lines because they can be omitted.
【００５５】また本フレームは、マトリックス状に形成
され、第２の接続片１４が図６と同じようにフルカット
される。フルカットは、ダイシングやＴ／Ｆ等で良い。The frame is formed in a matrix, and the second connection piece 14 is fully cut as in FIG. The full cut may be performed by dicing or T / F.
【００５６】本構造は、図１１に示すようにウェハサイ
ズのＣＳＰに応用できる。This structure can be applied to a wafer-sized CSP as shown in FIG.
【００５７】つまりウェハ２０全面にマトリックス状の
ＩＣを形成した後、パッシベーション膜を介して半田バ
ンプや半田ボールを形成しておく。そしてこの上に、マ
トリックス状に構成されたフレーム２１を配置し、接続
片と接続する。That is, after a matrix-shaped IC is formed on the entire surface of the wafer 20, solder bumps and solder balls are formed via a passivation film. Then, a frame 21 configured in a matrix is arranged on this, and connected to the connection piece.
【００５８】その後、必要によりウェハとフレームとの
間に樹脂を充填し、図６のように連結体Ｒをダイシング
して接続片を個々に分離し、フレーム単位間に設けられ
た連結体ｒをフルカットして個々に分離する。Thereafter, a resin is filled between the wafer and the frame, if necessary, and the connecting pieces R are diced to separate the connecting pieces as shown in FIG. 6, and the connecting pieces r provided between the frame units are separated. Full cut and separate individually.
【００５９】ここで第１、第２の両実施例は、色々なフ
レームが採用できる。図１１は、図１２の如く、対向す
る２側辺に接続片１３が設けられ、これがマトリックス
状に成ったフレームである。また図１３の如く、アイラ
ンドを囲むように、第１の接続片１３…、第２の接続片
１４…、第３の接続片２２が設けられても良い。Here, in both the first and second embodiments, various frames can be adopted. FIG. 11 shows a frame in which connecting pieces 13 are provided on two opposite sides as shown in FIG. 13, a first connection piece 13, a second connection piece 14, and a third connection piece 22 may be provided so as to surround the island.
【００６０】一方、全実施例で用いられるフレームは、
フレキシブルシートにサンドウィッチされた金属箔を用
いても良い。この場合、接続ポイント（接続片、アイラ
ンド）を除いてサンドウィッチされる。On the other hand, the frame used in all the embodiments is
A metal foil sandwiched between flexible sheets may be used. In this case, sandwiching is performed except for connection points (connection pieces, islands).
【００６１】図１６、図１７は、第１の実施例、第２の
実施例の断面図である。接続片１３、１４は、サイズも
小さくダイシング時に剥がれる可能性があるため、接続
片から樹脂食いつき手段Ｔが設けられている。この食い
つき手段Ｔは、図４で説明すると、ダイシングラインと
一致しない接続片の３側辺のどれかに設けられ、更には
接続片の側面から突出して設けられ、樹脂で完全にカバ
ーされ、アンカー効果により固定される。このアンカー
効果により、連結体がダイシングで削られる時でも、接
続片は樹脂から剥がれることなく固定される。FIGS. 16 and 17 are cross-sectional views of the first and second embodiments. Since the connection pieces 13 and 14 are small in size and may be peeled off during dicing, a resin biting means T is provided from the connection piece. 4, the biting means T is provided on any of the three sides of the connecting piece that does not coincide with the dicing line, and is further provided so as to protrude from the side face of the connecting piece, and is completely covered with the resin. Fixed by effect. Due to this anchor effect, even when the connecting body is cut by dicing, the connecting piece is fixed without peeling off from the resin.
【００６２】また図１６では、半導体チップ１５とフレ
ームとの間には所定の間隔が設けられてあるため、接続
片１３の一部は、半導体チップ１５の下に配置できる。
これにより接続片の配置領域全域をシュリンクでき、全
体のサイズを小さくすることができる。In FIG. 16, since a predetermined distance is provided between the semiconductor chip 15 and the frame, a part of the connection piece 13 can be arranged below the semiconductor chip 15.
As a result, the entire arrangement region of the connection pieces can be shrunk, and the overall size can be reduced.
【００６３】[0063]
【発明の効果】本発明によれば、金属から成るフレーム
を採用し、封止された後でフレームの一構成要素である
連結体を取り除くことで、接続片を個々に分離できる。
また接続片のサイズは、金属細線を接続できるサイズで
よく、全体としての半導体装置のサイズを小さくするこ
とができる。According to the present invention, the connection pieces can be individually separated by adopting a frame made of metal and removing the connecting body which is one component of the frame after the frame is sealed.
Further, the size of the connection piece may be a size capable of connecting a thin metal wire, and the size of the semiconductor device as a whole can be reduced.
【００６４】またフレームを樹脂に埋め込み、封止体の
裏面に接続片を露出させるので、従来のようにセラミッ
ク基板採用することなく実現できる。従ってセラミック
基板を採用した従来の半導体装置に比べコストを下げら
れる。Further, since the connection piece is exposed on the back surface of the sealing body by embedding the frame in the resin, it can be realized without using a ceramic substrate as in the conventional case. Therefore, the cost can be reduced as compared with a conventional semiconductor device using a ceramic substrate.
【００６５】またフレームにフェイスダウンするタイプ
では、チップサイズの半導体装置を実現できる。In the type in which the semiconductor device is face-down to the frame, a semiconductor device having a chip size can be realized.
【００６６】またダイシングで連結体を取り除くので、
この領域に露出する接続片の側面をロウ材の接続領域と
して活用でき、実装基板との接続強度を増強できる。Also, since the connected body is removed by dicing,
The side surface of the connection piece exposed in this region can be used as a connection region for the brazing material, and the connection strength with the mounting board can be enhanced.
【００６７】また連結体は、ダイシングで簡単に取り除
けるので、工程も簡略化できる。Further, since the connected body can be easily removed by dicing, the process can be simplified.
【図１】 本発明の第１の実施形態に係る半導体装置の
製造方法を説明する図である。FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【図２】 本発明の第１の実施形態に係る半導体装置の
製造方法を説明する図である。FIG. 2 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図３】 本発明の第１の実施形態に係る半導体装置の
製造方法を説明する図である。FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図４】 本発明の第１の実施形態に係る半導体装置の
製造方法を説明する図である。FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図５】 図１の単位フレームをマトリックス状に形成
したときの図である。5 is a diagram when the unit frames of FIG. 1 are formed in a matrix.
【図６】 図５を個々に分離するときの分離方法を説明
する図である。FIG. 6 is a diagram illustrating a separation method when FIG. 5 is separated individually.
【図７】 従来の半導体装置の製造方法を説明する図で
ある。FIG. 7 is a diagram illustrating a conventional method of manufacturing a semiconductor device.
【図８】 従来の半導体装置の製造方法を説明する図で
ある。FIG. 8 is a diagram illustrating a conventional method of manufacturing a semiconductor device.
【図９】 第２の実施の形態に係る半導体装置の製造方
法を説明する図である。FIG. 9 is a diagram illustrating a method of manufacturing a semiconductor device according to a second embodiment.
【図１０】 第２の実施の形態に係る半導体装置の製造
方法を説明する図である。FIG. 10 is a diagram illustrating a method for manufacturing the semiconductor device according to the second embodiment.
【図１１】 マトリックス状のフレームの説明をする図
である。FIG. 11 is a diagram illustrating a matrix frame.
【図１２】 フレームの説明をする図である。FIG. 12 is a diagram illustrating a frame.
【図１３】 フレームの説明をする図である。FIG. 13 is a diagram illustrating a frame.
【図１４】 フレームの説明をする図である。FIG. 14 is a diagram illustrating a frame.
【図１５】 フレームの説明をする図である。FIG. 15 is a diagram illustrating a frame.
【図１６】 第１の実施の形態に於いて、接続片に食い
つき手段を設けた図である。FIG. 16 is a view showing a connection piece provided with a biting means in the first embodiment.
【図１７】 第１の実施の形態に於いて、接続片に食い
つき手段を設けた図である。FIG. 17 is a view showing a connection piece provided with a biting means in the first embodiment.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/12 Ｈ０１Ｌ 21/78 Ｑ 23/28 23/12 Ｌ Ｆターム(参考） 4M109 AA01 BA01 CA04 CA21 DA04 DA07 DA10 DB02 DB04 FA01 5F044 AA01 GG03 LL01 QQ01 RR18 5F061 AA01 BA01 CA04 CA21 CB13 DD12 5F067 AA01 AB04 BA02 BA03 BB15 BC12 BD05 BE09 BE10 DE01 DF01 DF20 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 H01L 21/78 Q 23/28 23/12 L F term (Reference) 4M109 AA01 BA01 CA04 CA21 DA04 DA07 DA10 DB02 DB04 FA01 5F044 AA01 GG03 LL01 QQ01 RR18 5F061 AA01 BA01 CA04 CA21 CB13 DD12 5F067 AA01 AB04 BA02 BA03 BB15 BC12 BD05 BE09 BE10 DE01 DF01 DF20
Claims (9)
して設けられた複数の接続片と、前記接続片を一体化す
る連結体と、前記半導体チップと前記接続片を接続する
手段と、前記接続片、連結体および手段を封止する樹脂
封止体とを備えた半導体装置であり、 前記半導体装置裏面から前記連結体を取り除くことで前
記接続片を個々に分離した事を特徴とする半導体装置。A plurality of connecting pieces provided in proximity to at least one side of the semiconductor chip; a connecting body for integrating the connecting pieces; a means for connecting the semiconductor chip to the connecting pieces; A semiconductor device, comprising: a connection piece, a connection body, and a resin sealing body for sealing means, wherein the connection piece is individually separated by removing the connection body from the back surface of the semiconductor device. apparatus.
され、前記アイランドと前記連結体は、吊りリードで一
体化されている請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor chip is fixed to an island, and the island and the connecting body are integrated by a suspension lead.
辺に近接して設けられ、前記吊りリードは、前記アイラ
ンドの４コーナーから延在されている請求項２に記載の
半導体装置。3. The semiconductor device according to claim 2, wherein the connection pieces are provided near four sides of the semiconductor chip, and the suspension leads extend from four corners of the island.
り小さい請求項３に記載の半導体装置。4. The semiconductor device according to claim 3, wherein said island is smaller than said semiconductor chip.
リードはＸの形状で、このＸ形状の吊りリードの上に前
記半導体チップが固着される請求項３に記載の半導体装
置。5. The semiconductor device according to claim 3, wherein the island is omitted, the suspension lead has an X shape, and the semiconductor chip is fixed on the X-shaped suspension lead.
を成す請求項１、請求項２、請求項３、請求項４または
請求項５に記載の半導体装置。6. The semiconductor device according to claim 1, wherein said connection piece and said resin sealing body form the same surface.
実装され、前記手段は金属細線から成る請求項１、請求
項２、請求項３、請求項４、請求項５または請求項６に
記載の半導体装置。7. The semiconductor according to claim 1, wherein said semiconductor chip is mounted face-up, and said means comprises a thin metal wire. apparatus.
接続片は、所望の厚みのＣｕから成り、前記半導体チッ
プは、フェイスダウンで実装され、前記手段はロウ材か
ら成る請求項１、請求項２、請求項３、請求項４、請求
項５または請求項６に記載の半導体装置。8. The semiconductor device according to claim 1, wherein said island, said connecting body and said connecting piece are made of Cu having a desired thickness, said semiconductor chip is mounted face down, and said means is made of brazing material. 7. The semiconductor device according to claim 3, 4, 5, 5, or 6.
かれる請求項１、請求項２、請求項３、請求項４、請求
項５、請求項６、請求項７または請求項８に記載の半導
体装置。9. The semiconductor device according to claim 1, wherein said connected body is removed by dicing. .
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08925199A JP3976441B2 (en) | 1999-03-30 | 1999-03-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08925199A JP3976441B2 (en) | 1999-03-30 | 1999-03-30 | Semiconductor device |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007073279A Division JP4531073B2 (en) | 2007-03-20 | 2007-03-20 | Semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2000286375A true JP2000286375A (en) | 2000-10-13 |
| JP3976441B2 JP3976441B2 (en) | 2007-09-19 |
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ID=13965550
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|---|---|---|---|
| JP08925199A Expired - Fee Related JP3976441B2 (en) | 1999-03-30 | 1999-03-30 | Semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005022967A1 (en) * | 2003-08-29 | 2005-03-10 | Minowa Koa Inc. | Electronic part manufacturing method |
| US7170149B2 (en) | 2001-04-13 | 2007-01-30 | Yamaha Corporation | Semiconductor device and package, and method of manufacture therefor |
| US7192808B2 (en) | 2003-02-21 | 2007-03-20 | Yamaha Corporation | Semiconductor device having a lead frame smaller than a semiconductor chip and manufacturing method therefor |
| JP2007208283A (en) * | 2007-03-20 | 2007-08-16 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2010040595A (en) * | 2008-07-31 | 2010-02-18 | Mitsui High Tec Inc | Lead frame and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
| JP2016034011A (en) * | 2014-02-21 | 2016-03-10 | 大日本印刷株式会社 | Lead frame and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
-
1999
- 1999-03-30 JP JP08925199A patent/JP3976441B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7170149B2 (en) | 2001-04-13 | 2007-01-30 | Yamaha Corporation | Semiconductor device and package, and method of manufacture therefor |
| US7554182B2 (en) | 2001-04-13 | 2009-06-30 | Yamaha Corporation | Semiconductor device and package, and method of manufacturer therefor |
| US7192808B2 (en) | 2003-02-21 | 2007-03-20 | Yamaha Corporation | Semiconductor device having a lead frame smaller than a semiconductor chip and manufacturing method therefor |
| WO2005022967A1 (en) * | 2003-08-29 | 2005-03-10 | Minowa Koa Inc. | Electronic part manufacturing method |
| US7604833B2 (en) | 2003-08-29 | 2009-10-20 | Koa Corporation | Electronic part manufacturing method |
| JP2007208283A (en) * | 2007-03-20 | 2007-08-16 | Sanyo Electric Co Ltd | Semiconductor device |
| JP4531073B2 (en) * | 2007-03-20 | 2010-08-25 | 三洋電機株式会社 | Semiconductor device |
| JP2010040595A (en) * | 2008-07-31 | 2010-02-18 | Mitsui High Tec Inc | Lead frame and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
| JP2016034011A (en) * | 2014-02-21 | 2016-03-10 | 大日本印刷株式会社 | Lead frame and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
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