JP3965767B2 - Semiconductor chip substrate mounting structure - Google Patents

Semiconductor chip substrate mounting structure Download PDF

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Publication number
JP3965767B2
JP3965767B2 JP09325798A JP9325798A JP3965767B2 JP 3965767 B2 JP3965767 B2 JP 3965767B2 JP 09325798 A JP09325798 A JP 09325798A JP 9325798 A JP9325798 A JP 9325798A JP 3965767 B2 JP3965767 B2 JP 3965767B2
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Japan
Prior art keywords
wire
semiconductor chip
chip
hole
rows
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Expired - Fee Related
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JP09325798A
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Japanese (ja)
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JPH11297738A (en
Inventor
本田　　匡宏
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Denso Corp
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Denso Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップをワイヤボンディングにより配線基板に電気的に接続する半導体チップの基板実装構造に関し、特に構造の小型化に関する。
【０００２】
【従来の技術】
近年、機器の小型化に伴い、高密度実装に適しているベアチップ実装が盛んに検討されている。このベアチップ実装としては、図３及び図４に示す様な方式がある。ここで図３及び図４において、（ｂ）は（ａ）のＢ−Ｂ断面図である。
図３はワイヤボンディング方式であり、半導体チップ１の電極取出部と配線基板２との間をワイヤボンディングによるワイヤ３にて結線した後、接続部分の保護のため樹脂４により全体を封止する。
【０００３】
一方、図４はフリップチップ方式であり、半導体チップ１の電極取出部に半田で盛り上がらせて形成したバンプ５によって、半導体チップ１を配線基板２に接続する。また、上記両方式の他、配線フィルムを用いるＴＡＢ方式（テープキャリア方式）がある。
【０００４】
【発明が解決しようとする課題】
しかしながら、ワイヤボンディング方式の場合、一般的にＡｌパッド上にＡｕボールワイヤを超音波や熱の接合エネルギーの印加により圧着するという成熟した技術がある反面、図３の様に、半導体チップ１周辺から外部の配線基板２へボンディングが行われていることやワイヤ３のループ（ワイヤループ）の形成、封止樹脂４の関係等から、実装厚・実装面積に限界があり、チップサイズの実装構造とすることは不可能である。
【０００５】
また、フリップチップ方式は、各種実装法の中で最も実装面積が小さくかつ最も薄型実装が可能であるが、図４に示す様に、バンプ５の形成処理が必要なことや、半導体チップ（例えばＳｉチップ等）１と配線基板（例えばアルミナ基板）２との材料の熱膨張率の差に起因するバンプ５の熱疲労寿命が信頼性に支障をきたすなどの問題がある。さらには、この熱膨張率の差によってチップ１の大きさが制限されるだけでなく、配線基板２についてもＳｉ基板、セラミック基板あたりまでが実用化対象領域と考えられている。
【０００６】
また、ＴＡＢ方式に関しても、同様に、実装面積の限界、バンプ形成処理などが問題としてあげられる。
以上の点から本発明者は、比較的信頼性に優れ、材料の制約の少ないワイヤボンディング方式の実装構造を用いて、上記問題点を解決することとした。そこで、本発明の目的は、半導体チップを配線基板に搭載し、両者をワイヤボンディングで接続する実装構造において、チップの実装面積をチップサイズにまで縮小可能な構成を提供することとする。
【０００７】
【課題を解決するための手段】
本発明は、チップ配置の向き及びボンディングワイヤの接続方向という点に着目してなされたものである。すなわち、請求項１記載の発明においては、片面（２１）に電極取出部（２２）を有する半導体チップ（２０）と、片面（１１）側から他面（１２）側に貫通する貫通穴（１３）を有する配線基板（１０）とを備え、半導体チップ（２０）の片面（２１）と配線基板（１０）の片面（１１）とを、電極取出部（２２）と貫通穴（１３）とが対応するように対向配置して接着し、電極取出部（２２）と配線基板（１０）の他面（１２）とを、貫通穴（１３）を通してワイヤボンディングすることにより、半導体チップ（２０）と配線基板（１０）とを電気的に接続したことを特徴としている。また、本発明は、半導体チップ（２０）の片面（２１）には電極取出部（２２）が４列に配置されており、貫通穴（１３）は４列に配置された電極取出部（２２）の各々の２列に対応して２個設けられており、それぞれの貫通穴（１３）は２列に配置された電極取出部（２２）の配置スペースの大きさに対応して長方形状に開けられており、４列に配置された電極取出部（２２）、２個の貫通穴（１３）及びワイヤボンディングによって形成されたワイヤ（４０）は、樹脂（５０）により全体が一括して封止されていることを特徴としている。
【０００８】
本発明では、半導体チップ（２０）の電極取出部（２２）は、半導体チップ（２０）の中央部からワイヤボンディングにより配線基板（１０）の他面（１２）と接続されるため、半導体チップ（２０）の片面（２１）と対向する配線基板（１０）の片面（１１）には、半導体チップ（２０）のみの配置スペースがあればよい。従ってチップの実装面積をチップサイズにまで縮小可能とできる。
【０００９】
また、ワイヤボンディングによるワイヤ（４０）は、半導体チップ（２０）の電極取出部（２２）から配線基板（１０）の他面（１２）側に至るように形成され、貫通穴（１３）内部のスペースに形成されるため、ワイヤループが半導体チップ（２０）及び配線基板（１０）から突出する部分を小さく抑えることができ、実装厚さもチップサイズとできる。
【００１１】
なお、上記各手段の括弧内の符号は、後述する実施形態記載の具体的手段との対応関係を示すものである。
【００１２】
【発明の実施の形態】
以下、本発明を図に示す実施形態について説明する。
（第１の参考例）
図１に第１の参考例に係る半導体チップの基板実装構造を示す。図１において、１０は配線基板であり、図示しない配線部が形成されている。ここで、（ａ）は配線基板１０の表面（請求項でいう片面）１１からみた図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は配線基板１０の裏面（請求項でいう他面）１２からみた図である。
【００１３】
２０は、片面２１を拡散面としてデバイスが形成された半導体チップ（半導体素子）である。半導体チップ（以下チップという）２０は、片面２１の中央部に縦２列に配置された複数個のパッド（接合部）２２を有する。これらパッド２２は、上記デバイスと導通する電極取出部として構成されている。
また、配線基板１０には、表面１１から裏面１２に貫通するワイヤ通孔（貫通穴）１３が形成されている。ワイヤ通孔１３は、パッド２２の配置スペースの大きさに対応した長方形状に開けられており、後述のワイヤボンディングによるワイヤ４０が通るための孔となっている。
【００１４】
チップ２０は、片面２１を配線基板１０の表面１１に対向配置させた形（いわゆるフェースダウン）にて接着されており、パッド２２はワイヤ通孔１３に対応した位置にて、ワイヤ通孔１３から配線基板１０の裏面１２側を覗くようになっている。なお、チップ２０と配線基板１０とは、ダイボンディングされ、両面１１、２１間に介在する接着剤３０によって接着されている。
【００１５】
また、配線基板１０において、裏面１２のワイヤ通孔１３縁部には、パッド２２の数に対応した数の電極部１４が設けられており、これら電極部１４は、配線基板１０の上記配線部と導通されている。
そして、チップ２０の各パッド２２は各々、ワイヤ通孔１３を通るワイヤ４０によって、配線基板１０の裏面１２に設けられた各電極部１４に電気的に接続されている。これらワイヤ４０はＡｕ（金）線またはＡｌ（アルミニウム）線等からなり、通常のワイヤボンディングにより結線されている。
【００１６】
また、ワイヤ４０及びワイヤ４０の接続部の保護のため、パッド２２、ワイヤ通孔１３及びワイヤ４０は、モールド樹脂（樹脂）５０によって封止されている。第１の参考例の半導体チップの基板実装構造は、かかる構成を有するものであるが、本構造の製造方法について概略を述べておく。
【００１７】
パッド２２とワイヤ通孔１３とを対応させつつ、チップ２０の片面２１と配線基板１０の表面１１とを対向配置させ、これら両面１１、２１をダイボンディングする。続いて、パッド２２と電極部１４とを、各々Ａｕ線またはＡｌ線によりワイヤボンディングした後、ワイヤ４０及びワイヤ４０の接続部を樹脂封止する。こうして図１に示す半導体チップの基板実装構造となる。
【００１８】
ところで、上述のように、通常のワイヤボンディング方式の場合、ワイヤをチップの周りに引き出すことや封止樹脂の関係によりどうしても実装面積がチップサイズより大きくなってしまう。また、フリップチップにおいては実装面積がチップサイズではあるが、バンプ形成処理や、バンプの信頼性上の問題により基板種やチップの大きさが限られてしまう。
【００１９】
しかし、第１の参考例では、ワイヤ通孔１３を通して配線基板１０の裏面１２にワイヤボンディングが施してあるため、配線基板１０の表面１１における実装面積としては、チップ２０のみの配置スペースがあればよく、まさにチップサイズの面積実装が可能となる。また、配線基板１０の裏面１２に関してもチップ１０の中央部からワイヤボンディングが施してあるため、配線基板１２へのセカンドボンディングは表面１１のチップサイズ面積内に納まる。
【００２０】
また、第１の参考例では、配線基板１０の表面１１に、チップ２０からのワイヤボンディングが施されていないため、配線基板１０やチップ２０から突出するワイヤループを抑えることができ、また、フリップチップ方式のようなバンプもないため、実装厚もチップサイズとできる。また、第１の参考例では、信頼性の面に関しても、熱膨張率の差に起因する熱疲労寿命に問題を抱えているバンプ技術ではなく、成熟されたワイヤボンディング技術を用いているため問題はない。そのため、熱膨張率の影響は大きくなく、配線基板１０の種類やチップ２０のサイズも制限されることはない。
【００２１】
さらに、第１の参考例では、樹脂封止に関してもワイヤ通孔１３の真上から行うことができるのでワイヤ４０への負荷が少なく、ワイヤ流れによる（ＡｕまたはＡｌ線間の）短絡やワイヤ切断も押さえることができる。以上のように、第１の参考例では、中央縦２例にパッド２２が配列してあるチップ２０を、予めワイヤ通孔１３の開いている配線基板１０に、パッド２２を下向き（フェースダウン）に接着し、配線基板１０のワイヤ通孔１３を通して裏面１２から、電極部１４とパッド２２との両側にワイヤボンディングを行い、樹脂封止することで、本発明の目的を達成するものである。
【００２２】
ところで、上記図１では、配線基板１０のワイヤ通孔１３が１個、チップ２０のパッド２２が２列の場合におけるワイヤボンディングを例にとって説明をしたが、第１の参考例において、それらの数に制限はない。図２に、上記図１の図示例とは異なる３つの変形例を示す。なお、以下、主として上記図１と異なる部分について述べることとし、同一部分については、図中同一符号を付して説明を省略する。また、図２において符号は省略したが、ワイヤ４０の配線基板１０側接続部分は、上記図１と同様に電極部１４である。
【００２３】
（第２の参考例）：第２の参考例を図２（ａ）に示す。本例ではパッド２２を４列とし、ワイヤ通孔１３は１個であるが内周面に段部１３０を有することが異なる。チップ１０の中央部には４列のパッド２２が配置してあり、その配置スペースに対応した大きめのワイヤ通孔１３が設けられている。そのワイヤ通孔１３を通して、上記図１の構成と同様にワイヤボンディングが施され、樹脂封止されている。
【００２４】
この場合、ワイヤ４０の数が多くなったことにより、ワイヤループが大きくなってしまうので、配線基板１０において、ワイヤ通孔１３に段部１３０を設けることによりそれを防いでいる。従って、４列のパッドを配列し、段部１３０にて更にワイヤボンディング接続可能とすることにより、ボンディング数の増加が図れる。
【００２５】
（本実施形態）：図２（ｂ）に本実施形態を示す。本例ではパッド２２を４列とし、ワイヤ通孔１３を２個としたことが異なる。チップ２０には４列のパッド２２が配置してあるが、片側の２列と他側の２列との間に、ある程度間隔を設けてある。ワイヤ通孔１３は、パッド２２における各々の２列に対応した２つのワイヤ通孔１３ａ、１３ｂとからなる。各ワイヤ通孔１３ａ、１３ｂを通して、上記図１の構成と同様にワイヤボンディングが施され、樹脂封止されている。
【００２６】
従って、本例では、４列のパッド２２を配列し、ワイヤ通孔１３を２個としたことによりボンディング数の増加が図れ、更に、パッド２２をチップ２０の中央部に集める必要がなくなる。
（第３の参考例）：図２（ｃ）に第３の参考例を示す。本例は、上記第１の参考例および本実施形態を組み合わせたものであり、ボンディング数の大幅な改善（図では６列のパッド２２）ができる。
【００２７】
なお、以上述べた各図示例は、チップのパッド数、配置、ワイヤ通孔の数、配線基板の段部の組合せの代表的なものを示したが、これらの組み合わせによるチップサイズ内でのワイヤボンディング数の選択は自由であり、大幅な改善も可能である。また、チップ２０の片面２１はパッド２２が形成されていればよく、拡散面でなくともよい。
【図面の簡単な説明】
【図１】 本発明の第１の参考例に係る半導体チップの基板実装構造を示す図である。
【図２】 （ａ）及び（ｃ）は半導体チップの基板実装構造の参考例を示す図である、（ｂ）は半導体チップの基板実装構造の実施例を示す図である。
【図３】 従来のワイヤボンディング方式の実装構造を示す図である。
【図４】 従来のフリップチップ方式の実装構造を示す図である。
【符号の説明】
１０…配線基板、１１…配線基板の表面、１２…配線基板の裏面、１３…ワイヤ通孔（貫通穴）、２０…半導体チップ、２１…半導体チップの片面、２２…パッド、４０…ワイヤ、５０…モールド樹脂、１３０…段部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a substrate mounting structure of a semiconductor chip in which a semiconductor chip is electrically connected to a wiring substrate by wire bonding, and more particularly to downsizing of the structure.
[0002]
[Prior art]
In recent years, with the miniaturization of equipment, bare chip mounting suitable for high-density mounting has been actively studied. As this bare chip mounting, there are methods as shown in FIG. 3 and FIG. Here, in FIG. 3 and FIG. 4, (b) is a BB cross-sectional view of (a).
FIG. 3 shows a wire bonding method, in which the electrode extraction portion of the semiconductor chip 1 and the wiring substrate 2 are connected by a wire 3 by wire bonding, and then the whole is sealed with a resin 4 to protect the connection portion.
[0003]
On the other hand, FIG. 4 shows a flip-chip method, in which the semiconductor chip 1 is connected to the wiring substrate 2 by bumps 5 formed by raising the electrode extraction portion of the semiconductor chip 1 with solder. In addition to the above two methods, there is a TAB method (tape carrier method) using a wiring film.
[0004]
[Problems to be solved by the invention]
However, in the case of the wire bonding method, in general, there is a mature technique in which an Au ball wire is crimped onto an Al pad by applying ultrasonic or heat bonding energy. On the other hand, as shown in FIG. Due to the fact that bonding is performed to the external wiring board 2, the formation of the loop of the wire 3 (wire loop), the relationship of the sealing resin 4, etc., there is a limit to the mounting thickness and mounting area. It is impossible to do.
[0005]
In addition, the flip chip method has the smallest mounting area and the thinnest mounting among various mounting methods. However, as shown in FIG. 4, the bump 5 needs to be formed, and a semiconductor chip (for example, There is a problem that the thermal fatigue life of the bump 5 caused by the difference in thermal expansion coefficient between the material of the Si chip 1) and the wiring substrate (for example, alumina substrate) 2 impedes reliability. Further, not only the size of the chip 1 is limited by the difference in the coefficient of thermal expansion, but also the wiring substrate 2 is considered to be a practical application target region from the Si substrate to the ceramic substrate.
[0006]
Similarly, regarding the TAB method, the limit of the mounting area, bump formation processing, and the like are raised as problems.
From the above points, the present inventor decided to solve the above problems by using a wire bonding type mounting structure that is relatively excellent in reliability and has few material restrictions. Therefore, an object of the present invention is to provide a configuration in which a chip mounting area can be reduced to a chip size in a mounting structure in which a semiconductor chip is mounted on a wiring board and both are connected by wire bonding.
[0007]
[Means for Solving the Problems]
The present invention has been made paying attention to the orientation of the chip arrangement and the connection direction of the bonding wires. That is, in the first aspect of the invention, the semiconductor chip (20) having the electrode extraction portion (22) on one side (21) and the through hole (13) penetrating from the one side (11) side to the other side (12) side. ) Having a wiring board (10), one side (21) of the semiconductor chip (20) and one side (11) of the wiring board (10), an electrode extraction part (22) and a through hole (13). The semiconductor chip (20) and the semiconductor chip (20) are bonded to each other in a corresponding manner by wire bonding the electrode extraction part (22) and the other surface (12) of the wiring board (10) through the through hole (13). The wiring board (10) is electrically connected. Further, according to the present invention, the electrode extraction portions (22) are arranged in four rows on one surface (21) of the semiconductor chip (20), and the through holes (13) are arranged in four rows. 2) corresponding to each two rows, and each through hole (13) has a rectangular shape corresponding to the size of the arrangement space of the electrode extraction portions (22) arranged in two rows. The electrode extraction portions (22) arranged in four rows, the two through holes (13), and the wire (40) formed by wire bonding are collectively sealed with resin (50). It is characterized by being stopped.
[0008]
In the present invention, the electrode extraction part (22) of the semiconductor chip (20) is connected to the other surface (12) of the wiring substrate (10) by wire bonding from the central part of the semiconductor chip (20). On the one side (11) of the wiring board (10) facing the one side (21) of 20), it is sufficient if there is an arrangement space for only the semiconductor chip (20). Therefore, the chip mounting area can be reduced to the chip size.
[0009]
Further, the wire (40) by wire bonding is formed so as to extend from the electrode extraction part (22) of the semiconductor chip (20) to the other surface (12) side of the wiring substrate (10), and inside the through hole (13). Since the space is formed in the space, the portion where the wire loop protrudes from the semiconductor chip (20) and the wiring substrate (10) can be kept small, and the mounting thickness can also be set to the chip size.
[0011]
Contact name code in parentheses above means show the correspondence with specific means described embodiments to be described later.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.
(First reference example)
FIG. 1 shows a substrate mounting structure of a semiconductor chip according to a first reference example . In FIG. 1, reference numeral 10 denotes a wiring board on which a wiring portion (not shown) is formed. Here, (a) is a diagram viewed from the front surface (single side in the claims) 11 of the wiring board 10, (b) is a cross-sectional view taken along the line AA of (a), and (c) is the back surface of the wiring board 10 (claims). It is the figure seen from the other side 12).
[0013]
Reference numeral 20 denotes a semiconductor chip (semiconductor element) on which a device is formed with one side 21 as a diffusion surface. A semiconductor chip (hereinafter referred to as a chip) 20 has a plurality of pads (joining portions) 22 arranged in two vertical rows at the center of one surface 21. These pads 22 are configured as electrode extraction portions that are electrically connected to the device.
In addition, a wire through hole (through hole) 13 that penetrates from the front surface 11 to the back surface 12 is formed in the wiring substrate 10. The wire through-hole 13 is formed in a rectangular shape corresponding to the size of the arrangement space of the pad 22 and is a hole through which a wire 40 by wire bonding described later passes.
[0014]
The chip 20 is bonded in a form (so-called face down) in which one side 21 is disposed opposite to the surface 11 of the wiring substrate 10, and the pad 22 extends from the wire through hole 13 at a position corresponding to the wire through hole 13. The back surface 12 side of the wiring board 10 is looked into. The chip 20 and the wiring substrate 10 are die-bonded and bonded with an adhesive 30 interposed between both surfaces 11 and 21.
[0015]
Further, in the wiring substrate 10, the electrode portions 14 corresponding to the number of the pads 22 are provided at the edge of the wire through-hole 13 on the back surface 12, and these electrode portions 14 are provided on the wiring portion 10 of the wiring substrate 10. And is conducted.
Each pad 22 of the chip 20 is electrically connected to each electrode portion 14 provided on the back surface 12 of the wiring board 10 by a wire 40 passing through the wire through hole 13. These wires 40 are made of Au (gold) wire, Al (aluminum) wire, or the like, and are connected by ordinary wire bonding.
[0016]
In addition, the pad 22, the wire through hole 13, and the wire 40 are sealed with a mold resin (resin) 50 in order to protect the wire 40 and the connection portion of the wire 40. The substrate mounting structure of the semiconductor chip of the first reference example has such a configuration, but an outline of the manufacturing method of this structure will be described.
[0017]
While making the pad 22 and the wire through hole 13 correspond to each other, the one surface 21 of the chip 20 and the surface 11 of the wiring substrate 10 are arranged to face each other, and these both surfaces 11 and 21 are die-bonded. Subsequently, after the pads 22 and the electrode portions 14 are wire-bonded with Au wires or Al wires, the wires 40 and the connecting portions of the wires 40 are sealed with a resin. Thus, the substrate mounting structure of the semiconductor chip shown in FIG. 1 is obtained.
[0018]
Incidentally, as described above, in the case of the normal wire bonding method, the mounting area is inevitably larger than the chip size due to the wire drawn out around the chip and the relationship of the sealing resin. In flip chip, although the mounting area is the chip size, the substrate type and the chip size are limited due to bump formation processing and bump reliability problems.
[0019]
However, in the first reference example , since wire bonding is applied to the back surface 12 of the wiring board 10 through the wire through-holes 13, the mounting area on the front surface 11 of the wiring board 10 may be an arrangement space only for the chip 20. Well, it is possible to mount a chip-sized area. Further, since the back surface 12 of the wiring board 10 is also wire-bonded from the center of the chip 10, the second bonding to the wiring board 12 is within the chip size area of the front surface 11.
[0020]
Further, in the first reference example , since the wire bonding from the chip 20 is not performed on the surface 11 of the wiring substrate 10, wire loops protruding from the wiring substrate 10 and the chip 20 can be suppressed, and flipping is also possible. Since there is no bump as in the chip system, the mounting thickness can be set to the chip size. The first reference example also has a problem in terms of reliability because it uses a mature wire bonding technology rather than a bump technology that has a problem in thermal fatigue life due to a difference in thermal expansion coefficient. There is no. Therefore, the influence of the coefficient of thermal expansion is not great, and the type of the wiring board 10 and the size of the chip 20 are not limited.
[0021]
Furthermore, in the first reference example , the resin sealing can be performed from directly above the wire through-hole 13, so that the load on the wire 40 is small, and a short circuit or wire cutting (between Au or Al wires) due to the wire flow. Can also be suppressed. As described above, in the first reference example , the chip 20 in which the pads 22 are arranged in the two central vertical examples is placed on the wiring board 10 in which the wire through holes 13 are previously opened, and the pads 22 are faced down (face down). The object of the present invention is achieved by performing wire bonding on both sides of the electrode portion 14 and the pad 22 from the back surface 12 through the wire through hole 13 of the wiring substrate 10 and resin sealing.
[0022]
Incidentally, in FIG. 1 described above, the wire bonding in the case where there is one wire through hole 13 of the wiring substrate 10 and two rows of the pads 22 of the chip 20 has been described as an example . There is no limit. FIG. 2 shows three modified examples different from the example shown in FIG. In the following, portions different from those in FIG. 1 will be mainly described, and the same portions are denoted by the same reference numerals in the drawing and description thereof will be omitted. Further, although reference numerals are omitted in FIG. 2, the connection portion of the wire 40 on the wiring board 10 side is the electrode portion 14 as in FIG. 1.
[0023]
( Second Reference Example ): A second reference example is shown in FIG. In this example, the pads 22 are arranged in four rows, and the number of the wire through holes 13 is one, but a difference is that the step portion 130 is provided on the inner peripheral surface. Four rows of pads 22 are arranged at the center of the chip 10, and a large wire through hole 13 corresponding to the arrangement space is provided. Through the wire through hole 13, wire bonding is applied and resin-sealed in the same manner as in the configuration of FIG.
[0024]
In this case, since the number of the wires 40 increases and the wire loop becomes large, the step 130 is provided in the wire through hole 13 in the wiring board 10 to prevent this. Therefore, the number of bondings can be increased by arranging four rows of pads and further enabling wire bonding connection at the step portion 130.
[0025]
( Embodiment ): This embodiment is shown in FIG. In this example, the pads 22 are arranged in four rows, and the number of the wire through holes 13 is two. Although four rows of pads 22 are arranged on the chip 20, a certain amount of space is provided between two rows on one side and two rows on the other side. The wire through-hole 13 includes two wire through-holes 13 a and 13 b corresponding to the two rows in the pad 22. Through the wire through holes 13a and 13b, wire bonding is performed in the same manner as in the configuration of FIG. 1 and the resin is sealed.
[0026]
Therefore, in this example, the number of bondings can be increased by arranging four rows of pads 22 and two wire through holes 13, and it is not necessary to collect the pads 22 in the center of the chip 20.
( Third Reference Example ): A third reference example is shown in FIG. This example is a combination of the first reference example and this embodiment , and can greatly improve the number of bondings (six rows of pads 22 in the figure) .
[0027]
Each of the illustrated examples described above shows a typical combination of the number of pads of the chip, the arrangement, the number of wire through holes, and the stepped portion of the wiring board. However, the wire within the chip size by these combinations is shown. The number of bondings can be freely selected and can be greatly improved. Further, the one surface 21 of the chip 20 only needs to be provided with the pad 22 and may not be a diffusion surface.
[Brief description of the drawings]
FIG. 1 is a diagram showing a substrate mounting structure of a semiconductor chip according to a first reference example of the present invention.
FIGS. 2A and 2C are diagrams showing a reference example of a substrate mounting structure of a semiconductor chip, and FIG. 2B is a diagram showing an example of a substrate mounting structure of a semiconductor chip.
FIG. 3 is a view showing a mounting structure of a conventional wire bonding method.
FIG. 4 is a diagram showing a conventional flip-chip mounting structure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Wiring board, 11 ... Front surface of wiring board, 12 ... Back surface of wiring board, 13 ... Wire through-hole (through hole), 20 ... Semiconductor chip, 21 ... One side of semiconductor chip, 22 ... Pad, 40 ... Wire, 50 ... mold resin, 130 ... stepped part.

Claims (1)

片面（２１）に電極取出部（２２）を有する半導体チップ（２０）と、
片面（１１）側から他面（１２）側に貫通する貫通穴（１３）を有する配線基板（１０）とを備え、
前記半導体チップ（２０）の前記片面（２１）と前記配線基板（１０）の前記片面（１１）とは、前記電極取出部（２２）と前記貫通穴（１３）とが対応するように対向配置されて接着されており、
前記電極取出部（２２）と前記配線基板（１０）の前記他面（１２）とを、前記貫通穴（１３）を通してワイヤボンディングすることにより、前記半導体チップ（２０）と前記配線基板（１０）とが電気的に接続されている半導体チップの基板実装構造であって、
前記半導体チップ（２０）の前記片面（２１）には前記電極取出部（２２）が４列に配置されており、前記貫通穴（１３）は前記４列に配置された電極取出部（２２）の各々の２列に対応して２個設けられており、それぞれの前記貫通穴（１３）は前記２列に配置された前記電極取出部（２２）の配置スペースの大きさに対応して長方形状に開けられており、
前記４列に配置された電極取出部（２２）、前記２個の貫通穴（１３）及び前記ワイヤボンディングによって形成されたワイヤ（４０）は、樹脂（５０）により全体が一括して封止されていることを特徴とする半導体チップの基板実装構造。A semiconductor chip (20) having an electrode extraction part (22) on one side (21);
A wiring board (10) having a through hole (13) penetrating from one side (11) side to the other side (12) side,
The one side (21) of the semiconductor chip (20) and the one side (11) of the wiring board (10) are arranged to face each other so that the electrode extraction part (22) and the through hole (13) correspond to each other. Has been glued,
The semiconductor chip (20) and the wiring substrate (10) are bonded by wire bonding the electrode extraction part (22) and the other surface (12) of the wiring substrate (10) through the through hole (13). Is a substrate mounting structure of a semiconductor chip electrically connected to each other,
The electrode extraction portions (22) are arranged in four rows on the one surface (21) of the semiconductor chip (20), and the through holes (13) are arranged in the four rows of electrode extraction portions (22). The two through holes (13) are rectangular corresponding to the size of the arrangement space of the electrode extraction portions (22) arranged in the two rows. Open to the shape,
The electrode extraction portions (22) arranged in the four rows, the two through holes (13), and the wires (40) formed by the wire bonding are collectively sealed with a resin (50). A substrate mounting structure of a semiconductor chip, characterized in that
JP09325798A 1998-04-06 1998-04-06 Semiconductor chip substrate mounting structure Expired - Fee Related JP3965767B2 (en)

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