JPH1187556A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1187556A JPH1187556A JP24306397A JP24306397A JPH1187556A JP H1187556 A JPH1187556 A JP H1187556A JP 24306397 A JP24306397 A JP 24306397A JP 24306397 A JP24306397 A JP 24306397A JP H1187556 A JPH1187556 A JP H1187556A
- Authority
- JP
- Japan
- Prior art keywords
- wiring terminal
- terminal electrode
- solder ball
- semiconductor device
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、高信頼度のボールグリッドアレイ（ＢＧＡ：
Ｂall Ｇrid Ａrray）構造の半導体装置に適用して有効
な技術に関するものである。The present invention relates to a semiconductor device, and more particularly, to a highly reliable ball grid array (BGA).
The present invention relates to a technology which is effective when applied to a semiconductor device having a ball grid (Array) structure.
【０００２】[0002]
【従来の技術】従来、ビルドアップ法で製造したプラス
チック配線基板を用いたフリップチップ型ＢＧＡ基板の
配線端子電極（パッド）と半導体チップの外部電極（パ
ッド）とを半田ボールを介して電気的に接続し、前記半
導体チップとＢＧＡ基板との隙間を充填用樹脂によって
封止したものがある。2. Description of the Related Art Conventionally, wiring terminal electrodes (pads) of a flip-chip type BGA substrate using a plastic wiring substrate manufactured by a build-up method and external electrodes (pads) of a semiconductor chip are electrically connected via solder balls. In some cases, the gap between the semiconductor chip and the BGA substrate is sealed with a filling resin.
【０００３】前記ビルドアップ法で製造したプラスチッ
ク配線基板を用いたＢＧＡ基板に関する技術について
は、例えば、日経エレクトニクス、１９９５年４月１０
日号（ｎｏ６３３）の第９９頁〜第１０７頁に記載され
ている。[0003] Regarding the technology related to the BGA substrate using the plastic wiring substrate manufactured by the build-up method, see, for example, Nikkei Electronics, April 10, 1995.
No. 633, pp. 99-107.
【０００４】[0004]
【発明が解決しようとする課題】本発明者は、前記の従
来技術を検討した結果、以下の問題点を見いだした。前
述のＢＧＡ基板としてビルドアップ法で製造したプラス
チック配線基板を用いた場合、そのＢＧＡ基板の半田ボ
ール接続部の形状は、中央に凹部（窪み）ができたもの
になってしまう。この凹部は下層配線と接続するため必
然的に生じるものである。前記下層配線の中央の凹部の
上に半田ボールが接続されるため、その接続時に用いる
フラックスが凹部に溜まり、接続時に加わる熱でフラッ
クスが気化するが、半田ボールに封じ込められ、半田ボ
ールが溶融したときに半田ボール中にボイド（気泡）を
発生し、接続強度が低下し、接続信頼度が低減するとい
う問題がある。このため、半田ボール中にクラックを生
じ、ＢＧＡ基板と半導体チップとの電気的接続の信頼度
が低減する。The present inventor has found the following problems as a result of studying the above prior art. When a plastic wiring board manufactured by the build-up method is used as the above-mentioned BGA board, the shape of the solder ball connection portion of the BGA board is such that a concave portion (dent) is formed at the center. The recess is inevitably generated for connection with the lower wiring. Since the solder ball is connected to the central concave portion of the lower wiring, the flux used at the time of the connection accumulates in the concave portion, and the heat applied at the time of connection vaporizes the flux, but the solder ball is sealed and melted. Occasionally, voids (bubbles) are generated in the solder balls, resulting in a problem that connection strength is reduced and connection reliability is reduced. For this reason, cracks occur in the solder balls, and the reliability of the electrical connection between the BGA substrate and the semiconductor chip is reduced.
【０００５】特に、ＢＧＡ基板としてプラスチップ基板
を用いる場合には、前記半田ボール中にボイドがある
と、そのＢＧＡ基板と半導体チップとの熱膨張係数差に
より、歪みの影響を生けやすい。そのため、半田ボール
中にクラックを発生し、そのクラックがＢＧＡ基板と半
導体チップとの電気的接続部の信頼度に大きな影響を与
える。In particular, when a plus chip substrate is used as a BGA substrate, if there is a void in the solder ball, the effect of distortion is likely to occur due to the difference in the coefficient of thermal expansion between the BGA substrate and the semiconductor chip. For this reason, cracks occur in the solder balls, and the cracks greatly affect the reliability of the electrical connection between the BGA substrate and the semiconductor chip.
【０００６】本発明の目的は、ＢＧＡ基板の配線端子電
極と半導体チップの外部電極、もしくはＢＧＡ基板の配
線端子電極とプリント配線基板の配線端子電極とを半田
ボールを介して電気的に接続する接続部において、前記
半田ボール中にクラックを発生するのを低減することが
可能な技術を提供することにある。An object of the present invention is to provide a connection for electrically connecting a wiring terminal electrode of a BGA substrate and an external electrode of a semiconductor chip, or a wiring terminal electrode of a BGA substrate and a wiring terminal electrode of a printed wiring board via solder balls. It is another object of the present invention to provide a technique capable of reducing the occurrence of cracks in the solder balls.
【０００７】本発明の目的は、ビルドアップ法で製造し
たプラスチック配線基板を用いたフリップチップ型のＢ
ＧＡ基板の配線端子電極と半導体チップの外部電極とを
半田ボールを介して電気的に接続した半導体装置におい
て、前記半田ボール中にクラックが発生するのを低減す
ることが可能な技術を提供することにある。An object of the present invention is to provide a flip-chip type B using a plastic wiring board manufactured by a build-up method.
Provided is a technique capable of reducing occurrence of cracks in the solder balls in a semiconductor device in which wiring terminal electrodes of a GA substrate and external electrodes of a semiconductor chip are electrically connected via solder balls. It is in.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。 （１）フリップチップ型のＢＧＡ基板の配線端子電極と
半導体チップの外部電極とを半田ボールを介して電気的
に接続した半導体装置であって、前記ＢＧＡ基板の前記
配線端子電極の半田ボールとの接続部を平坦にしたもの
である。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows. (1) A semiconductor device in which a wiring terminal electrode of a flip-chip type BGA substrate and an external electrode of a semiconductor chip are electrically connected via a solder ball, wherein the wiring terminal electrode of the BGA substrate is connected to a solder ball of the wiring terminal electrode. The connection portion is flattened.
【００１０】（２）前記フリップチップ型のＢＧＡ基板
は、ビルドアップ法で製造したプラスチック配線基板を
用いたものである。(2) The flip-chip type BGA substrate uses a plastic wiring substrate manufactured by a build-up method.
【００１１】（３）前記配線端子電極を平坦な面上まで
延在させ、該配線端子電極と半田ボールとの接続部を平
坦な面上に配設したものである。(3) The wiring terminal electrode is extended to a flat surface, and a connection portion between the wiring terminal electrode and the solder ball is provided on the flat surface.
【００１２】（４）前記配線端子電極の半田ボールとの
接続部に生じる凹部を金属で埋め込み平坦としたもので
ある。(4) The recess formed in the connection portion of the wiring terminal electrode with the solder ball is buried with metal and flattened.
【００１３】前述した手段によれば、ＢＧＡ基板の配線
端子電極の半田ボールとの接続部を平坦にすることによ
り、半田ボールとの接続部にボイド（気泡）が生じない
ので、半田ボール中のクラックの発生を低減することが
できる。According to the above-mentioned means, since the connection portion between the wiring terminal electrode of the BGA substrate and the solder ball is flattened, no void (bubble) is generated at the connection portion with the solder ball. The occurrence of cracks can be reduced.
【００１４】以下、本発明について、図面を参照して実
施形態とともに詳細に説明する。なお、本実施形態を説
明するための全図において、同一機能を有するものは同
一符号を付け、その繰り返しの説明は省略する。Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings. In all of the drawings for describing the present embodiment, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.
【００１５】[0015]
（実施形態１）図１は本発明の実施形態１による半導体
装置の概略構成を説明するための断面模式図、図２は図
１の半導体装置の各部の寸法を説明するための半田ボー
ル側から見た平面図、図３は図１の要部の断面図であ
る。図１〜図３において、１は半導体チップ、２はビル
ドアップ法で製造したプラスチック配線基板を用いたフ
リップチップ型のＢＧＡ基板、３は半導体チップ１の半
田ボール、４は半導体チップ１の外部電極（パッド）、
５はＢＧＡ基板２の配線端子電極（パッド）、５Ａは配
線端子電極の延在部分、６は封止樹脂、７はＢＧＡ基板
２の配線、８は保護膜、９はＢＧＡ基板２の半田ボール
である。(Embodiment 1) FIG. 1 is a schematic cross-sectional view for explaining a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a view from the solder ball side for explaining dimensions of respective parts of the semiconductor device of FIG. FIG. 3 is a sectional view of a main part of FIG. 1 to 3, reference numeral 1 denotes a semiconductor chip, 2 denotes a flip-chip type BGA substrate using a plastic wiring board manufactured by a build-up method, 3 denotes solder balls of the semiconductor chip 1, and 4 denotes external electrodes of the semiconductor chip 1. (pad),
5 is a wiring terminal electrode (pad) of the BGA substrate 2, 5A is an extended portion of the wiring terminal electrode, 6 is a sealing resin, 7 is a wiring of the BGA substrate 2, 8 is a protective film, and 9 is a solder ball of the BGA substrate 2. It is.
【００１６】本実施形態１による半導体装置は、図１及
び図２に示すように、ビルドアップ法で製造したプラス
チック配線基板を用いたフリップチップ型のＢＧＡ基板
２の配線端子電極５を平坦な面上まで延在させ、この延
在させた配線端子電極５の部分５Ａと半導体チップ１の
外部電極４とを半田ボール３を介して電気的に接続し、
ＢＧＡ基板２と半導体チップ１との間を封止樹脂６で封
止したものである。In the semiconductor device according to the first embodiment, as shown in FIGS. 1 and 2, a wiring terminal electrode 5 of a flip-chip type BGA substrate 2 using a plastic wiring substrate manufactured by a build-up method is flat. Extending upward, electrically connecting the extended portion 5A of the wiring terminal electrode 5 and the external electrode 4 of the semiconductor chip 1 via the solder ball 3;
The space between the BGA substrate 2 and the semiconductor chip 1 is sealed with a sealing resin 6.
【００１７】前記半導体チップ１の大きさは、図２に示
すように、１５.７ｍｍ×１５.７ｍｍであり、半田ボー
ル３の配列間隔（ピッチ）は、それぞれＸ方向が０.４
ｍｍ、Ｙ方向が０.３ｍｍである。As shown in FIG. 2, the size of the semiconductor chip 1 is 15.7 mm × 15.7 mm, and the arrangement interval (pitch) of the solder balls 3 is 0.4 in the X direction.
mm, Y direction is 0.3 mm.
【００１８】前記ビルドアップ法で製造したプラスチッ
ク配線基板は、前述した文献等に記載されている公知の
ビルドアップ法を用いた製造法で作製されたものであ
る。前記配線端子電極５は、Ａｕ／Ｎｉ／Ｃｕの多層構
造になっており、図３に示すように、その配線端子電極
５の平坦な表面上まで延在させた長さは約１５０μｍで
あり、その面積は約１５０μｍ×１５０μｍ程度の大き
さである。The plastic wiring board manufactured by the build-up method is manufactured by a manufacturing method using a known build-up method described in the above-mentioned literature. The wiring terminal electrode 5 has a multilayer structure of Au / Ni / Cu, and as shown in FIG. 3, the length of the wiring terminal electrode 5 extending to a flat surface is about 150 μm. Its area is about 150 μm × 150 μm.
【００１９】前記配線端子電極５を平坦な面上まで延在
させる製造方法は、通常の方法で配線端子電極５を形成
する際に、配線端子電極のパターンマスクを変更するだ
けで容易に実現できる。The manufacturing method of extending the wiring terminal electrode 5 on a flat surface can be easily realized only by changing the pattern mask of the wiring terminal electrode when forming the wiring terminal electrode 5 by a usual method. .
【００２０】前記ＢＧＡ基板２の配線７上の配線端子電
極５の凹部部分は、エポキシ系樹脂からなる保護膜８で
埋め込まれている。The concave portion of the wiring terminal electrode 5 on the wiring 7 of the BGA substrate 2 is buried with a protective film 8 made of epoxy resin.
【００２１】前記半田ボール３の高さは約１００μｍ程
度あり、半導体チップ１の外部電極（パッド）４はＡｕ
／Ｎｉ／Ｃｒの多層構造になっており、その面積は約１
５０μｍ×１５０μｍ程度の大きさである。The height of the solder balls 3 is about 100 μm, and the external electrodes (pads) 4 of the semiconductor chip 1 are made of Au.
/ Ni / Cr multilayer structure with an area of about 1
The size is about 50 μm × 150 μm.
【００２２】本実施形態１による半導体装置によれば、
ＢＧＡ基板２の配線端子電極５を平坦な面上まで延在さ
せて半田ボール３との接続部を平坦にすることにより、
半田ボール３との接続部にボイドを生じさせないので、
半田ボール３中のクラックの発生を低減することができ
る。これにより、ＢＧＡ基板２の配線端子電極５と半導
体チップ１の外部電極４との接続部の電気的接続寿命の
低下を抑えることができる。According to the semiconductor device of the first embodiment,
By extending the wiring terminal electrode 5 of the BGA substrate 2 on a flat surface to flatten the connection portion with the solder ball 3,
Since no void is generated at the connection portion with the solder ball 3,
The occurrence of cracks in the solder balls 3 can be reduced. As a result, it is possible to suppress a reduction in the electrical connection life of the connection portion between the wiring terminal electrode 5 of the BGA substrate 2 and the external electrode 4 of the semiconductor chip 1.
【００２３】（実施の態２）図４は本発明の実施形態２
による半導体装置の要部の断面図である。本実施形態２
による半導体装置は、図４に示すように、配線端子電極
５の半田ボール３との接続部に生じる凹部部分を金属１
０で埋め込み平坦としたものである。前記凹部部分を金
属１０で埋め込み配線端子電極５を平坦にする手段は、
例えば、銅（Ｃｕ）メッキを行い、そのＣｕメッキ上に
Ｎｉメッキと金（Ａｕ）メッキを行って金（Ａｕ）表面
とする通常のメッキ法で実現できる。(Embodiment 2) FIG. 4 shows Embodiment 2 of the present invention.
1 is a cross-sectional view of a main part of a semiconductor device according to the first embodiment. Embodiment 2
As shown in FIG. 4, in the semiconductor device according to the present invention, a concave portion formed in a connection portion of the wiring terminal electrode 5 with the solder ball 3 is
0 indicates that the burying is flat. The means for embedding the concave portion with metal 10 and flattening the wiring terminal electrode 5 includes:
For example, it can be realized by a normal plating method in which copper (Cu) plating is performed, Ni plating and gold (Au) plating are performed on the Cu plating, and a gold (Au) surface is formed.
【００２４】本実施形態２による半導体装置によれば、
前記実施形態１のものより、半導体チップ１の外部電極
（パッド）を小さくすることができ、多ピン化に有利で
ある。According to the semiconductor device of the second embodiment,
The external electrodes (pads) of the semiconductor chip 1 can be smaller than those of the first embodiment, which is advantageous for increasing the number of pins.
【００２５】前記実施形態１，２では、フリップチップ
型のＢＧＡ基板２の配線端子電極５と半導体チップ１の
外部電極４とを半田ボール３を介して電気的に接続する
実施例について説明したが、本発明は、前述の説明から
わかるように、セラミックパッケージにおけるＢＧＡ基
板２の配線端子電極５と半導体チップ１の外部電極４と
を半田ボール３を介して電気的に接続する場合の接続部
にも適用できる。また、ＢＧＡ基板２とプリント配線基
板に半田ボールを介して電気的に接続する接続部にも適
用することができる。In the first and second embodiments, an example in which the wiring terminal electrodes 5 of the flip-chip type BGA substrate 2 and the external electrodes 4 of the semiconductor chip 1 are electrically connected via the solder balls 3 has been described. According to the present invention, as can be understood from the above description, the connection portion in the case where the wiring terminal electrode 5 of the BGA substrate 2 and the external electrode 4 of the semiconductor chip 1 are electrically connected via the solder ball 3 in the ceramic package. Can also be applied. Further, the present invention can also be applied to a connection portion that is electrically connected to the BGA substrate 2 and the printed wiring board via solder balls.
【００２６】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００２７】[0027]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。本発明によれば、基板の配線端子電極
と半導体チップの外部電極、もしくは基板の配線端子電
極とプリント配線そ板の端子電極とを半田ボールを介し
て電気的に接続する接続部において、ＢＧＡ基板の配線
端子電極の半田ボールとの接続部を平坦にすることによ
り、半田ボールとの接続部にボイド（気泡）が生じない
ので、半田ボール中のクラックの発生を低減することが
できる。これにより、ＢＧＡ基板の配線端子電極と半導
体チップの外部電極との接続部の電気的接続寿命の低下
を抑えることができる。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, a BGA substrate is provided at a connection portion for electrically connecting a wiring terminal electrode of a substrate and an external electrode of a semiconductor chip, or a wiring terminal electrode of a substrate and a terminal electrode of a printed wiring board via a solder ball. By flattening the connection portion of the wiring terminal electrode with the solder ball, voids (bubbles) are not generated at the connection portion with the solder ball, so that cracks in the solder ball can be reduced. As a result, it is possible to suppress a reduction in the electrical connection life of the connection portion between the wiring terminal electrode of the BGA substrate and the external electrode of the semiconductor chip.
【図１】本発明の実施形態１による半導体装置の概略構
成を説明するための断面模式図である。FIG. 1 is a schematic cross-sectional view for explaining a schematic configuration of a semiconductor device according to a first embodiment of the present invention.
【図２】図１の半導体装置の各部の寸法を説明するため
の半田ボール側から見た平面図である。FIG. 2 is a plan view seen from a solder ball side for explaining dimensions of respective parts of the semiconductor device of FIG. 1;
【図３】図１の要部の断面図である。FIG. 3 is a sectional view of a main part of FIG. 1;
【図４】本発明の実施形態２による半導体装置の要部の
断面図である。FIG. 4 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;
１…半導体チップ、２…ＢＧＡ基板、３…半導体チップ
の半田ボール、４…半導体チップの外部電極（パッ
ド）、５…ＢＧＡ基板の配線端子電極（パッド）、５Ａ
…配線端子電極の延在部分、６…封止樹脂、７…ＢＧＡ
基板の配線、８…保護膜、９…ＢＧＡ基板の半田ボー
ル、１０…金属メッキ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... BGA board, 3 ... Solder ball of semiconductor chip, 4 ... External electrode (pad) of semiconductor chip, 5 ... Wiring terminal electrode (pad) of BGA board, 5A
… Extended part of wiring terminal electrode, 6… encapsulation resin, 7… BGA
Wiring of the board, 8: protective film, 9: solder ball of BGA board, 10: metal plating.
Claims (4)
イ基板の配線端子電極と半導体チップの外部電極とを半
田ボールを介して電気的に接続した半導体装置であっ
て、前記ボールグリッドアレイ基板の配線端子電極の半
田ボールとの接続部を平坦にしたことを特徴とする半導
体装置。1. A semiconductor device in which wiring terminal electrodes of a flip-chip type ball grid array substrate and external electrodes of a semiconductor chip are electrically connected via solder balls, wherein the wiring terminal electrodes of the ball grid array substrate are provided. A connection portion between the semiconductor device and the solder ball is flattened.
イ基板は、ビルドアップ法で製造したプラスチック配線
基板を用いたものであることを特徴とする請求項１に記
載の半導体装置。2. The semiconductor device according to claim 1, wherein the flip-chip type ball grid array substrate uses a plastic wiring substrate manufactured by a build-up method.
させ、該配線端子電極と半田ボールとの接続部を平坦な
面上に配設したことを特徴とする請求項１又は２に記載
の半導体装置。3. The method according to claim 1, wherein the wiring terminal electrode extends to a flat surface, and a connection portion between the wiring terminal electrode and the solder ball is disposed on the flat surface. 13. The semiconductor device according to claim 1.
部に生じる凹部を金属で埋め込み平坦としたことを特徴
とする請求項１又は２に記載の半導体装置。4. The semiconductor device according to claim 1, wherein a recess formed in a connection portion of the wiring terminal electrode with the solder ball is buried with metal and flattened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24306397A JPH1187556A (en) | 1997-09-08 | 1997-09-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24306397A JPH1187556A (en) | 1997-09-08 | 1997-09-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187556A true JPH1187556A (en) | 1999-03-30 |
Family
ID=17098254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24306397A Pending JPH1187556A (en) | 1997-09-08 | 1997-09-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187556A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002134890A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| JP2002134889A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| JP2002134891A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| WO2002099743A1 (en) * | 2001-06-07 | 2002-12-12 | Sokymat S.A. | Ic connected to a winded isolated wire coil by flip-chip technology |
| JP2014225569A (en) * | 2013-05-16 | 2014-12-04 | ソニー株式会社 | Method for manufacturing mounting board and method for manufacturing electronic apparatus |
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| US9496236B2 (en) | 2010-12-10 | 2016-11-15 | Tessera, Inc. | Interconnect structure |
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-
1997
- 1997-09-08 JP JP24306397A patent/JPH1187556A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002134889A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| JP2002134891A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| JP4484350B2 (en) * | 2000-10-19 | 2010-06-16 | イビデン株式会社 | Method for manufacturing printed wiring board |
| JP4514308B2 (en) * | 2000-10-19 | 2010-07-28 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
| JP4514309B2 (en) * | 2000-10-19 | 2010-07-28 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
| JP2002134890A (en) * | 2000-10-19 | 2002-05-10 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
| WO2002099743A1 (en) * | 2001-06-07 | 2002-12-12 | Sokymat S.A. | Ic connected to a winded isolated wire coil by flip-chip technology |
| US9397063B2 (en) | 2010-07-27 | 2016-07-19 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9030001B2 (en) | 2010-07-27 | 2015-05-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
| US9496236B2 (en) | 2010-12-10 | 2016-11-15 | Tessera, Inc. | Interconnect structure |
| JP2014225569A (en) * | 2013-05-16 | 2014-12-04 | ソニー株式会社 | Method for manufacturing mounting board and method for manufacturing electronic apparatus |
| US11370047B2 (en) | 2013-05-16 | 2022-06-28 | Sony Semiconductor Solutions Corporation | Method of manufacturing mounting substrate and method of manufacturing electronic apparatus |
| US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US9818713B2 (en) | 2015-07-10 | 2017-11-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10535626B2 (en) | 2015-07-10 | 2020-01-14 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US10892246B2 (en) | 2015-07-10 | 2021-01-12 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
| US11710718B2 (en) | 2015-07-10 | 2023-07-25 | Adeia Semiconductor Technologies Llc | Structures and methods for low temperature bonding using nanoparticles |
| US11973056B2 (en) | 2016-10-27 | 2024-04-30 | Adeia Semiconductor Technologies Llc | Methods for low temperature bonding using nanoparticles |
| US12027487B2 (en) | 2016-10-27 | 2024-07-02 | Adeia Semiconductor Technologies Llc | Structures for low temperature bonding using nanoparticles |
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