JP4514308B2 - Manufacturing method of multilayer printed wiring board - Google Patents

Description

【００６２】
（式中、ｎは、２以上の整数を表す。）
【００６３】
【化２】

【００６４】
（式中、ｍは、２以上の整数を表す。また、Ｒ¹ 、Ｒ² は、メチレン基、エチレン基または−ＣＨ₂ −Ｏ−ＣＨ₂ −を表し、両者は同一であってもよいし、異なっていてもよい。）
【００６５】
また、上記化学式（１）で表される繰り返し単位を有する熱可塑性ポリフェニレンエーテル樹脂は、ベンゼン環にメチル基が結合した構造を有しているが、本発明で用いることのできるポリフェニレンエーテル樹脂としては、上記メチル基が、エチル基等の他のアルキル基等で置換された誘導体や、メチル基の水素がフッ素で置換された誘導体等であってもよい。
【００６６】
また、上記熱可塑性樹脂としては、例えば、ポリエーテルスルフォン、ポリスルフォン等が挙げられる。
また、熱硬化性樹脂と熱可塑性樹脂との複合体（樹脂複合体）としては、熱硬化性樹脂と熱可塑性樹脂とを含むものであれば特に限定されず、その具体例としては、例えば、粗化面形成用樹脂組成物等が挙げられる。
【００６７】
上記粗化面形成用樹脂組成物としては、例えば、酸、アルカリおよび酸化剤から選ばれる少なくとも１種からなる粗化液に対して難溶性の未硬化の耐熱性樹脂マトリックス中に、酸、アルカリおよび酸化剤から選ばれる少なくとも１種からなる粗化液に対して可溶性の物質が分散されたもの等が挙げられる。
なお、上記「難溶性」および「可溶性」という語は、同一の粗化液に同一時間浸漬した場合に、相対的に溶解速度の早いものを便宜上「可溶性」といい、相対的に溶解速度の遅いものを便宜上「難溶性」と呼ぶ。
【００６８】
上記耐熱性樹脂マトリックスとしては、層間樹脂絶縁層に上記粗化液を用いて粗化面を形成する際に、粗化面の形状を保持できるものが好ましく、例えば、熱硬化性樹脂、熱可塑性樹脂、これらの複合体等が挙げられる。また、感光性樹脂であってもよい。後述するバイアホール用開口を形成する工程において、露光現像処理により開口を形成することができるからである。
【００６９】
上記熱硬化性樹脂としては、例えば、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂、ポリオレフィン樹脂、フッ素樹脂等が挙げられる。また、上記熱硬化性樹脂を感光化する場合は、メタクリル酸やアクリル酸等を用い、熱硬化基を（メタ）アクリル化反応させる。特にエポキシ樹脂の（メタ）アクリレートが望ましい。さらに、１分子中に、２個以上のエポキシ基を有するエポキシ樹脂がより望ましい。上述の粗化面を形成することができるばかりでなく、耐熱性等にも優れているため、ヒートサイクル条件下においても、導体回路に応力の集中が発生せず、導体回路と層間樹脂絶縁層との間で剥離が発生しにくい。
【００７０】
上記熱可塑性樹脂としては、例えば、フェノキシ樹脂、ポリエーテルスルフォン、ポリスルフォン、ポリフェニレンスルフォン、ポリフェニレンサルファイド、ポリフェニルエーテル、ポリエーテルイミド等が挙げられる。これらは単独で用いてもよいし、２種以上併用してもよい。
【００７１】
上記酸、アルカリおよび酸化剤から選ばれる少なくとも１種からなる粗化液に対して可溶性の物質は、無機粒子、樹脂粒子、金属粒子、ゴム粒子、液相樹脂および液相ゴムから選ばれる少なくとも１種であることが望ましい。
【００７２】
上記無機粒子としては、例えば、アルミニウム化合物、カルシウム化合物、カリウム化合物、マグネシウム化合物、ケイ素化合物等が挙げられる。これらは単独で用いてもよいし、２種以上併用してもよい。
【００７３】
上記アルミニウム化合物としては、例えば、アルミナ、水酸化アルミニウム等が挙げられ、上記カルシウム化合物としては、例えば、炭酸カルシウム、水酸化カルシウム等が挙げられ、上記カリウム化合物としては、例えば、炭酸カリウム等が挙げられ、上記マグネシウム化合物としては、例えば、マグネシア、ドロマイト、塩基性炭酸マグネシウム、タルク等が挙げられ、上記ケイ素化合物としては、例えば、シリカ、ゼオライト等が挙げられる。これらは単独で用いてもよいし、２種以上併用してもよい。
【００７４】
上記アルミナ粒子は、ふっ酸で溶解除去することができ、炭酸カルシウムは塩酸で溶解除去することができる。また、ナトリウム含有シリカやドロマイトはアルカリ水溶液で溶解除去することができる。
【００７５】
上記樹脂粒子としては、例えば、熱硬化性樹脂、熱可塑性樹脂等からなるものが挙げられ、酸、アルカリおよび酸化剤から選ばれる少なくとも１種からなる粗化液に浸漬した場合に、上記耐熱性樹脂マトリックスよりも溶解速度の早いものであれば特に限定されず、具体的には、例えば、アミノ樹脂（メラミン樹脂、尿素樹脂、グアナミン樹脂等）、エポキシ樹脂、フェノール樹脂、フェノキシ樹脂、ポリイミド樹脂、ポリフェニレン樹脂、ポリオレフィン樹脂、フッ素樹脂、ビスマレイミド−トリアジン樹脂等が挙げられる。これらは、単独で用いてもよく、２種以上併用してもよい。
【００７６】
上記樹脂粒子は予め硬化処理されていることが必要である。硬化させておかないと上記樹脂粒子が樹脂マトリックスを溶解させる溶剤に溶解してしまうため、均一に混合されてしまい、酸や酸化剤で樹脂粒子のみを選択的に溶解除去することができないからである。
【００７７】
上記金属粒子としては、例えば、金、銀、銅、スズ、亜鉛、ステンレス、アルミニウム、ニッケル、鉄、鉛等が挙げられる。これらは、単独で用いてもよく、２種以上併用してもよい。
また、上記金属粒子は、絶縁性を確保するために、表層が樹脂等により被覆されていてもよい。
【００７８】
上記ゴム粒子としては、例えば、アクリロニトリル−ブタジエンゴム、ポリクロロプレンゴム、ポリイソプレンゴム、アクリルゴム、多硫系剛性ゴム、フッ素ゴム、ウレタンゴム、シリコーンゴム、ＡＢＳ樹脂等が挙げられる。
【００７９】
また、上記ゴム粒子として、例えば、ポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等を使用することもできる。
これらの可溶性の物質は、単独で用いてもよいし、２種以上併用してもよい。
【００８０】
上記液相樹脂としては、上記熱硬化性樹脂の未硬化溶液を使用することができ、このような液相樹脂の具体例としては、例えば、未硬化のエポキシオリゴマーとアミン系硬化剤の混合液等が挙げられる。
上記液相ゴムとしては、例えば、上記したポリブタジエンゴム、エポキシ変性、ウレタン変性、（メタ）アクリロニトリル変性等の各種変性ポリブタジエンゴム、カルボキシル基を含有した（メタ）アクリロニトリル・ブタジエンゴム等の未硬化溶液等を使用することができる。
【００８１】
上記液相樹脂や液相ゴムを用いて上記感光性樹脂組成物を調製する場合には、耐熱性樹脂マトリックスと可溶性の物質とが均一に相溶しない（つまり相分離するように）ように、これらの物質を選択する必要がある。
上記基準により選択された耐熱性樹脂マトリックスと可溶性の物質とを混合することにより、上記耐熱性樹脂マトリックスの「海」の中に液相樹脂または液相ゴムの「島」が分散している状態、または、液相樹脂または液相ゴムの「海」の中に、耐熱性樹脂マトリックスの「島」が分散している状態の感光性樹脂組成物を調製することができる。
【００８２】
（４）次に、その材料として熱硬化性樹脂や樹脂複合体を用いた層間樹脂絶縁層を形成する場合には、未硬化の樹脂絶縁層に硬化処理を施すとともに、バイアホール用開口を形成し、層間樹脂絶縁層とする。
上記バイアホール用開口は、レーザ処理により形成することが望ましい。上記レーザ処理は、上記硬化処理前に行ってもよいし、硬化処理後に行ってもよい。
また、感光性樹脂からなる層間樹脂絶縁層を形成した場合には、露光、現像処理を行うことにより、バイアホール用開口を設けてもよい。なお、この場合、露光、現像処理は、上記硬化処理前に行う。
【００８３】
また、その材料として熱可塑性樹脂を用いた層間樹脂絶縁層を形成する場合には、熱可塑性樹脂からなる樹脂層にレーザ処理によりバイアホール用開口を形成し、層間樹脂絶縁層とすることができる。
【００８４】
このとき、使用するレーザとしては、例えば、炭酸ガスレーザ、エキシマレーザ、ＵＶレーザ、ＹＡＧレーザ等が挙げられる。
これらのレーザは、形成するバイアホール用開口の形状等を考慮して使い分けてもよい。
【００８５】
上記バイアホール用開口を形成する場合、マスクを介して、ホログラム方式のエキシマレーザによるレーザ光照射することにより、一度に多数のバイアホール用開口を形成することができる。
また、短パルスの炭酸ガスレーザを用いて、バイアホール用開口を形成すると、開口内の樹脂残りが少なく、開口周縁の樹脂に対するダメージが小さい。
【００８６】
また、光学系レンズとマスクとを介してレーザ光を照射することにより、一度に多数のバイアホール用開口を形成することができる。
光学系レンズとマスクとを介することにより、同一強度で、かつ、照射角度が同一のレーザ光を複数の部分に同時に照射することができるからである。
【００８７】
上記マスクに形成された貫通孔は、レーザ光のスポット形状を真円にするために、真円であることが望ましく、上記貫通孔の径は、０．１〜２ｍｍ程度が望ましい。
また、上記炭酸ガスレーザを用いる場合、そのパルス間隔は、１０^-4〜１０^-8秒であることが望ましい。また、開口を形成するためのレーザを照射する時間は、１０〜５００μ秒であることが望ましい。
レーザ光にてバイアホール用開口を形成した場合、特に炭酸ガスレーザを用いた場合には、デスミア処理を行うことが望ましい。
【００８８】
また、上記した方法で形成する層間樹脂絶縁層の厚さは特に限定されないが、５〜５０μｍが望ましい。
また、上記バイアホール用開口の開口径は特に限定されないが、通常、４０〜２００μｍが望ましい。
【００８９】
また、層間樹脂絶縁層を形成した後、必要に応じて、該層間樹脂絶縁層と基板とを貫通する貫通孔を形成してもよい。該貫通孔は、ドリル加工やレーザ処理等を用いて形成すればよい。
このような貫通孔を形成した場合には、後工程で、層間樹脂絶縁層の表面に薄膜導体層を形成する際に、該貫通孔の壁面にも薄膜導体層を形成することにより、基板と層間樹脂絶縁層とを挟んだ２層の導体回路間は勿論のこと、この２層の導体回路と基板の両面に形成された２層の導体回路との計４層の導体回路間を電気的に接続するスルーホールを形成することができる。このようにして導体回路間を接続することにより、信号伝送距離を短くすることができるため、信号遅延等が発生しにくくなり、多層プリント配線板の性能の向上に繋がる。
【００９０】
（５）次に、バイアホール用開口の内壁を含む層間樹脂絶縁層の表面と上記工程で貫通孔を形成した場合には貫通孔の内壁とに、必要に応じて、酸または酸化剤を用いて粗化面を形成する。
上記酸としては、硫酸、硝酸、塩酸、リン酸、蟻酸等が挙げられ、上記酸化剤としては、クロム酸、クロム硫酸、過マンガン酸ナトリウム等の過マンガン酸塩等が挙げられる。
また、上記粗化面の形成は、プラズマ処理等を用いて行ってもよい。
【００９１】
また、粗化面を形成した後には、アルカリ等の水溶液や中和液等を用いて、層間樹脂絶縁層の表面を中和することが望ましい。
次工程に、酸や酸化剤の影響を与えないようにすることができるからである。
【００９２】
（６）次に、バイアホール用開口の内壁を含む層間樹脂絶縁層の表面と、上記工程で貫通孔を形成した場合には貫通孔の内壁とに、必要に応じて、酸や酸化剤等を用いて粗化面を形成する。
なお、この粗化面は、層間樹脂絶縁層とその上に形成する薄膜導体層との密着性を高めるために形成するものであり、層間樹脂絶縁層と薄膜導体層との間に充分な密着性がある場合には形成しなくてもよい。
【００９３】
（７）次に、バイアホール用開口を設けた層間樹脂絶縁層の表面に薄膜導体層を形成する。
上記薄膜導体層は、無電解めっき、スパッタリング、蒸着等の方法を用いて形成することができる。なお、層間樹脂絶縁層の表面に粗化面を形成しなかった場合には、上記薄膜導体層は、スパッタリングにより形成することが望ましい。
なお、無電解めっきにより薄膜導体層を形成する場合には、被めっき表面に、予め、触媒を付与しておく。上記触媒としては、例えば、塩化パラジウム等が挙げられる。
【００９４】
上記薄膜導体層の厚さは特に限定されないが、該薄膜導体層を無電解めっきにより形成した場合には、０．６〜１．２μｍが望ましく、スパッタリングにより形成した場合には、０．１〜１．０μｍが望ましい。
なお、上記（４）の工程で貫通孔を形成した場合には、この工程で貫通孔の内壁面にも金属からなる薄膜導体層を形成することにより、スルーホールとすることができる。
【００９５】
また、上記したように貫通孔の内壁面に薄膜導体層を形成し、スルーホールとした場合には、この後、スルーホール内を樹脂充填材で充填することが望ましい。上記樹脂充填材としては、例えば、エポキシ樹脂と硬化剤と無機粒子とを含む樹脂組成物等が挙げられる。
【００９６】
また、スルーホール内を樹脂充填材により充填した場合には、スルーホール上に樹脂充填材を覆う蓋めっき層を形成してもよく、蓋めっき層を形成した場合には、該蓋めっき層の直上に、バイアホールや半田パッドを形成することができるため、信号伝送距離を短くすることができる。
【００９７】
（８）次に、上記薄膜導体層上の一部にドライフィルムを用いてめっきレジストを形成し、その後、上記薄膜導体層をめっきリードとして電気めっきを行い、上記めっきレジスト非形成部に電気めっき層を形成する。
このとき、バイアホール用開口を電気めっきで充填してフィールドビア構造としてもよく、バイアホール用開口に導電性ペーストを充填した後、その上に蓋めっき層を形成してフィールドビア構造としてもよい。
【００９８】
（９）電気めっき層を形成した後、めっきレジストを剥離し、めっきレジストの下に存在していた金属からなる薄膜導体層をエッチングにより除去し、独立した導体回路とする。
エッチング液としては、例えば、硫酸−過酸化水素水溶液、過硫酸アンモニウム等の過硫酸塩水溶液、塩化第二鉄、塩化第二銅、塩酸等が挙げられる。また、エッチング液として上述した第二銅錯体と有機酸とを含む混合溶液を用いてもよい。
【００９９】
また、上記（８）および（９）に記載した方法に代えて、以下の方法を用いることにより導体回路を形成してもよい。
即ち、上記薄膜導体層上の全面に電気めっき層を形成した後、該電気めっき層上の一部にドライフィルムを用いてエッチングレジストを形成し、その後、エッチングレジスト非形成部下の電気めっき層および薄膜導体層をエッチングにより除去し、さらに、エッチングレジストを剥離することにより独立した導体回路を形成してもよい。
【０１００】
（１０）この後、上記（３）〜（９）の工程を繰り返すことにより、層間樹脂絶縁層上に最上層の導体回路が形成された基板を作製する。
【０１０１】
（１１）次に、最上層の導体回路を含む基板上に、複数の半田バンプ形成用開口を有するソルダーレジスト層を形成する。
具体的には、未硬化のソルダーレジスト組成物をロールコータやカーテンコータ等により塗布したり、フィルム状に成形したソルダーレジスト組成物を圧着したりした後、レーザ処理や露光現像処理により半田バンプ形成用開口を形成し、さらに、必要に応じて、硬化処理を施すことによりソルダーレジスト層を形成する。
【０１０２】
上記ソルダーレジスト層は、例えば、ポリフェニレンエーテル樹脂、ポリオレフィン樹脂、フッ素樹脂、熱可塑性エラストマー、エポキシ樹脂、ポリイミド樹脂等を含むソルダーレジスト組成物を用いて形成することができ、これらの樹脂の具体例としては、例えば、層間樹脂絶縁層に用いた樹脂と同様の樹脂等が挙げられる。
【０１０３】
また、上記以外のソルダーレジスト組成物としては、例えば、ノボラック型エポキシ樹脂の（メタ）アクリレート、イミダゾール硬化剤、２官能性（メタ）アクリル酸エステルモノマー、分子量５００〜５０００程度の（メタ）アクリル酸エステルの重合体、ビスフェノール型エポキシ樹脂等からなる熱硬化性樹脂、多価アクリル系モノマー等の感光性モノマー、グリコールエーテル系溶剤などを含むペースト状の流動体が挙げられ、その粘度は２５℃で１〜１０Ｐａ・ｓに調整されていることが望ましい。
上記ノボラック型エポキシ樹脂の（メタ）アクリレートとしては、例えば、フェノールノボラックやクレゾールノボラックのグリシジルエーテルをアクリル酸やメタクリル酸等と反応させたエポキシ樹脂等が挙げられる。
【０１０４】
上記２官能性（メタ）アクリル酸エステルモノマーとしては特に限定されず、例えば、各種ジオール類のアクリル酸やメタクリル酸のエステル等が挙げられ、その市販品としては、日本化薬社製のＲ−６０４、ＰＭ２、ＰＭ２１等が挙げられる。
【０１０５】
また、上記ソルダーレジスト組成物は、エラストマーや無機フィラーが配合されていてもよい。
エラストマーが配合されていることにより、形成されるソルダーレジスト層は、エラストマーの有する柔軟性および反発弾性により、ソルダーレジスト層に応力が作用した場合でも、該応力を吸収したり、緩和したりすることができ、その結果、多層プリント配線板の製造工程や製造した多層プリント配線板にＩＣチップ等の電子部品を搭載した後のソルダーレジスト層にクラックや剥離が発生することを抑制でき、さらに、クラックが発生した場合でも該クラックが大きく成長することがほとんどない。
【０１０６】
また、上記半田バンプ形成用開口を形成する際に用いるレーザとしては、上述したバイアホール用開口を形成する際に用いるレーザと同様のもの等が挙げられる。
【０１０７】
次に、上記半田バンプ形成用開口の底面に露出した導体回路の表面に、必要に応じて、半田パッドを形成する。
上記半田パッドは、ニッケル、パラジウム、金、銀、白金等の耐食性金属により上記導体回路表面を被覆することにより形成することができる。
具体的には、ニッケル−金、ニッケル−銀、ニッケル−パラジウム、ニッケル−パラジウム−金等の金属により形成することが望ましい。
また、上記半田パッドは、例えば、めっき、蒸着、電着等の方法を用いて形成することができるが、これらのなかでは、被覆層の均一性に優れるという点からめっきが望ましい。
【０１０８】
（１２）次に、上記半田バンプ形成用開口の底面に半田バッドを有するソルダーレジスト層に、上記した（ａ）〜（ｃ）の工程を行うことにより、半田ペースト層を形成し、該半田ペースト層にリフロー処理を施すことにより半田ペーストを形成する。
なお、上記リフロー処理は、第一および第二の半田ペースト印刷工程終了後に行ってもよいし、第一の半田ペースト印刷工程終了後に一度行い、第二の半田ペースト印刷工程終了後に再度行ってもよい。
【０１０９】
また、第二の半田ペースト印刷工程で形成した半田ペースト層にリフロー処理を施す前に、予め、該半田ペースト層に導電性ピンを取り付けておき、外部端子と接続するためのＰＧＡ（Pin Grid Array) を形成してもよい。
なお、製品認識文字などを形成するための文字印刷工程やソルダーレジスト層の改質のために、酸素や四塩化炭素などのプラズマ処理を適時行ってもよい。
【０１１０】
【実施例】
以下、本発明をさらに詳細に説明する。
（実施例１）
Ａ．層間樹脂絶縁層用樹脂フィルムの作製
ビスフェノールＡ型エポキシ樹脂（エポキシ当量４６９、油化シェルエポキシ社製エピコート１００１）３０重量部、クレゾールノボラック型エポキシ樹脂（エポキシ当量２１５、大日本インキ化学工業社製 エピクロンＮ−６７３）４０重量部、トリアジン構造含有フェノールノボラック樹脂（フェノール性水酸基当量１２０、大日本インキ化学工業社製 フェノライトＫＡ−７０５２）３０重量部をエチルジグリコールアセテート２０重量部、ソルベントナフサ２０重量部に攪拌しながら加熱溶解させ、そこへ末端エポキシ化ポリブタジエンゴム（ナガセ化成工業社製 デナレックスＲ−４５ＥＰＴ）１５重量部と２−フェニル−４、５−ビス（ヒドロキシメチル）イミダゾール粉砕品１．５重量部、微粉砕シリカ２重量部、シリコン系消泡剤０．５重量部を添加しエポキシ樹脂組成物を調製した。
得られたエポキシ樹脂組成物を厚さ３８μｍのＰＥＴフィルム上に乾燥後の厚さが５０μｍとなるようにロールコーターを用いて塗布した後、８０〜１２０℃で１０分間乾燥させることにより、層間樹脂絶縁層用樹脂フィルムを作製した。
【０１１１】
Ｂ．貫通孔充填用樹脂組成物の調製
ビスフェノールＦ型エポキシモノマー（油化シェル社製、分子量：３１０、ＹＬ９８３Ｕ）１００重量部、表面にシランカップリング剤がコーティングされた平均粒径が１．６μｍで、最大粒子の直径が１５μｍ以下のＳｉＯ₂ 球状粒子（アドテック社製、ＣＲＳ １１０１−ＣＥ）７２重量部およびレベリング剤（サンノプコ社製 ペレノールＳ４）１．５重量部を容器にとり、攪拌混合することにより、その粘度が２５±１℃で３０〜８０Ｐａ・ｓの樹脂充填材を調製した。
なお、硬化剤として、イミダゾール硬化剤（四国化成社製、２Ｅ４ＭＺ−ＣＮ）６．５重量部を用いた。
【０１１２】
Ｃ．プリント配線板の製造方法
（１）厚さ０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる基板１の両面に１８μｍの銅箔８がラミネートされている銅張積層板を出発材料とした（図３（ａ）参照）。まず、この銅張積層板をドリル削孔し、無電解めっき処理を施し、パターン状にエッチングすることにより、基板１の両面に下層導体回路４とスルーホール９を形成した。
【０１１３】
（２）スルーホール９および下層導体回路４を形成した基板を水洗いし、乾燥した後、ＮａＯＨ（１０ｇ／ｌ）、ＮａＣｌＯ₂ （４０ｇ／ｌ）、Ｎａ₃ ＰＯ₄ （６ｇ／ｌ）を含む水溶液を黒化浴（酸化浴）とする黒化処理、および、ＮａＯＨ（１０ｇ／ｌ）、ＮａＢＨ₄ （６ｇ／ｌ）を含む水溶液を還元浴とする還元処理を行い、そのスルーホール９を含む下層導体回路４の全表面に粗化面４ａ、９ａを形成した（図３（ｂ）参照）。
【０１１４】
（３）次に、上記Ｂに記載した貫通孔充填用樹脂組成物を調製した後、下記の方法により調整後２４時間以内に、スルーホール９内、および、基板１の片面の導体回路非形成部と導体回路４の外縁部とに樹脂充填材１０の層を形成した。
即ち、まず、スキージを用いてスルーホール内に貫通孔充填用樹脂組成物を押し込んだ後、１００℃、２０分の条件で乾燥させた。次に、導体回路非形成部に相当する部分が開口したマスクを基板上に載置し、スキージを用いて凹部となっている導体回路非形成部に樹脂充填材１０の層を形成し、１００℃、２０分の条件で乾燥させた（図３（ｃ）参照）。
【０１１５】
（４）上記（３）の処理を終えた基板の片面を、＃６００のベルト研磨紙（三共理化学製）を用いたベルトサンダー研磨により、内層銅パターン４の表面やスルーホール９のランド表面に樹脂充填材１０が残らないように研磨し、次いで、上記ベルトサンダー研磨による傷を取り除くためのバフ研磨を行った。このような一連の研磨を基板の他方の面についても同様に行った。
次いで、１００℃で１時間、１５０℃で１時間の加熱処理を行って樹脂充填材１０を硬化させた。
【０１１６】
このようにして、スルーホール９や導体回路非形成部に形成された樹脂充填材１０の表層部および下層導体回路４の表面を平坦化し、樹脂充填材１０と下層導体回路４の側面４ａとが粗化面を介して強固に密着し、またスルーホール９の内壁面９ａと樹脂充填材１０とが粗化面を介して強固に密着した絶縁性基板を得た（図３（ｄ）参照）。即ち、この工程により、樹脂充填材１０の表面と下層導体回路４の表面が同一平面となる。
【０１１７】
（５）上記基板を水洗、酸性脱脂した後、ソフトエッチングし、次いで、エッチング液を基板の両面にスプレイで吹きつけて、下層導体回路４の表面とスルーホール９のランド表面と内壁とをエッチングすることにより、下層導体回路４の全表面に粗化面４ａ、９ａを形成した（図４（ａ）参照）。なお、エッチング液としては、イミダゾール銅（ＩＩ）錯体１０重量部、グリコール酸７重量部、塩化カリウム５重量部からなるエッチング液（メック社製、メックエッチボンド）を使用した。
【０１１８】
（６）基板の両面に、上記Ａで作製した基板より少し大きめの層間樹脂絶縁層用樹脂フィルムを基板上に載置し、圧力０．４ＭＰａ、温度８０℃、圧着時間１０秒の条件で仮圧着して裁断した後、さらに、以下の方法により真空ラミネーター装置を用いて張り付け、その後、熱硬化させることにより層間樹脂絶縁層２を形成した（図４（ｂ）参照）。すなわち、層間樹脂絶縁層用樹脂フィルムを基板上に、真空度６７Ｐａ、圧力０．４ＭＰａ、温度８０℃、圧着時間６０秒の条件で本圧着して張り付け、その後、１７０℃で３０分間熱硬化させた。
【０１１９】
（７）次に、層間樹脂絶縁層２上に、厚さ１．２ｍｍの貫通孔が形成されたマスクを介して、波長１０．４μｍのＣＯ₂ ガスレーザにて、ビーム径４．０ｍｍ、トップハットモード、パルス幅８．０μ秒、マスクの貫通孔の径１．０ｍｍ、１ショットの条件で層間樹脂絶縁層２に、直径７５μｍのバイアホール用開口６を形成した（図４（ｃ）参照）。
【０１２０】
（８）さらに、バイアホール用開口６を形成した基板を、６０ｇ／ｌの過マンガン酸を含む８０℃の溶液に１０分間浸漬し、層間樹脂絶縁層２の表面に存在するエポキシ樹脂粒子を溶解除去することにより、バイアホール用開口６の内壁を含む層間樹脂絶縁層２の表面を粗面とした（図４（ｄ）参照）。
【０１２１】
（９）次に、上記処理を終えた基板を、中和溶液（シプレイ社製）に浸漬してから水洗いした。
さらに、粗面化処理（粗化深さ３μｍ）した該基板の表面に、パラジウム触媒（アトテック社製）を付与することにより、層間樹脂絶縁層２の表面およびバイアホール用開口６の内壁面に触媒核を付着させた。
【０１２２】
（１０）次に、以下の組成の無電解銅めっき水溶液中に基板を浸漬して、粗面全体に厚さ０．６〜３．０μｍの無電解銅めっき層１２を形成した（図５（ａ）参照）。
〔無電解めっき水溶液〕
ＮｉＳＯ₄ ０．００３ ｍｏｌ／ｌ
酒石酸 ０．２００ ｍｏｌ／ｌ
硫酸銅 ０．０３０ ｍｏｌ／ｌ
ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ
ＮａＯＨ ０．１００ ｍｏｌ／ｌ
α、α′−ビピリジル ４０ ｍｇ／ｌ
ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ
〔無電解めっき条件〕
３５℃の液温度で４０分
【０１２３】
（１１）市販の感光性ドライフィルムを無電解銅めっき層１２に貼り付け、マスクを載置して、１００ｍＪ／ｃｍ² で露光し、０．８％炭酸ナトリウム水溶液で現像処理することにより、厚さ２０μｍのめっきレジスト３を設けた（図５（ｂ）参照）。
【０１２４】
（１２）ついで、基板を５０℃の水で洗浄して脱脂し、２５℃の水で水洗後、さらに硫酸で洗浄してから、以下の条件で電解銅めっきを施し、電解銅めっき層１３を形成した（図５（ｃ）参照）。
〔電解めっき水溶液〕
硫酸 ２．２４ ｍｏｌ／ｌ
硫酸銅 ０．２６ ｍｏｌ／ｌ
添加剤 １９．５ ｍｌ／ｌ
（アトテックジャパン社製、カパラシドＨＬ）
〔電解めっき条件〕
電流密度 １ Ａ／ｄｍ²
時間 ６５ 分
温度 ２２±２ ℃
【０１２５】
（１３）さらに、めっきレジスト３を５％ＮａＯＨ水溶液で剥離除去した後、そのめっきレジスト３下の無電解めっき膜１２を硫酸と過酸化水素の混合液でエッチング処理して溶解除去し、無電解銅めっき膜１２と電解めっき膜１３からなる厚さ１８μｍの独立の上層導体回路５（バイアホール７を含む）とした（図５（ｄ）参照）。
【０１２６】
（１４）上記（５）〜（１３）の工程を繰り返すことにより、さらに、上層の層間樹脂絶縁層２と上層の導体回路５（バイアホール７を含む）を形成した（図６（ａ）〜図７（ａ）参照）。
その後、上記上層の導体回路５の表面にエッチング液を用いて粗化面を形成した。なお、エッチング液としては、メック社製、メックエッチボンドを使用した（図７（ｂ）参照）。
【０１２７】
（１５）次に、ジエチレングリコールジメチルエーテル（ＤＭＤＧ）に６０重量％の濃度になるように溶解させた、クレゾールノボラック型エポキシ樹脂（日本化薬社製）のエポキシ基５０％をアクリル化した感光性付与のオリゴマー（分子量：４０００）４６．６７重量部、メチルエチルケトンに溶解させた８０重量％のビスフェノールＡ型エポキシ樹脂（油化シェル社製、商品名：エピコート１００１）１５．０重量部、イミダゾール硬化剤（四国化成社製、商品名：２Ｅ４ＭＺ−ＣＮ）１．６重量部、感光性モノマーである多価アクリルモノマー（日本化薬社製、商品名：Ｒ６０４）３．０重量部、同じく多価アクリルモノマー（共栄化学社製、商品名：ＤＰＥ６Ａ）１．５重量部、分散系消泡剤（サンノプコ社製、Ｓ−６５）０．７１重量部を容器にとり、攪拌、混合して混合組成物を調製し、この混合組成物に対して光重合開始剤としてベンゾフェノン（関東化学社製）２．０重量部、光増感剤としてのミヒラーケトン（関東化学社製）０．２重量部を加え、粘度を２５℃で２．０Ｐａ・ｓに調整したソルダーレジスト組成物を得た。
なお、粘度測定は、Ｂ型粘度計（東京計器社製、ＤＶＬ−Ｂ型）で６０ｍｉｎ^-1（ｒｐｍ）の場合はローターＮｏ．４、６ｍｉｎ^-1（ｒｐｍ）の場合はローターＮｏ．３によった。
【０１２８】
（１６）次に、多層配線基板の両面に、上記ソルダーレジスト組成物を２０μｍの厚さで塗布し、７０℃で２０分間、７０℃で３０分間の条件で乾燥処理を行った後、半田パッドのパターンが描画された厚さ５ｍｍのフォトマスクをソルダーレジスト層に密着させて１０００ｍＪ／ｃｍ² の紫外線で露光し、ＤＭＴＧ溶液で現像処理し、直径８０μｍの開口を形成した。
そして、さらに、８０℃で１時間、１００℃で１時間、１２０℃で１時間、１５０℃で３時間の条件でそれぞれ加熱処理を行ってソルダーレジスト層を硬化させ、半田バンプ形成用開口を有し、その厚さが２０μｍのソルダーレジスト層１４を形成した。なお、半田バンプ形成用開口の開口径は８０μｍであり、隣合う半田バンプ形成用開口間の距離は１５０μｍである。
また、上記ソルダーレジスト組成物としては、市販のソルダーレジスト組成物を使用することもできる。
【０１２９】
（１７）次に、過硫酸ナトリウムを主成分とするエッチング液を、そのエッチング能が毎分２μｍ程度になるように調製し、このエッチング液中にソルダーレジスト層１４が形成された基板を１分間浸漬し、導体回路表面に平均粗度（Ｒａ）が１μｍ以下の粗化面を形成した。
さらに、この基板を、塩化ニッケル（２．３×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（２．８×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．６×１０^-1ｍｏｌ／ｌ）を含むｐＨ＝４．５の無電解ニッケルめっき液に２０分間浸漬して、開口部に厚さ５μｍのニッケルめっき層１５を形成した。さらに、その基板をシアン化金カリウム（７．６×１０^-3ｍｏｌ／ｌ）、塩化アンモニウム（１．９×１０^-1ｍｏｌ／ｌ）、クエン酸ナトリウム（１．２×１０^-1ｍｏｌ／ｌ）、次亜リン酸ナトリウム（１．７×１０^-1ｍｏｌ／ｌ）を含む無電解金めっき液に８０℃の条件で７．５分間浸漬して、ニッケルめっき層１５上に、厚さ０．０３μｍの金めっき層１６を形成し、半田パッドとした。
【０１３０】
（１８）この後、ソルダーレジスト層１４上に、全ての半田バンプ形成用開口に対向する部分に直径１００μｍの開口を有するマスクを載置し、ピストン式圧入型印刷機を用いて、凹形状の半田バンプ形成用開口を半田ペーストで完全に充填した。
なお、ここで充填した半田ペーストは、Ｓｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２００Ｐａ・ｓに調整したものである。
【０１３１】
（１９）次に、上記（１８）の工程で充填した半田ペーストのうち、ソルダーレジスト層の表面より盛り上がった部分の半田ペーストをステンレス製のスキージまたは硬度９０°の平ゴムスキージを用いて除去することにより、充填した半田ペーストの表面を平坦化するとともに、半田ペーストの表面とソルダーレジスト層の表面とを同一平面にした。
【０１３２】
（２０）次に、ソルダーレジスト層１４上に、上記（１８）の工程で用いたマスクと同様のマスクを載置し、ピストン式圧入型印刷機で半田ペーストを印刷することにより半田ペースト層を形成した。
なお、ここで充填した半田ペーストは、Ｓｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２５０Ｐａ・ｓに調整したものである。
【０１３３】
（２１）その後、上記（１８）〜（２０）の工程で印刷した半田ペーストを２５０℃でリフローし、さらに、フラックス洗浄を行うことにより、半田バンプを備えた多層プリント配線板を得た（図７（ｃ）参照）。
【０１３４】
（実施例２）
Ａ．実施例１と同様にして、層間樹脂絶縁層用樹脂フィルムの作製、および、貫通孔充填用樹脂組成物の調製を行った。
【０１３５】
Ｂ．多層プリント配線板の製造
（１）厚さ０．８ｍｍのガラスエポキシ樹脂またはＢＴ（ビスマレイミドトリアジン）樹脂からなる絶縁性基板３０の両面に１８μｍの銅箔３２がラミネートされている銅張積層板を出発材料とした（図８（ａ）参照）。まず、この銅張積層板を下層導体回路パターン状にエッチングすることにより、基板の両面に下層導体回路３４を形成した（図８（ｂ）参照）。
【０１３６】
（２）下層導体回路３４を形成した基板３０を水洗いし、乾燥した後、ＮａＯＨ（１０ｇ／ｌ）、ＮａＣｌＯ₂ （４０ｇ／ｌ）、Ｎａ₃ ＰＯ₄ （６ｇ／ｌ）を含む水溶液を黒化浴（酸化浴）とする黒化処理、および、ＮａＯＨ（１０ｇ／ｌ）、ＮａＢＨ₄ （６ｇ／ｌ）を含む水溶液を還元浴とする還元処理を行い、下層導体回路３４の表面に粗化面３４ａを形成した（図８（ｃ）参照）。
【０１３７】
（３）次に、上記Ａで作製した層間樹脂絶縁層用樹脂フィルムを、温度５０〜１５０℃まで昇温しながら、０．５ＭＰａで真空圧着ラミネートして貼り付け、樹脂フィルム層５０αを形成した（図８（ｄ）参照）。
さらに、樹脂フィルム層５０αを貼り付けた基板３０に、ドリル加工により直径３００μｍの貫通孔３５を形成した（図８（ｅ）参照）。
【０１３８】
（４）次に、樹脂フィルム層５０α上に、厚さ１．２ｍｍの貫通孔が形成されたマスクを介して、波長１０．４μｍのＣＯ₂ ガスレーザにて、ビーム径４．０ｍｍ、トップハットモード、パルス幅８．０μ秒、マスクの貫通孔の径１．０ｍｍ、１ショットの条件で樹脂フィルム層５０αに、直径７５μｍのバイアホール用開口５２を形成し、層間樹脂絶縁層５０とした（図９（ａ）参照）。
【０１３９】
（５）バイアホール用開口５２を形成した基板を、６０ｇ／ｌの過マンガン酸を含む８０℃の溶液に１０分間浸漬し、貫通孔３５の壁面にデスミア処理を施すとともに、層間樹脂絶縁層５０の表面に存在するエポキシ樹脂粒子を溶解除去することにより、バイアホール用開口５２の内壁面を含むその表面に粗化面５０ａ、５２ａを形成した（図９（ｂ）参照）。
【０１４０】
（６）次に、上記処理を終えた基板を、中和溶液（シプレイ社製）に浸漬してから水洗いした。
さらに、粗面化処理（粗化深さ３μｍ）した該基板の表面に、パラジウム触媒を付与することにより、層間樹脂絶縁層５０の表面（バイアホール用開口５２の内壁面を含む）、および、貫通孔３５の壁面に触媒核を付着させた（図示せず）。即ち、上記基板を塩化パラジウム（ＰｂＣｌ₂ ）と塩化第一スズ（ＳｎＣｌ₂ ）とを含む触媒液中に浸漬し、パラジウム金属を析出させることにより触媒を付与した。
【０１４１】
（７）次に、以下の組成の無電解銅めっき水溶液中に、基板を浸漬し、層間樹脂絶縁層５０の表面（バイアホール用開口５２の内壁面を含む）、および、貫通孔３５の壁面に厚さ０．６〜３．０μｍの無電解銅めっき膜４２を形成した（図９（ｃ）参照）。
〔無電解めっき水溶液〕
ＮｉＳＯ₄ ０．００３ ｍｏｌ／ｌ
酒石酸 ０．２００ ｍｏｌ／ｌ
硫酸銅 ０．０３０ ｍｏｌ／ｌ
ＨＣＨＯ ０．０５０ ｍｏｌ／ｌ
ＮａＯＨ ０．１００ ｍｏｌ／ｌ
α、α′−ビピリジル １００ ｍｇ／ｌ
ポリエチレングリコール（ＰＥＧ） ０．１０ ｇ／ｌ
〔無電解めっき条件〕
３４℃の液温度で４０分
【０１４２】
（８）次に、無電解銅めっき膜４２が形成された基板に市販の感光性ドライフィルムを張り付け、マスクを載置して、１００ｍＪ／ｃｍ² で露光し、０．８％炭酸ナトリウム水溶液で現像処理することにより、厚さ２０μｍのめっきレジスト４３を設けた（図９（ｄ）参照）。
【０１４３】
（９）ついで、基板を５０℃の水で洗浄して脱脂し、２５℃の水で水洗後、さらに硫酸で洗浄してから、以下の条件で電解めっきを施し、めっきレジスト４３非形成部に、厚さ２０μｍの電解銅めっき膜４４を形成した（図９（ｅ）参照）。
〔電解めっき液〕
硫酸 ２．２４ ｍｏｌ／ｌ
硫酸銅 ０．２６ ｍｏｌ／ｌ
添加剤 １９．５ ｍｌ／ｌ
（アトテックジャパン社製、カパラシドＧＬ）
〔電解めっき条件〕
電流密度 １ Ａ／ｄｍ²
時間 ６５ 分
温度 ２２±２ ℃
【０１４４】
（１０）次に、めっきレジスト４３を５％ＫＯＨで剥離除去した後、そのめっきレジスト４３下の無電解めっき膜を硫酸と過酸化水素との混合液でエッチング処理して溶解除去し、スルーホール３６、および、上層導体回路４５（バイアホール４６を含む）とした（図１０（ａ）参照）。
【０１４５】
（１１）次に、スルーホール３６等を形成した基板３０をエッチング液に浸漬し、スルーホール３６、および、上層導体回路（バイアホール４６を含む）の表面に粗化面３６ａ、４６ａを形成した（図１０（ｂ）参照）。
なお、エッチング液としては、メック社製、メックエッチボンドを使用した。
【０１４６】
（１２）次に、上記Ａに記載した貫通孔充填用樹脂組成物を調製した後、下記の方法により調製後２４時間以内に、スルーホール３６内、および、基板の片面のバイアホール４６内に樹脂充填材４０、５４の層を形成した。
即ち、まず、スキージを用いてスルーホール内に貫通孔充填用樹脂組成物を押し込んだ後、１００℃、２０分の条件で乾燥させた。次に、バイアホール４６に相当する部分が開口したマスクを基板上に載置し、スキージを用いてバイアホール４６内に貫通孔充填用樹脂組成物を充填し、１００℃、２０分の条件で乾燥を行った。
さらに、同様にして、基板の他方の面のバイアホール４６内にも貫通孔充填用樹脂組成物を充填した（図１０（ｃ）参照）。
【０１４７】
（１３）次に、上記（１２）の処理を終えた基板の両面にバフ研磨を施し、スルーホール３６およびバイアホール４６から露出した樹脂充填材４０、５４の層の表面を平坦にした。
次いで、１００℃で１時間、１５０℃で１時間の加熱処理を行うことにより、樹脂充填材４０、５４の層を硬化させた（図１０（ｄ）参照）。
【０１４８】
（１４）次に、層間樹脂絶縁層５０の表面、および、樹脂充填材４０、５４の露出面に、上記（６）と同様の処理を行いてパラジウム触媒（図示せず）を付与した。
次に、上記（７）と同様の条件で無電解めっき処理を施し、層間樹脂絶縁層５０の表面、および、樹脂充填材４０、５４の露出面に無電解めっき膜５６を形成した（図１１（ａ）参照）。
【０１４９】
（１５）次に、上記（８）と同様の方法を用いて、無電解めっき膜５６上に、厚さ２０μｍのめっきレジストを設けた（図示せず）。さらに、上記（９）と同様の条件で電解めっきを施して、めっきレジスト非形成部に電解めっき膜５７を形成した。その後、めっきレジストと、その下に存在する無電解めっき膜５６とを除去し、スルーホール３６上およびバイアホール４６上に、無電解めっき膜５６と電解めっき膜５７とからなる蓋めっき層５８を形成した（図１１（ｂ）参照）。
【０１５０】
（１６）次に、蓋めっき層５８の表面に上記（１１）で用いたエッチング液（メックエッチボンド）を用いて粗化面５８ａを形成した（図１１（ｃ）参照）。
（１７）次に、上記（３）〜（１１）の工程を繰り返すことにより、さらに上層の層間樹脂絶縁層６０、導体回路（バイアホール６６を含む）を形成し、多層配線板を得た（図１１（ｄ）参照）。なお、この工程では、スルーホールを形成しなかった。
【０１５１】
（１８）次に、実施例１の（１６）および（１７）と同様にして、半田バンプ形成用開口が形成され、その底面に、半田パッド６６を有するソルダーレジスト層６０を形成した（図１２（ａ）〜（ｃ）参照）。なお、半田バンプ形成用開口の開口径は８０μｍであり、隣合う半田バンプ形成用開口間の距離は１５０μｍである。
【０１５２】
（１９）この後、ソルダーレジスト層１４上に、全ての半田バンプ形成用開口に対向する部分に直径９０μｍの開口を有するマスクを載置し、ピストン式圧入型印刷機を用いて、凹形状の半田バンプ形成用開口を半田ペーストで完全に充填した。
なお、ここで充填した半田ペーストは、Ｓｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２００Ｐａ・ｓに調整したものである。
【０１５３】
（２０）次に、上記（１９）の工程で充填した半田ペーストのうち、ソルダーレジスト層の表面より盛り上がった部分の半田ペーストをステンレス製のスキージを用いて除去することにより、充填した半田ペーストの表面を平坦化するとともに、半田ペーストの表面とソルダーレジスト層の表面とを同一平面にした。
さらに、充填した半田ペーストを２５０℃でリフローした。
【０１５４】
（２１）次に、ソルダーレジスト層１４の片面に、全ての半田バンプ形成用開口に対向する部分に直径１００μｍの開口を有するマスクを載置し、ピストン式圧入型印刷機で半田ペーストを印刷することにより半田ペースト層を形成した。
なお、ここで充填した半田ペーストは、Ｓｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２５０Ｐａ・ｓに調整したものである。
【０１５５】
また、ソルダーレジスト層１４の他の一面には、Ｓｎ：Ｓｂ＝９５：５の半田ペースト層を形成した後、導電性ピン７８を取り付けた（図１３参照）。
【０１５６】
（２２）その後、上記（２１）の工程で形成した半田ペースト層を２６０℃でリフローし、さらに、フラックス洗浄を行うことにより、半田バンプとＰＧＡ（Pin Grid Array）とを備えた多層プリント配線板を得た。
【０１５７】
（実施例３）
実施例１において、（１６）の工程でその開口径が１００μｍの半田バンプ形成用開口を形成し、（１８）の工程でＳｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２５０Ｐａ・ｓに調整した半田ペーストを充填した以外は、実施例１と同様にして多層プリント配線板を製造した。
【０１５８】
（実施例４）
実施例２において、（１８）の工程でその開口径が１００μｍの半田バンプ形成用開口を形成し、（１９）の工程でＳｎ：Ａｇを重量比９６．５：３．５で配合させた主として粒径５〜２０μｍの半田を含むもので、その粘度を２５０Ｐａ・ｓに調整した半田ペーストを充填した以外は、実施例２と同様にして多層プリント配線板を製造した。
【０１５９】
（比較例１）
実施例１の（１８）〜（２１）の工程に代えて、全ての半田バンプ形成用開口に１回の半田ペースト印刷で半田ペースト層を形成し、リフローすることにより半田バンプを形成した以外は、実施例１と同様にして多層プリント配線板を製造した。具体的には、以下の工程を行った。
【０１６０】
即ち、半田パッドを形成したソルダーレジスト層上に、全ての半田バンプ形成用開口に対向する部分に直径１００μｍの開口を有するマスクを載置し、ピストン式圧入型印刷機を用いて、半田バンプ形成用開口に半田ペーストを印刷し、半田バンプを形成するための半田ペースト層を形成した。
その後、半田ペースト層を２５０℃でリフローし、さらに、フラックス洗浄を行うことにより、半田バンプを備えた多層プリント配線板を得た。
なお、半田ペーストとしては、実施例１の（１８）の工程で用いたものと同様のものを使用した。
【０１６１】
（比較例２）
実施例２の（１９）〜（２２）の工程に代えて、全ての半田バンプ形成用開口に１回の半田ペースト印刷で半田ペースト層を形成し、リフローすることにより半田バンプを形成した以外は、実施例２と同様にして多層プリント配線板を製造した。具体的には、以下の工程を行った。
【０１６２】
即ち、半田パッドを形成したソルダーレジスト層上に、全ての半田バンプ形成用開口に対向する部分に直径１００μｍの開口を有するマスクを載置し、ピストン式圧入型印刷機を用いて、半田バンプ形成用開口に半田ペーストを印刷し、半田バンプを形成するための半田ペースト層を形成した。
その後、Ｓｎ：Ｓｂ＝９５：５の半田ペースト層を形成した基板の片面に導電性ピンを取り付け、さらに、半田ペースト層を２６０℃でリフローした後、フラックス洗浄を行うことにより、半田バンプとＰＧＡとを備えた多層プリント配線板を得た。
なお、半田ペーストとしては、実施例２の（２１）の工程で用いたものと同様のものを使用した。
【０１６３】
実施例１〜４および比較例１、２で得られた多層プリント配線板について、ソルダーレジスト層表面の汚染の有無、半田バンプのボイドの有無、および、半田バンプの形状と高さの観察、信頼性試験前後の性能評価を下記の評価方法を用いて行った。結果を表１に示した。
【０１６４】
評価方法
（１）半田バンプのボイドの有無、半田バンプの形状と高さ
多層プリント配線板の半田バンプが形成されている部分をＸ線にて観察してボイドの有無を評価し、ソルダーレジスト層からの半田バンプの高さを測定し、形状を観察した。なお、形状については、半球状になっているものを○、そうでないものを×とした。
【０１６５】
（２）信頼性試験
１３５℃、相対湿度８５％の条件下で１０００時間放置した後、下記する導通試験を行い、プリント配線板を半田バンプが形成されている部分で切断して半田バンプの状態を観察した。信頼性試験と変わらないものを○、クラック等が観察されたものを×とした。
【０１６６】
（３）導通試験
多層プリント配線板を製造した後、上記信頼性試験前後に導通試験を行い、モニターに表示された結果から導通状態を評価した。短絡、断線のないものを○、短絡、断線のあったものを×とした。
【０１６７】
【表１】

【０１６８】
表１に示したように、実施例１〜４の多層プリント配線板では、半田バンプにボイドは観察されず、半田バンプの高さ、形状は略均一であり、ソルダーレジスト層の表面も半田ペーストで汚染されていなかった。また、半田バンプ間での短絡もなく、信頼性試験前後に行った導通試験にも全く問題はなく、信頼性試験後にクラック、剥がれ等も見当たらなかった。
また、第二の半田ペースト印刷工程で印刷する半田ペーストの粘度を１５０〜３５０Ｐａ・ｓの範囲で順次変更し、実施例１と同様の方法を用いて半田バンプを形成した場合にも所望の形状の半田バンプを形成することができた。
【０１６９】
一方、比較例１の多層プリント配線板では、一回の印刷工程で粘度の低い半田ペーストのみを印刷しているため、半田バンプにボイドは形成されていなかったものの、高さも実施例１と比べてバラツキが大きく、形状も一様でなかった。また、ソルダーレジスト層の表面が半田ペーストで汚染されていた。これは、印刷時に半田ペーストがマスクの裏側に回り込んだためであると推定された。
また、導通試験に関しては、半田バンプ形成後は特に問題がなかったが、信頼性試験後には断線、短絡が発生した。また、断線と確認された部分の半田バンプの断面を観察すると、クラック、剥がれを引き起こしていた。
【０１７０】
また、比較例２の多層プリント配線板では、一回の印刷工程で粘度の高い半田ペーストのみを印刷しているため、ソルダーレジスト層の表面は殆ど汚染されていなかったものの、半田バンプには多くのボイドが形成されており、高さも実施例２と比べてバラツキが大きく、形状も一様でなかった。
また、導通試験に関しては、半田バンプ形成後は特に問題がなかったが、信頼性試験後には断線、短絡が発生した。また、断線と確認された部分の半田バンプの断面を観察すると、比較例１と比べて多くのクラックや剥がれが発生していた。これは、半田バンプ内のボイドから誘発されたものであると推定された。
【０１７１】
【発明の効果】
以上説明したように、本発明の多層プリント配線板の製造方法では、第一の半田ペースト印刷工程の後、半田ペーストの表面を平坦にし、その後、第二の半田ペースト印刷工程を行うため、均一な形状および高さを有するとともに、相互間で短絡のない半田バンプを形成することができ、接続性および信頼性に優れたプリント配線板を製造することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法における（ａ）〜（ｃ）の工程を模式的に示す部分断面図である。
【図２】（ａ）〜（ｂ）は、本発明の多層プリント配線板の製造方法において、半田ペーストを印刷する方法の一例を模式式に示す部分断面図である。
【図３】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図４】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図５】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図６】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図７】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図８】（ａ）〜（ｅ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図９】（ａ）〜（ｅ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図１０】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図１１】（ａ）〜（ｄ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図１２】（ａ）〜（ｃ）は、本発明の多層プリント配線板の製造方法の工程の一部を示す断面図である。
【図１３】本発明の製造方法により得られる多層プリント配線板の一例を模式的に示す断面図である。
【符号の説明】
１、３０ 基板
８、３２ 銅箔
４、３４ 下層導体回路
９、３６ スルーホール
６、５２ バイアホール用開口
１２、４２ 薄膜導体層（無電解めっき膜）
３、４３ めっきレジスト
１３、４４ 電解めっき膜
２、５０ 層間樹脂絶縁層
１０、５４ 樹脂充填材
５８ 蓋めっき層
１４、７０ ソルダーレジスト層
１７、７６ 半田バンプ
７８ 導電性ピン[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a printed wiring board characterized by a method of printing a solder paste in a solder bump forming opening of a solder resist layer.
[0002]
[Prior art]
A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like, on a resin board reinforced with a glass cloth of about 0.5 to 1.5 mm called a core, and copper It is produced by alternately laminating conductive circuits and interlayer resin insulation layers by the method described above. The connection between the conductor circuits through the interlayer resin insulating layer of the multilayer printed wiring board is made by via holes.
[0003]
Conventionally, a build-up multilayer printed wiring board is manufactured by a method disclosed in, for example, Japanese Patent Laid-Open No. 9-130050.
That is, first, a through hole is formed in a copper clad laminate on which a copper foil is attached, and then a through hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern using a photolithographic technique to form a conductor circuit. Next, a roughened surface is formed on the surface of the formed conductor circuit by electroless plating or etching, and an insulating resin layer is formed on the conductor circuit having the roughened surface, followed by exposure and development. Via hole openings are formed, and then an interlayer resin insulation layer is formed through UV curing and main curing.
[0004]
Further, after roughening the interlayer resin insulation layer with acid, oxidizing agent, etc., a thin electroless plating film is formed, a plating resist is formed on the electroless plating film, and then thickened by electrolytic plating. Etching is performed after the plating resist is peeled off to form a conductor circuit connected to the underlying conductor circuit by a via hole.
After repeating this process, a solder resist layer for protecting the conductor circuit is finally formed, and plating is applied to the exposed portions for connection to electronic components such as IC chips and motherboards, and soldering is performed. After forming the bump forming pads, a solder paste is printed on the electronic component side such as an IC chip to form solder bumps, thereby manufacturing a build-up multilayer printed wiring board. Further, if necessary, solder bumps are also formed on the mother board side.
[0005]
[Problems to be solved by the invention]
There are two types of solder bump forming pads formed on the solder resist layer: a flat one formed on a flat conductor circuit, and a one having a recess with a diameter of 10 to 120 μm in the center formed on a via hole. There is.
[0006]
The solder bump forming pad having a depression in the center may not be completely filled with the vicinity of the depression depending on the viscosity of the solder paste when the solder paste is filled. In some cases, voids are formed.
[0007]
The void formed in the solder bump diffuses or expands due to heat generated during reflow or when an electronic component such as an IC chip is operated. There was a problem that the pad was peeled off or cracked, adversely affecting the connectivity and reliability.
[0008]
In recent years, with the increase in density and integration of electronic components such as IC chips, the solder bumps on the board are also becoming narrower and finer, and the adverse effects of voids have become prominent. I came.
[0009]
As a method of reducing this void, a method of lowering the viscosity of the solder paste is conceivable. In this method, although the void of the solder bump is reduced, the uniformity of the shape and height of the solder bump is impaired, and the IC Problems such as poor connection with electronic components such as chips, and solder paste oozing onto the surface of the solder resist layer during printing, causing a short circuit between the solder bumps.
[0010]
In addition, by changing the opening diameter of the mask used during solder paste printing, changing the reflow conditions such as peak temperature, preheating temperature, and conveyor speed, and changing the printing conditions such as squeegee speed and printing pressure Although a method for reducing voids is conceivable, it has been difficult to obtain a desired result by such a method.
In recent years, due to the use of Pb-free solder, changing the solder paste from 63Sn / 37Pb to SnAg, SnAgCu, etc. has been studied, but it has been found that the occurrence rate of the hood increases as the Sn content increases.
[0011]
[Means for Solving the Problems]
As a result of diligent research in view of the above problems, the present inventors have performed solder paste printing at least twice, and after the solder bump forming openings are completely filled with the solder paste in the first solder paste printing, The surface of the solder paste is flattened, and the surface of the solder paste and the surface of the solder resist layer are made substantially flush with each other, and then the second solder paste printing is performed, so that the shape and height are excellent in uniformity. It was found that solder bumps can be formed, there is no short-circuit between each other, and a multilayer printed wiring board having solder bumps with excellent connection reliability with external connection parts can be manufactured. Reached the invention of composition.
[0012]
That is, in the method for manufacturing a printed wiring board of the present invention, after forming an interlayer resin insulation layer and a conductor circuit on a substrate on which a conductor circuit is formed, a plurality of solder bumps are formed on the uppermost conductor circuit. A method for producing a multilayer printed wiring board in which a solder resist layer having an opening is provided and a solder bump is formed by printing a solder paste on the solder bump forming opening,
at leastIncludes a first solder paste printing process and a second solder paste printing processThe solder paste is printed by performing the following steps (a) to (c).At this time, the viscosity of the solder paste printed in the first solder paste printing step is lower than the viscosity of the solder paste printed in the second solder paste printing step.It is characterized by that.
(A) Printing the solder paste one or more times to fill the concave solder bump forming openings with the solder pastethe aboveFirst solder paste printing process,
(B) a solder paste flattening step for flattening the surface of the solder paste filled in the step (a), and
(C) One or more times of solder paste printingthe aboveSecond solder paste printing process.
[0013]
In the first and second solder paste printing steps of the method for producing a multilayer printed wiring board of the present invention, a mask having an opening is placed on the solder resist layer at a portion facing the solder bump forming opening. After that, it is desirable to print a solder paste.
[0014]
In the method for manufacturing a multilayer printed wiring board, the opening diameter of the mask used in the first solder paste printing step and the opening of the mask used in the second solder paste printing step are set. The aperture diameter is the same, or the opening diameter of the mask used in the first solder paste printing process is larger than the opening diameter of the opening of the mask used in the second solder paste printing process. Small is desirable.
[0016]
Further, in the first solder paste printing step of the method for manufacturing a multilayer printed wiring board, only the opening for forming solder bumps having a depression on the bottom surface is filled with the depression by the first solder paste printing. It is desirable to print the solder paste to such an extent that the concave solder bump forming openings are completely filled in the second solder paste printing.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
In the printed wiring board manufacturing method of the present invention, an interlayer resin insulation layer and a conductor circuit are laminated on a substrate on which a conductor circuit is formed, and then a plurality of solder bump forming openings are formed on the uppermost conductor circuit. A method for producing a multilayer printed wiring board, wherein a solder resist layer is provided, and a solder bump is formed by printing a solder paste on the solder bump forming opening,
at leastIncludes a first solder paste printing process and a second solder paste printing processThe solder paste is printed by performing the following steps (a) to (c).At this time, the viscosity of the solder paste printed in the first solder paste printing step is lower than the viscosity of the solder paste printed in the second solder paste printing step.It is characterized by that.
(A) Printing the solder paste one or more times to fill the concave solder bump forming openings with the solder pastethe aboveFirst solder paste printing process,
(B) a solder paste flattening step for flattening the surface of the solder paste filled in the step (a), and
(C) One or more times of solder paste printingthe aboveSecond solder paste printing process.
[0018]
In the printed wiring board manufacturing method, after the first solder paste printing step, the surface of the solder paste is flattened, and then the second solder paste printing step is performed, so that it has a uniform shape and height, Solder bumps without a short circuit can be formed between each other, and a printed wiring board excellent in connectivity and reliability can be manufactured.
[0019]
Below, the manufacturing method of the printed wiring board of this invention is demonstrated.
In addition, the manufacturing method of the multilayer printed wiring board of this invention has the characteristics in the process of printing a solder paste in the opening for solder bump formation provided in the soldering resist layer, ie, the process of said (a)-(c). Therefore, first, this process will be described with reference to the drawings, and all manufacturing processes for manufacturing a multilayer printed wiring board will be described later.
[0020]
FIG. 1 is a partial cross-sectional view schematically showing steps (a) to (c) in the method for producing a multilayer printed wiring board of the present invention.
In the step (a) (first solder paste printing step), the solder paste layer 114 having the solder bump formation openings 106 is printed on the substrate having one or more solder pastes to form a concave solder. Solder paste 117 is filled in the bump forming openings 106 (see FIG. 1A). In the figure, 102 is an interlayer resin insulation layer, 105 is a conductor circuit, 107 is a via hole, and 116 is a solder pad.
In this step, the solder bump forming openings 106 are completely filled with the solder paste 117. In order to reliably fill the solder bump forming openings 106, a larger amount of solder paste than the volume of the solder bump forming openings is printed. Therefore, after the first solder paste printing process is completed, a part of the printed solder paste is raised from the surface of the solder resist layer (indicated as solder paste 1117 in the figure).
[0021]
In the first solder paste printing step, it is desirable to print a solder paste after placing a mask having an opening in a portion facing the solder bump forming opening on the solder resist layer.
By placing the mask and selectively printing the solder paste on the solder bump formation opening, the solder paste does not adhere to the surface of the solder resist layer except the wall surface of the solder bump formation opening. This is because it is not necessary to remove the solder paste attached to the surface of the solder resist layer.
[0022]
Moreover, it does not specifically limit as a kind of said mask, All the materials used with the printing mask for printed wiring board manufacture and other printing masks can be used.
Specifically, for example, a metal mask made of nickel alloy, nickel-cobalt alloy, SUS, or the like; a plastic mask made of epoxy resin, polyimide resin, or the like can be given. Further, examples of the mask manufacturing method include etching, additive processing, laser processing, and the like.
[0023]
Further, the opening of the mask may be formed so as to have a wall surface perpendicular to the solder resist layer, but it is desirable that a taper that gradually increases in diameter toward the solder resist layer is formed. . This is because the solder paste is excellent in detachability and the solder bump forming opening can be more reliably filled with the solder paste.
[0024]
Moreover, it does not specifically limit as a solder paste used at a 1st solder paste printing process, All the things generally used by manufacture of a printed wiring board can be used. Specifically, for example, Sn: Pb (weight ratio) = 63: 37, Sn: Pb: Ag = 62: 36: 2, Sn: Ag = 96.5: 3.5, etc. The thing which consists of Sb is mentioned. The particle diameter of the solder particles is preferably 2 to 40 μm, and more preferably 5 to 20 μm.
[0025]
The viscosity of the solder paste is preferably lower than the viscosity of the solder paste printed in the second solder paste printing step described later.
This is because by increasing the fluidity of the solder paste, the solder paste can be surely filled through the openings for forming solder bumps. In particular, it is possible to reliably fill the solder bump forming opening having a depression on the bottom surface.
In addition, when the solder bump forming opening is filled with a solder paste having high fluidity, voids are less likely to occur when the solder bump is formed.
Examples of the method for reducing the viscosity of the solder paste include a method of increasing the amount of solvent added to the solder paste, increasing the flux content, and reducing the particle size of the solder particles. The viscosity of the solder paste may be the same as the viscosity of the solder paste printed in the second solder paste printing step.
[0026]
In the first solder paste printing process, the solder paste is printed for the first time, and the solder paste is printed in such an amount that only the opening for forming the solder bump having the depression on the bottom surface is filled. Then, the solder paste may be printed so that the concave solder bump forming opening is completely filled by the second solder paste printing.
[0027]
The conductor circuit is exposed on the bottom surface of the solder bump forming opening formed in the solder resist layer. Usually, the exposed surface of the conductor circuit (bottom surface of the solder bump forming opening) is soldered by plating or the like. Bump forming pads (hereinafter also referred to as solder pads) are formed.
Here, when this solder pad is formed on the via hole of the conductor circuit, the shape of the solder pad has a depression in a part thereof.
When filling the solder bump forming opening having such a depression on the bottom surface with the solder paste, as described above, the solder paste printing is performed in two times, so that the solder paste is formed in the solder bump forming opening. Can be more reliably filled.
[0028]
Moreover, when printing a solder paste, a printing squeegee is usually used.
The material of the squeegee for printing is not particularly limited, and for example, a material generally used for printing a printed wiring board such as rubber such as polyethylene; metal such as iron or stainless steel; ceramic or the like can be used.
Among these, rubber having a hardness of 60 ° or more is desirable because it has elasticity and has high followability to unevenness (undulation) on the substrate surface, so that solder paste can be printed more reliably in the opening. Metals are desirable because they are less likely to lose weight and are less likely to contaminate the solder paste due to wear.
[0029]
Examples of the shape of the squeegee include various shapes such as a flat shape and a square shape. By filling the squeegee with the above shape in a timely manner, the filling property of the solder paste can be improved.
Although the thickness of the squeegee is not particularly limited, it is usually preferably 10 to 30 mm and more preferably 15 to 25 mm. This is because there is no warping or deflection even when printing is repeated. In the case of a metallic squeegee, the thickness is preferably 50 to 300 μm.
[0030]
The solder paste may be printed using a sealed squeegee unit. Examples of such a squeegee include an air press-fit type, a roller press-fit type, and a piston press-fit type. When forming a solder bump having a distance between adjacent solder bumps of 200 μm or less, a solder paste layer that can form such a solder bump is difficult to form using ordinary squeegee printing. It is desirable to form using a closed squeegee unit.
Further, among the above-described sealed squeegee units, a piston press-in type is desirable from the viewpoint of excellent printing pressure stability.
[0031]
After completion of the first solder paste printing step, the step (b) (solder paste flattening step) is performed.
In this step, when the first solder paste printing step is performed, the solder paste surface 117a is flattened by removing the portion of the solder paste 1117 raised from the surface of the solder resist layer, and the filled solder paste The surface 117a of the solder and the surface 114a of the solder resist layer are substantially flush with each other (see FIG. 1B).
[0032]
As a method of removing the solder paste 1117 in the portion raised from the surface of the solder resist layer, any method can be used as long as it can achieve the flattening of the surface of the solder paste as described above. It can be removed using cleaning paper or the like.
If the solder paste is attached to the surface of the solder resist layer excluding the wall surface of the solder bump forming opening, the attached solder paste may be removed in this step.
[0033]
In order to eliminate the need for this solder paste flattening step, the solder paste does not have a raised shape from the surface of the solder resist layer, and the solder paste has an amount that completely fills the solder bump forming openings. May be filled. However, in order to fill this amount of solder paste, the printing amount of the solder paste must be strictly controlled for each opening for forming the solder bumps, which increases the management items at the time of printing. Even if an error occurs, the error leads to a decrease in the quality of the multilayer printed wiring board. As a result, using such a method leads to a decrease in yield and is economically disadvantageous. It becomes.
Accordingly, although the number of processing steps is increased, the method of the present invention uses a method of removing the solder paste in a portion raised from the surface of the solder resist layer after printing a sufficient amount of solder paste to fill the opening. The method is more economical.
[0034]
After flattening the surface of the solder paste, the step (c) (second solder paste printing step) is performed on the solder bump formation opening filled with the solder paste in the steps (a) and (b). A solder paste layer is formed, and the solder bump 127 is formed by reflowing the printed solder paste (see FIG. 1C). The solder paste can be printed using a printing squeegee or a sealed squeegee unit as in the first solder paste printing step.
[0035]
In the second solder paste printing step, it is desirable to print a solder paste after placing a mask having an opening in a portion corresponding to a solder bump forming portion.
By performing printing using a mask, it is possible to form a solder paste layer having excellent uniformity in shape and height.
[0036]
As the type of mask used in the second solder paste printing step, the same mask as that used in the first solder paste printing step can be used.
As with the mask used in the first solder paste printing process, the mask used in the second solder paste printing process is also preferably formed with a taper that expands toward the solder resist layer.
[0037]
In the first and second solder paste printing steps, when printing a solder paste using a mask, the mask used in the first solder paste printing step and the mask used in the second solder paste printing step It is desirable that the opening diameter is the same or the mask used in the first solder paste printing process is smaller.
[0038]
When the opening diameters of the masks used in the first and second solder paste printing processes are the same, the same mask can be used in both processes, which is economically advantageous and the printing apparatus itself is It can be made compact.
[0039]
Further, when the opening diameter of the mask used in the first solder paste printing process is smaller than the opening diameter of the mask used in the second solder paste printing process, the following effects are obtained.
That is, the first solder paste printing step is a step performed to reliably fill the solder bump forming openings, and the extra printed solder paste is removed in a later step. Therefore, the smaller the opening diameter of the mask, the smaller the amount of solder paste to be printed, which makes it easier to remove the solder paste in a later process and the amount of solder paste to be removed can be reduced.
Further, by using a mask having an opening having a diameter slightly larger than the opening diameter of the solder bump forming opening, it is possible to cope with alignment misalignment during printing and to more reliably fill the solder paste. In some cases, a mask having an opening having the same diameter as the solder bump forming opening may be used. The alignment misalignment is a misalignment between the solder bump forming opening and the printed solder paste due to variations in the finishing accuracy of the substrate and the mask and the printing accuracy of the printing press.
[0040]
On the other hand, the second solder paste printing step is a step performed to form a solder paste layer having excellent uniformity in shape and height. In this step, as described later, it is desirable to print a solder paste having a high viscosity. Therefore, a solder paste layer having a desired shape can be formed by using a mask having an opening capable of printing a sufficient amount of solder paste.
[0041]
The composition of the solder paste used in the second solder paste printing step is not particularly limited, and examples thereof include the same solder paste used in the first solder paste printing step.
[0042]
Further, the viscosity of the solder paste printed in the second solder paste printing step is preferably the same as or higher than the viscosity of the solder paste printed in the first solder paste printing step, and the difference is 0 to 150 Pa · s is desirable, and 50 to 100 Pa · s is more desirable.
Specifically, the viscosity of the solder paste printed in the second solder paste printing step is desirably 150 to 350 Pa · s at 25 ° C. If the viscosity is less than 150 Pa · s, the solder paste cannot be printed in a desired shape, and solder bumps having a uniform shape cannot be formed, or the solder paste oozes onto the surface of the solder resist layer during printing. This may cause a short circuit of the formed solder bump. On the other hand, if the viscosity exceeds 350 Pa · s, it may not be possible to print the solder paste in a desired shape, especially when the solder paste is printed using a mask, because the solder paste has low detachability, A portion where the solder paste cannot be printed may occur.
[0043]
In the second solder paste printing step, the solder paste may be printed once or divided into a plurality of times.
Whether printing of solder paste is completed once or whether printing is performed multiple times depends on the distance between solder bumps to be formed, the height and shape of solder bumps, the composition of solder paste, the particle size of solder particles, etc. Although it cannot be said at a glance, for example, when the distance between the solder bumps to be formed is extremely narrow, it is desirable to perform the printing a plurality of times, especially when the solder paste is printed using a mask. It is desirable to perform printing once.
[0044]
This is because when a solder paste is printed by a single printing using a mask, if the distance between the solder bumps to be formed is narrow, the distance between the openings of the mask is also shortened. This is because the mechanical strength of the mask is weakened and the mask may be damaged or warped when the solder paste is printed.
In particular, when the opening of the mask has a taper having a shape that expands toward the back side of the mask, the mechanical strength of the mask is likely to be weakened.
[0045]
In the second solder paste printing step, as a specific method for printing the solder paste in a plurality of times, for example, a method described below can be used.
2A to 2B are cross-sectional views schematically showing an example of a method for printing a solder paste in the second solder paste printing step.
[0046]
As shown in FIG. 2 (a), a second solder paste is formed using a mask 224 in which openings are formed only in a portion facing a part of all the solder bump forming openings and the distance between the openings is wide. In the printing process, the first solder paste printing is performed to form the solder paste layer 227a. Next, as shown in (b), in the second printing, the solder bump formation openings are not printed in the first time. A printing process is performed using a mask 225 in which an opening is formed in an opposite portion, and a solder paste layer 227b is formed.
[0047]
In such a mask in which the distance between the openings is wide, the mechanical strength of the mask can be kept sufficiently high.
Here, “the distance between the openings is wide” means that the distance between the openings of the mask is wide compared to the case where the openings are formed in a portion of the mask facing the openings for forming all solder bumps. Means that
[0048]
Specifically, when the second solder paste printing process is performed using a mask, for example, in the first printing, a mask having an opening at a portion facing the opening for forming solder bumps is used. A solder paste layer is formed on the solder bump forming openings in the row, and a solder paste layer is formed on the remaining solder bump forming openings by the second printing.
[0049]
In the second and subsequent printings, it is desirable to use a mask in which a concave portion (hereinafter also referred to as “zakuri”) is formed on the back side of the mask facing the previously formed solder paste layer.
By using the mask 225 on which the counterbore 225a is formed (see FIG. 2B), the solder paste layer 227a printed by the mask 225 is not damaged, and the solder paste adheres to the back side of the mask. This is because a short circuit due to adhering to the surface of the solder resist layer 214 can be prevented.
[0050]
By passing through the steps (a) to (c), a solder paste layer is provided for providing solder bumps that are excellent in uniformity in shape and height and do not cause a short circuit between each other. be able to.
[0051]
Next, all the manufacturing processes of the manufacturing method of the multilayer printed wiring board of this invention are demonstrated in order of a process.
(1) In the method for producing a multilayer printed wiring board of the present invention, first, a conductor circuit is formed on a substrate.
Specifically, for example, after forming a solid conductor layer by performing electroless plating treatment on both surfaces of the substrate, an etching resist corresponding to the conductor circuit pattern is formed on the conductor layer, and then etching is performed. What is necessary is just to form by performing.
In addition, after giving an electroless-plating process, you may thicken the thickness of a conductor layer by giving electrolytic plating.
As the substrate, a resin substrate is desirable, and specific examples include a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine resin substrate (BT resin substrate), a fluororesin substrate, and the like.
Moreover, you may use a copper clad laminated board, a RCC board | substrate, etc. as a board | substrate with which the solid conductor layer was formed.
[0052]
In addition, when performing the electroless plating process, if necessary, a through hole is formed in the insulating substrate in advance, and the wall surface of the through hole is also subjected to the electroless plating process, thereby It is good also as a through hole which electrically connects between the interposed conductor circuits.
Further, when a through hole is formed, it is desirable to fill the through hole with a resin filler.
[0053]
(2) Next, the surface of the conductor circuit is roughened as necessary. Examples of the roughening treatment method include blackening (oxidation) -reduction treatment, etching treatment using a mixed solution containing an organic acid and a cupric complex, treatment by Cu-Ni-P needle alloy plating, and the like. Can be used.
[0054]
(3) Next, an uncured resin layer made of a thermosetting resin or a resin composite is formed on the conductor circuit, or a resin layer made of a thermoplastic resin is formed.
The uncured resin insulation layer may be formed by applying uncured resin with a roll coater, curtain coater, or the like, or by thermocompression bonding of an uncured (semi-cured) resin film. Good. Furthermore, you may affix the resin film in which metal layers, such as copper foil, were formed in the single side | surface of an uncured resin film.
The resin layer made of a thermoplastic resin is preferably formed by thermocompression bonding a resin molded body formed into a film shape.
[0055]
In the case of applying the uncured resin, the resin is applied and then heat treatment is performed.
By performing the heat treatment, the uncured resin can be thermoset.
In addition, you may perform the said thermosetting, after forming the opening for via holes and a through-hole which are mentioned later.
[0056]
Specific examples of the thermosetting resin used in the formation of such a resin layer include, for example, epoxy resins, phenol resins, polyimide resins, polyester resins, bismaleimide resins, polyolefin resins, polyphenylene ether resins, and the like.
[0057]
Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.
[0058]
Examples of the polyolefin resin include polyethylene, polystyrene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.
Among these, the dielectric constant and dielectric loss tangent are low, and even when a high frequency signal in the GHz band is used, signal delay and signal error are not easily generated. Olefin resins are desirable.
[0059]
As the cycloolefin-based resin, a homopolymer or copolymer of a monomer composed of 2-norbornene, 5-ethylidene-2-norbornene, or a derivative thereof is desirable. Examples of the derivative include those in which an amino group for forming a bridge, a maleic anhydride residue, or a maleic acid-modified one is bonded to the cycloolefin such as 2-norbornene.
Examples of the monomer for synthesizing the copolymer include ethylene and propylene.
The polyolefin resin may contain an organic filler.
[0060]
Examples of the polyphenylene ether resin include a thermoplastic polyphenylene ether resin having a repeating unit represented by the following chemical formula (1) and a thermosetting polyphenylene ether resin having a repeating unit represented by the following chemical formula (2). It is done.
[0061]
[Chemical 1]

[0062]
(In the formula, n represents an integer of 2 or more.)
[0063]
[Chemical 2]

[0064]
(In the formula, m represents an integer of 2 or more. Also, R¹ , R² Is a methylene group, ethylene group or -CH₂ -O-CH₂ -Represents that both may be the same or different. )
[0065]
In addition, the thermoplastic polyphenylene ether resin having a repeating unit represented by the chemical formula (1) has a structure in which a methyl group is bonded to a benzene ring, but as a polyphenylene ether resin that can be used in the present invention, Further, a derivative in which the methyl group is substituted with another alkyl group such as an ethyl group, a derivative in which hydrogen of the methyl group is substituted with fluorine, or the like may be used.
[0066]
Examples of the thermoplastic resin include polyether sulfone and polysulfone.
Further, the composite of the thermosetting resin and the thermoplastic resin (resin composite) is not particularly limited as long as it includes a thermosetting resin and a thermoplastic resin. Specific examples thereof include, for example, Examples thereof include a resin composition for forming a roughened surface.
[0067]
Examples of the roughened surface-forming resin composition include, in an uncured heat-resistant resin matrix that is hardly soluble in a roughened liquid consisting of at least one selected from an acid, an alkali, and an oxidizing agent. And a material in which a substance soluble in a roughening liquid comprising at least one selected from oxidizing agents is dispersed.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.
[0068]
The heat resistant resin matrix is preferably one that can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using the roughening liquid, for example, a thermosetting resin, a thermoplastic resin. Examples thereof include resins and composites thereof. Photosensitive resin may also be used. This is because the opening can be formed by exposure and development processing in a step of forming a via hole opening to be described later.
[0069]
Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. Moreover, when sensitizing the said thermosetting resin, methacrylic acid, acrylic acid, etc. are used, and a thermosetting group is (meth) acrylated. In particular, (meth) acrylate of epoxy resin is desirable. Furthermore, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-mentioned roughened surface be formed, but also has excellent heat resistance, etc., so that stress concentration does not occur in the conductor circuit even under heat cycle conditions, and the conductor circuit and the interlayer resin insulation layer Peeling hardly occurs between
[0070]
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like. These may be used alone or in combination of two or more.
[0071]
The substance soluble in the roughening liquid consisting of at least one selected from the acid, alkali and oxidizing agent is at least one selected from inorganic particles, resin particles, metal particles, rubber particles, liquid phase resin and liquid phase rubber. It is desirable to be a seed.
[0072]
Examples of the inorganic particles include aluminum compounds, calcium compounds, potassium compounds, magnesium compounds, and silicon compounds. These may be used alone or in combination of two or more.
[0073]
Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and calcium hydroxide. Examples of the potassium compound include potassium carbonate. Examples of the magnesium compound include magnesia, dolomite, basic magnesium carbonate, and talc. Examples of the silicon compound include silica and zeolite. These may be used alone or in combination of two or more.
[0074]
The alumina particles can be dissolved and removed with hydrofluoric acid, and calcium carbonate can be dissolved and removed with hydrochloric acid. Sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.
[0075]
Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the resin particles are immersed in a roughening solution made of at least one selected from an acid, an alkali, and an oxidizing agent, the heat resistance It is not particularly limited as long as it has a faster dissolution rate than the resin matrix. Specifically, for example, amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, Examples include polyphenylene resin, polyolefin resin, fluororesin, and bismaleimide-triazine resin. These may be used alone or in combination of two or more.
[0076]
The resin particles must be previously cured. If not cured, the resin particles are dissolved in a solvent that dissolves the resin matrix, so they are uniformly mixed, and only the resin particles cannot be selectively dissolved and removed with an acid or an oxidizing agent. is there.
[0077]
Examples of the metal particles include gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead, and the like. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.
[0078]
Examples of the rubber particles include acrylonitrile-butadiene rubber, polychloroprene rubber, polyisoprene rubber, acrylic rubber, polysulfuric rigid rubber, fluorine rubber, urethane rubber, silicone rubber, ABS resin, and the like.
[0079]
In addition, as the rubber particles, for example, polybutadiene rubber, various modified polybutadiene rubbers such as epoxy modification, urethane modification, (meth) acrylonitrile modification, (meth) acrylonitrile / butadiene rubber containing a carboxyl group, and the like can be used.
These soluble substances may be used alone or in combination of two or more.
[0080]
As the liquid phase resin, an uncured solution of the thermosetting resin can be used. As a specific example of such a liquid phase resin, for example, a mixed liquid of an uncured epoxy oligomer and an amine curing agent. Etc.
Examples of the liquid phase rubber include various polybutadiene rubbers such as the above polybutadiene rubber, epoxy modification, urethane modification, (meth) acrylonitrile modification, uncured solutions such as (meth) acrylonitrile / butadiene rubber containing a carboxyl group, etc. Can be used.
[0081]
When preparing the photosensitive resin composition using the liquid phase resin or liquid phase rubber, so that the heat resistant resin matrix and the soluble substance are not compatible with each other uniformly (that is, so as to phase-separate), It is necessary to select these substances.
By mixing the heat-resistant resin matrix selected according to the above criteria and a soluble substance, the liquid-phase resin or liquid-phase rubber “islands” are dispersed in the “sea” of the heat-resistant resin matrix. Alternatively, it is possible to prepare a photosensitive resin composition in which “islands” of a heat-resistant resin matrix are dispersed in a “sea” of a liquid phase resin or a liquid phase rubber.
[0082]
(4) Next, when forming an interlayer resin insulation layer using a thermosetting resin or a resin composite as the material, the uncured resin insulation layer is cured and a via hole opening is formed. And an interlayer resin insulation layer.
The via hole opening is preferably formed by laser processing. The laser treatment may be performed before the curing treatment or after the curing treatment.
When an interlayer resin insulating layer made of a photosensitive resin is formed, a via hole opening may be provided by performing exposure and development processes. In this case, the exposure and development processes are performed before the curing process.
[0083]
When an interlayer resin insulation layer using a thermoplastic resin as the material is formed, a via hole opening can be formed in the resin layer made of the thermoplastic resin by laser processing to form an interlayer resin insulation layer. .
[0084]
At this time, examples of the laser to be used include a carbon dioxide laser, an excimer laser, a UV laser, and a YAG laser.
These lasers may be properly used in consideration of the shape of the via hole opening to be formed.
[0085]
In the case of forming the via hole openings, a large number of via hole openings can be formed at a time by irradiating laser light with a hologram type excimer laser through a mask.
In addition, when a via hole opening is formed using a short pulse carbon dioxide laser, there is little resin residue in the opening, and damage to the resin at the periphery of the opening is small.
[0086]
In addition, by irradiating laser light through an optical system lens and a mask, a large number of openings for via holes can be formed at one time.
This is because laser light having the same intensity and the same irradiation angle can be simultaneously irradiated to a plurality of portions through the optical system lens and the mask.
[0087]
The through hole formed in the mask is preferably a perfect circle in order to make the spot shape of the laser beam a perfect circle, and the diameter of the through hole is preferably about 0.1 to 2 mm.
When the carbon dioxide laser is used, the pulse interval is 10^-Four-10^-8It is desirable to be seconds. Moreover, it is desirable that the time for irradiating the laser for forming the opening is 10 to 500 μsec.
When the via hole opening is formed by laser light, especially when a carbon dioxide laser is used, it is desirable to perform desmear treatment.
[0088]
The thickness of the interlayer resin insulation layer formed by the above method is not particularly limited, but is preferably 5 to 50 μm.
Moreover, the opening diameter of the opening for the via hole is not particularly limited, but is usually preferably 40 to 200 μm.
[0089]
Further, after forming the interlayer resin insulation layer, if necessary, a through-hole penetrating the interlayer resin insulation layer and the substrate may be formed. The through hole may be formed using drilling, laser processing, or the like.
When such a through hole is formed, when a thin film conductor layer is formed on the surface of the interlayer resin insulation layer in a later step, the thin film conductor layer is also formed on the wall surface of the through hole, thereby In addition to the two-layer conductor circuit sandwiching the interlayer resin insulation layer, the two-layer conductor circuit and the two-layer conductor circuit formed on both sides of the substrate are electrically connected between the four-layer conductor circuits. Through-holes connected to can be formed. By connecting the conductor circuits in this way, the signal transmission distance can be shortened, so that signal delay or the like hardly occurs and the performance of the multilayer printed wiring board is improved.
[0090]
(5) Next, if necessary, an acid or an oxidizing agent is used for the surface of the interlayer resin insulating layer including the inner wall of the opening for the via hole and the inner wall of the through hole in the case where the through hole is formed in the above process. To form a roughened surface.
Examples of the acid include sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, formic acid, and examples of the oxidizing agent include permanganates such as chromic acid, chromium sulfuric acid, and sodium permanganate.
In addition, the roughened surface may be formed using plasma treatment or the like.
[0091]
In addition, after the roughened surface is formed, it is desirable to neutralize the surface of the interlayer resin insulation layer using an aqueous solution such as an alkali or a neutralizing solution.
This is because the next step can be prevented from being affected by an acid or an oxidizing agent.
[0092]
(6) Next, an acid, an oxidant, or the like, if necessary, on the surface of the interlayer resin insulating layer including the inner wall of the opening for the via hole and the inner wall of the through hole when the through hole is formed in the above process Is used to form a roughened surface.
This roughened surface is formed in order to improve the adhesion between the interlayer resin insulation layer and the thin film conductor layer formed thereon, and provides sufficient adhesion between the interlayer resin insulation layer and the thin film conductor layer. If there is a property, it may not be formed.
[0093]
(7) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulating layer provided with the via hole opening.
The thin film conductor layer can be formed using a method such as electroless plating, sputtering, or vapor deposition. When the roughened surface is not formed on the surface of the interlayer resin insulating layer, the thin film conductor layer is preferably formed by sputtering.
In addition, when forming a thin film conductor layer by electroless plating, the catalyst is previously provided to the to-be-plated surface. Examples of the catalyst include palladium chloride.
[0094]
The thickness of the thin film conductor layer is not particularly limited, but when the thin film conductor layer is formed by electroless plating, 0.6 to 1.2 μm is desirable, and when formed by sputtering, 0.1 to 0.1 μm is preferable. 1.0 μm is desirable.
When the through hole is formed in the step (4), a through hole can be formed by forming a thin film conductor layer made of metal on the inner wall surface of the through hole in this step.
[0095]
Further, when a thin film conductor layer is formed on the inner wall surface of the through hole as described above to form a through hole, it is desirable that the through hole is filled with a resin filler thereafter. Examples of the resin filler include a resin composition containing an epoxy resin, a curing agent, and inorganic particles.
[0096]
Further, when the through hole is filled with the resin filler, a lid plating layer covering the resin filler may be formed on the through hole. When the lid plating layer is formed, the lid plating layer Via holes and solder pads can be formed directly above, so that the signal transmission distance can be shortened.
[0097]
(8) Next, a plating resist is formed on a part of the thin film conductor layer using a dry film, and then electroplating is performed using the thin film conductor layer as a plating lead, and the plating resist non-formed portion is electroplated. Form a layer.
At this time, the via hole opening may be filled with electroplating to form a field via structure, or after filling the via hole opening with a conductive paste, a lid plating layer may be formed thereon to form a field via structure. .
[0098]
(9) After the electroplating layer is formed, the plating resist is peeled off, and the thin film conductor layer made of metal existing under the plating resist is removed by etching to form an independent conductor circuit.
Examples of the etchant include sulfuric acid-hydrogen peroxide aqueous solution, persulfate aqueous solution such as ammonium persulfate, ferric chloride, cupric chloride, hydrochloric acid and the like. Moreover, you may use the mixed solution containing the cupric complex mentioned above and organic acid as etching liquid.
[0099]
Moreover, it may replace with the method described in said (8) and (9), and may form a conductor circuit by using the following method.
That is, after an electroplating layer is formed on the entire surface of the thin film conductor layer, an etching resist is formed on a part of the electroplating layer using a dry film, and then the electroplating layer under the non-etching resist forming portion and An independent conductor circuit may be formed by removing the thin film conductor layer by etching and further removing the etching resist.
[0100]
(10) Thereafter, by repeating the steps (3) to (9), a substrate having the uppermost conductor circuit formed on the interlayer resin insulation layer is produced.
[0101]
(11) Next, a solder resist layer having a plurality of solder bump forming openings is formed on the substrate including the uppermost conductor circuit.
Specifically, after applying an uncured solder resist composition with a roll coater or curtain coater, or after crimping a solder resist composition formed into a film, solder bumps are formed by laser processing or exposure development processing. A solder resist layer is formed by forming an opening for use and, if necessary, performing a curing treatment.
[0102]
The solder resist layer can be formed using, for example, a solder resist composition containing a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, an epoxy resin, a polyimide resin, and the like as specific examples of these resins. For example, the same resin as the resin used for the interlayer resin insulating layer can be used.
[0103]
Examples of solder resist compositions other than those described above include, for example, (meth) acrylates of novolak epoxy resins, imidazole curing agents, bifunctional (meth) acrylic acid ester monomers, and (meth) acrylic acid having a molecular weight of about 500 to 5,000. Examples include paste polymers containing ester polymers, thermosetting resins composed of bisphenol-type epoxy resins, photosensitive monomers such as polyvalent acrylic monomers, glycol ether solvents, and the viscosity at 25 ° C. It is desirable that the pressure is adjusted to 1 to 10 Pa · s.
Examples of the (meth) acrylate of the novolak type epoxy resin include an epoxy resin obtained by reacting a glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid.
[0104]
The bifunctional (meth) acrylic acid ester monomer is not particularly limited, and examples thereof include acrylic acid and methacrylic acid esters of various diols, and commercially available products thereof include R- manufactured by Nippon Kayaku Co., Ltd. 604, PM2, PM21 and the like.
[0105]
The solder resist composition may contain an elastomer or an inorganic filler.
When the elastomer is blended, the formed solder resist layer absorbs or relieves stress even when stress acts on the solder resist layer due to the flexibility and rebound resilience of the elastomer. As a result, it is possible to suppress the occurrence of cracks and peeling in the solder resist layer after mounting electronic components such as IC chips on the manufacturing process of the multilayer printed wiring board and the manufactured multilayer printed wiring board. Even when this occurs, the crack hardly grows.
[0106]
Further, examples of the laser used when forming the solder bump forming opening include the same lasers as those used when forming the above-described via hole opening.
[0107]
Next, if necessary, solder pads are formed on the surface of the conductor circuit exposed at the bottom surface of the solder bump forming opening.
The solder pad can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, or platinum.
Specifically, it is desirable to form with a metal such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
The solder pad can be formed by using, for example, a method such as plating, vapor deposition, or electrodeposition. Among these, plating is preferable because the uniformity of the coating layer is excellent.
[0108]
(12) Next, a solder paste layer is formed on the solder resist layer having a solder pad on the bottom surface of the solder bump forming opening by performing the steps (a) to (c). A solder paste is formed by reflowing the layer.
The reflow process may be performed after the first and second solder paste printing processes are completed, or may be performed once after the first solder paste printing process is completed, and may be performed again after the second solder paste printing process is completed. Good.
[0109]
Further, before the reflow process is performed on the solder paste layer formed in the second solder paste printing step, a conductive pin is attached to the solder paste layer in advance, and a PGA (Pin Grid Array for connecting to an external terminal). ) May be formed.
In addition, plasma treatment with oxygen, carbon tetrachloride, or the like may be performed in a timely manner for a character printing process for forming product recognition characters or the like or for modifying the solder resist layer.
[0110]
【Example】
Hereinafter, the present invention will be described in more detail.
Example 1
A. Preparation of resin film for interlayer resin insulation layer
30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy Co., Ltd.), 40 parts by weight of cresol novolac type epoxy resin (epoxy equivalent 215, Epiklon N-673 manufactured by Dainippon Ink & Chemicals, Inc.), triazine 30 parts by weight of a structure-containing phenol novolak resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 manufactured by Dainippon Ink & Chemicals, Inc.) was dissolved in 20 parts by weight of ethyl diglycol acetate and 20 parts by weight of solvent naphtha with stirring. Thereto, terminal epoxidized polybutadiene rubber (Nagase Kasei Kogyo Denarex R-45EPT) 15 parts by weight, 2-phenyl-4,5-bis (hydroxymethyl) imidazole pulverized product 1.5 parts by weight, finely pulverized silica 2 parts by weight , Silicon Added to prepare an epoxy resin composition agent 0.5 parts by weight.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.
[0111]
B. Preparation of resin composition for filling through-hole
100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), SiO having an average particle diameter of 1.6 μm and a maximum particle diameter of 15 μm or less coated with a silane coupling agent on the surface₂ By taking 72 parts by weight of spherical particles (manufactured by Adtech, CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Perenol S4, manufactured by San Nopco) in a container, the viscosity is 30 to 25 ° C. at 25 ± 1 ° C. An 80 Pa · s resin filler was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.
[0112]
C. Method for manufacturing printed wiring board
(1) A copper-clad laminate in which 18 μm copper foil 8 is laminated on both surfaces of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material (FIG. 3 ( a)). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern to form the lower conductor circuits 4 and the through holes 9 on both surfaces of the substrate 1.
[0113]
(2) The substrate on which the through hole 9 and the lower conductor circuit 4 are formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂ (40 g / l), Na_Three PO_Four Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH_Four Reduction treatment using an aqueous solution containing (6 g / l) as a reducing bath was performed, and roughened surfaces 4a and 9a were formed on the entire surface of the lower conductor circuit 4 including the through holes 9 (see FIG. 3B).
[0114]
(3) Next, after preparing the resin composition for filling through-holes described in B above, within 24 hours after adjustment by the following method, in the through-hole 9 and on one side of the substrate 1, no conductor circuit is formed. A layer of the resin filler 10 was formed on the outer edge of the conductor circuit 4.
That is, first, the resin composition for filling a through hole was pushed into the through hole using a squeegee and then dried at 100 ° C. for 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-forming portion is placed on the substrate, and a layer of the resin filler 10 is formed on the conductor circuit non-forming portion which is a concave portion using a squeegee. The film was dried at 20 ° C. for 20 minutes (see FIG. 3C).
[0115]
(4) One side of the substrate after the processing of (3) above is applied to the surface of the inner layer copper pattern 4 or the land surface of the through hole 9 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that the resin filler 10 did not remain, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, the resin filler 10 was cured by heat treatment at 100 ° C. for 1 hour and 150 ° C. for 1 hour.
[0116]
In this way, the surface layer portion of the resin filler 10 and the surface of the lower conductor circuit 4 formed in the through hole 9 and the conductor circuit non-forming portion are flattened, and the resin filler 10 and the side surface 4a of the lower conductor circuit 4 are formed. An insulating substrate was obtained in which the inner wall surface 9a of the through hole 9 and the resin filler 10 were firmly adhered through the roughened surface (see FIG. 3D). . That is, by this step, the surface of the resin filler 10 and the surface of the lower conductor circuit 4 are flush.
[0117]
(5) After washing the substrate with water and acid degreasing, soft etching is performed, and then an etching solution is sprayed on both sides of the substrate to spray the surface of the lower conductor circuit 4, the land surface of the through hole 9, and the inner wall. Thus, roughened surfaces 4a and 9a were formed on the entire surface of the lower conductor circuit 4 (see FIG. 4A). As an etching solution, an etching solution (MEC Etch Bond, manufactured by MEC Co., Ltd.) composed of 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.
[0118]
(6) On both surfaces of the substrate, a resin film for an interlayer resin insulation layer that is slightly larger than the substrate prepared in A above is placed on the substrate, temporarily under the conditions of pressure 0.4 MPa, temperature 80 ° C., and pressure bonding time 10 seconds. After crimping and cutting, the interlayer resin insulation layer 2 was further formed by pasting using a vacuum laminator apparatus by the following method and then thermosetting (see FIG. 4B). That is, a resin film for an interlayer resin insulation layer is stuck on the substrate under the conditions of a degree of vacuum of 67 Pa, a pressure of 0.4 MPa, a temperature of 80 ° C., a pressure bonding time of 60 seconds, and then thermally cured at 170 ° C. for 30 minutes. It was.
[0119]
(7) Next, CO 2 having a wavelength of 10.4 μm is passed through a mask in which a through hole having a thickness of 1.2 mm is formed on the interlayer resin insulation layer 2.₂ With a gas laser, a via hole with a diameter of 75 μm is formed in the interlayer resin insulating layer 2 under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a mask through-hole diameter of 1.0 mm, and one shot. 6 was formed (see FIG. 4C).
[0120]
(8) Furthermore, the substrate on which the via hole opening 6 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve the epoxy resin particles present on the surface of the interlayer resin insulation layer 2 By removing, the surface of the interlayer resin insulating layer 2 including the inner wall of the via hole opening 6 was made rough (see FIG. 4D).
[0121]
(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, a palladium catalyst (manufactured by Atotech) is applied to the surface of the substrate that has been roughened (roughening depth: 3 μm), so that the surface of the interlayer resin insulation layer 2 and the inner wall surface of the via hole opening 6 are applied. A catalyst nucleus was deposited.
[0122]
(10) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form an electroless copper plating layer 12 having a thickness of 0.6 to 3.0 μm over the entire rough surface (FIG. 5 ( a)).
[Electroless plating aqueous solution]
NiSO_Four                 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature
[0123]
(11) A commercially available photosensitive dry film is affixed to the electroless copper plating layer 12 and a mask is placed thereon, and 100 mJ / cm.² The plating resist 3 having a thickness of 20 μm was provided by developing with a 0.8% sodium carbonate aqueous solution (see FIG. 5B).
[0124]
(12) Next, the substrate is washed with 50 ° C. water, degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. It formed (refer FIG.5 (c)).
(Electrolytic plating aqueous solution)
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside HL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0125]
(13) Further, after removing the plating resist 3 with 5% NaOH aqueous solution, the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. An independent upper layer conductor circuit 5 (including the via hole 7) having a thickness of 18 μm made of the copper plating film 12 and the electrolytic plating film 13 was formed (see FIG. 5D).
[0126]
(14) By repeating the steps (5) to (13), an upper interlayer resin insulation layer 2 and an upper conductor circuit 5 (including via holes 7) are further formed (FIG. 6 (a) to FIG. 6). FIG. 7 (a)).
Thereafter, a roughened surface was formed on the surface of the upper conductor circuit 5 using an etching solution. As an etchant, MEC etch bond manufactured by MEC was used (see FIG. 7B).
[0127]
(15) Next, a photosensitizing agent obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 15.0 parts by weight of 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, imidazole curing agent (Shikoku 1.6 parts by weight manufactured by Kasei Co., Ltd., trade name: 2E4MZ-CN), 3.0 parts by weight of polyvalent acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604), which is a photosensitive monomer, Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoam (San Nopco, S-65) 0.7 Part by weight is placed in a container, and a mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator and Michler's ketone as a photosensitizer are mixed with this mixture composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C.
The viscosity is measured with a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) for 60 minutes.^-1(Rpm), rotor No. 4, 6 min^-1(Rpm), rotor No. 3 according.
[0128]
(16) Next, the solder resist composition is applied to both surfaces of the multilayer wiring board at a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the solder pad A photomask with a thickness of 5 mm on which a pattern of 10 mm was drawn was brought into close contact with the solder resist layer and 1000 mJ / cm² Were exposed to UV light and developed with DMTG solution to form an opening having a diameter of 80 μm.
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. Then, a solder resist layer 14 having a thickness of 20 μm was formed. The opening diameter of the solder bump forming openings is 80 μm, and the distance between adjacent solder bump forming openings is 150 μm.
Moreover, as said solder resist composition, a commercially available solder resist composition can also be used.
[0129]
(17) Next, an etching solution containing sodium persulfate as a main component is prepared so that the etching ability is about 2 μm per minute, and the substrate on which the solder resist layer 14 is formed in this etching solution is applied for 1 minute. Immersion was performed to form a roughened surface having an average roughness (Ra) of 1 μm or less on the surface of the conductor circuit.
Further, this substrate was made of nickel chloride (2.3 × 10^-1mol / l), sodium hypophosphite (2.8 × 10^-1mol / l), sodium citrate (1.6 × 10^-1The nickel plating layer 15 having a thickness of 5 μm was formed in the opening by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Further, the substrate was made of potassium gold cyanide (7.6 × 10 6^-3mol / l), ammonium chloride (1.9 × 10^-1mol / l), sodium citrate (1.2 × 10^-1mol / l), sodium hypophosphite (1.7 × 10^-1mol / l) is immersed in an electroless gold plating solution at 80 ° C. for 7.5 minutes to form a 0.03 μm-thick gold plating layer 16 on the nickel plating layer 15 as a solder pad. .
[0130]
(18) Thereafter, on the solder resist layer 14, a mask having an opening with a diameter of 100 μm is placed on the part facing all the solder bump forming openings, and a concave shape is formed by using a piston type press-fitting printer. The openings for forming solder bumps were completely filled with solder paste.
In addition, the solder paste filled here contains a solder having a particle size of 5 to 20 μm in which Sn: Ag is mixed in a weight ratio of 96.5: 3.5, and the viscosity is adjusted to 200 Pa · s. It is.
[0131]
(19) Next, of the solder paste filled in the step (18), the portion of the solder paste raised from the surface of the solder resist layer is removed using a stainless steel squeegee or a flat rubber squeegee having a hardness of 90 °. Thus, the surface of the filled solder paste was flattened, and the surface of the solder paste and the surface of the solder resist layer were made flush.
[0132]
(20) Next, a mask similar to the mask used in the step (18) is placed on the solder resist layer 14, and the solder paste layer is printed by printing the solder paste with a piston press-fitting printer. Formed.
In addition, the solder paste filled here contains solder with a particle size of 5 to 20 μm, which is mainly mixed with Sn: Ag in a weight ratio of 96.5: 3.5, and its viscosity is adjusted to 250 Pa · s. It is.
[0133]
(21) Thereafter, the solder paste printed in the above steps (18) to (20) is reflowed at 250 ° C., and further, flux cleaning is performed to obtain a multilayer printed wiring board provided with solder bumps (see FIG. 7 (c)).
[0134]
(Example 2)
A. In the same manner as in Example 1, a resin film for an interlayer resin insulation layer was prepared and a resin composition for filling a through hole was prepared.
[0135]
B. Manufacture of multilayer printed wiring boards
(1) A copper-clad laminate in which 18 μm copper foil 32 is laminated on both surfaces of an insulating substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm was used as a starting material (see FIG. 8 (a)). First, the copper-clad laminate was etched into a lower conductor circuit pattern to form lower conductor circuits 34 on both sides of the substrate (see FIG. 8B).
[0136]
(2) The substrate 30 on which the lower conductor circuit 34 is formed is washed with water and dried, followed by NaOH (10 g / l), NaClO₂ (40 g / l), Na_Three PO_Four Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH_Four Reduction treatment using an aqueous solution containing (6 g / l) as a reduction bath was performed to form a roughened surface 34a on the surface of the lower conductor circuit 34 (see FIG. 8C).
[0137]
(3) Next, the resin film for an interlayer resin insulation layer prepared in A above was laminated by vacuum compression bonding at 0.5 MPa while raising the temperature to 50 to 150 ° C., thereby forming a resin film layer 50α. (See FIG. 8D).
Furthermore, a through hole 35 having a diameter of 300 μm was formed by drilling in the substrate 30 to which the resin film layer 50α was attached (see FIG. 8E).
[0138]
(4) Next, through a mask in which a through hole having a thickness of 1.2 mm is formed on the resin film layer 50α, CO having a wavelength of 10.4 μm₂ With a gas laser, a via hole opening 52 with a diameter of 75 μm is formed in the resin film layer 50α under the conditions of a beam diameter of 4.0 mm, a top hat mode, a pulse width of 8.0 μsec, a mask through-hole diameter of 1.0 mm, and one shot. To form an interlayer resin insulation layer 50 (see FIG. 9A).
[0139]
(5) The substrate on which the via hole opening 52 is formed is dipped in an 80 ° C. solution containing 60 g / l permanganic acid for 10 minutes, and the wall surface of the through-hole 35 is subjected to desmear treatment, and the interlayer resin insulating layer 50 By dissolving and removing the epoxy resin particles present on the surface, roughened surfaces 50a and 52a were formed on the surface including the inner wall surface of the via hole opening 52 (see FIG. 9B).
[0140]
(6) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Furthermore, the surface of the interlayer resin insulation layer 50 (including the inner wall surface of the via hole opening 52) is provided by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth 3 μm), and Catalyst nuclei were attached to the wall surface of the through hole 35 (not shown). That is, the substrate is made of palladium chloride (PbCl₂ ) And stannous chloride (SnCl)₂ The catalyst was imparted by immersing it in a catalyst solution containing) and depositing palladium metal.
[0141]
(7) Next, the substrate is immersed in an electroless copper plating aqueous solution having the following composition, and the surface of the interlayer resin insulation layer 50 (including the inner wall surface of the via hole opening 52) and the wall surface of the through hole 35 Then, an electroless copper plating film 42 having a thickness of 0.6 to 3.0 μm was formed (see FIG. 9C).
[Electroless plating aqueous solution]
NiSO_Four                   0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 100 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 34 ° C liquid temperature
[0142]
(8) Next, a commercially available photosensitive dry film is attached to the substrate on which the electroless copper plating film 42 is formed, and a mask is placed thereon, and 100 mJ / cm.² Then, a plating resist 43 having a thickness of 20 μm was provided by developing with a 0.8% sodium carbonate aqueous solution (see FIG. 9D).
[0143]
(9) Next, the substrate is washed with 50 ° C. water, degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions to form a plating resist 43 non-formed portion. Then, an electrolytic copper plating film 44 having a thickness of 20 μm was formed (see FIG. 9E).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm²
65 minutes
Temperature 22 ± 2 ° C
[0144]
(10) Next, after removing the plating resist 43 with 5% KOH, the electroless plating film under the plating resist 43 is removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove through holes. 36 and the upper-layer conductor circuit 45 (including the via hole 46) (see FIG. 10A).
[0145]
(11) Next, the substrate 30 on which the through holes 36 and the like are formed is immersed in an etching solution, and roughened surfaces 36a and 46a are formed on the surfaces of the through holes 36 and the upper layer conductor circuit (including the via holes 46). (See FIG. 10B).
As an etchant, MEC Etch Bond manufactured by MEC was used.
[0146]
(12) Next, after preparing the resin composition for filling through holes described in A above, within 24 hours after preparation by the following method, in the through hole 36 and in the via hole 46 on one side of the substrate. Layers of resin fillers 40 and 54 were formed.
That is, first, the resin composition for filling a through hole was pushed into the through hole using a squeegee and then dried at 100 ° C. for 20 minutes. Next, a mask having an opening corresponding to the via hole 46 is placed on the substrate, and the via hole 46 is filled with a resin composition for filling a through hole using a squeegee, at 100 ° C. for 20 minutes. Drying was performed.
Further, in the same manner, the through hole filling resin composition was filled in the via hole 46 on the other surface of the substrate (see FIG. 10C).
[0147]
(13) Next, buffing was performed on both surfaces of the substrate after the processing of (12), and the surfaces of the layers of the resin fillers 40 and 54 exposed from the through holes 36 and the via holes 46 were flattened.
Next, the layers of the resin fillers 40 and 54 were cured by heat treatment at 100 ° C. for 1 hour and 150 ° C. for 1 hour (see FIG. 10D).
[0148]
(14) Next, a palladium catalyst (not shown) was applied to the surface of the interlayer resin insulation layer 50 and the exposed surfaces of the resin fillers 40 and 54 by performing the same treatment as in the above (6).
Next, an electroless plating process was performed under the same conditions as in (7) above, and an electroless plating film 56 was formed on the surface of the interlayer resin insulation layer 50 and the exposed surfaces of the resin fillers 40 and 54 (FIG. 11). (See (a)).
[0149]
(15) Next, a plating resist having a thickness of 20 μm was provided on the electroless plating film 56 using the same method as in (8) above (not shown). Furthermore, electrolytic plating was performed under the same conditions as in (9) above, and an electrolytic plating film 57 was formed on the plating resist non-forming portion. Thereafter, the plating resist and the electroless plating film 56 existing thereunder are removed, and a lid plating layer 58 composed of the electroless plating film 56 and the electrolytic plating film 57 is formed on the through hole 36 and the via hole 46. It formed (refer FIG.11 (b)).
[0150]
(16) Next, a roughened surface 58a was formed on the surface of the lid plating layer 58 using the etching solution (MEC etch bond) used in (11) above (see FIG. 11C).
(17) Next, by repeating the above steps (3) to (11), an upper interlayer resin insulation layer 60 and a conductor circuit (including via holes 66) were further formed to obtain a multilayer wiring board ( (Refer FIG.11 (d)). In this step, no through hole was formed.
[0151]
(18) Next, in the same manner as in (16) and (17) of Example 1, a solder bump forming opening was formed, and a solder resist layer 60 having a solder pad 66 was formed on the bottom thereof (FIG. 12). (See (a) to (c)). The opening diameter of the solder bump forming openings is 80 μm, and the distance between adjacent solder bump forming openings is 150 μm.
[0152]
(19) Thereafter, on the solder resist layer 14, a mask having an opening with a diameter of 90 μm is placed in a portion facing all the solder bump forming openings, and a concave shape is formed using a piston-type press-fitting printer. The openings for forming solder bumps were completely filled with solder paste.
In addition, the solder paste filled here contains a solder having a particle size of 5 to 20 μm in which Sn: Ag is mixed in a weight ratio of 96.5: 3.5, and the viscosity is adjusted to 200 Pa · s. It is.
[0153]
(20) Next, of the solder paste filled in the above step (19), the portion of the solder paste raised from the surface of the solder resist layer is removed using a stainless steel squeegee, whereby the filled solder paste The surface was flattened, and the surface of the solder paste and the surface of the solder resist layer were flush.
Further, the filled solder paste was reflowed at 250 ° C.
[0154]
(21) Next, a mask having an opening with a diameter of 100 μm is placed on one side of the solder resist layer 14 at a portion facing all the solder bump forming openings, and the solder paste is printed by a piston press-fitting type printing machine. Thus, a solder paste layer was formed.
In addition, the solder paste filled here contains solder with a particle size of 5 to 20 μm, which is mainly mixed with Sn: Ag in a weight ratio of 96.5: 3.5, and its viscosity is adjusted to 250 Pa · s. It is.
[0155]
Moreover, after forming a solder paste layer of Sn: Sb = 95: 5 on the other surface of the solder resist layer 14, conductive pins 78 were attached (see FIG. 13).
[0156]
(22) After that, the solder paste layer formed in the step (21) is reflowed at 260 ° C., and further, flux cleaning is performed to provide a multilayer printed wiring board having solder bumps and PGA (Pin Grid Array). Got.
[0157]
(Example 3)
In Example 1, an opening for forming a solder bump having an opening diameter of 100 μm was formed in the step (16), and Sn: Ag was mixed at a weight ratio of 96.5: 3.5 in the step (18). A multilayer printed wiring board was produced in the same manner as in Example 1 except that it contained solder having a particle diameter of 5 to 20 μm and was filled with a solder paste whose viscosity was adjusted to 250 Pa · s.
[0158]
Example 4
In Example 2, a solder bump forming opening having an opening diameter of 100 μm was formed in the step (18), and Sn: Ag was blended in a weight ratio of 96.5: 3.5 in the step (19). A multilayer printed wiring board was produced in the same manner as in Example 2 except that it contained a solder having a particle size of 5 to 20 μm and was filled with a solder paste whose viscosity was adjusted to 250 Pa · s.
[0159]
(Comparative Example 1)
Instead of the steps (18) to (21) of the first embodiment, a solder paste layer is formed by one solder paste printing in all solder bump forming openings, and solder bumps are formed by reflowing. A multilayer printed wiring board was produced in the same manner as in Example 1. Specifically, the following steps were performed.
[0160]
That is, on the solder resist layer on which the solder pads are formed, a mask having an opening with a diameter of 100 μm is placed on the portion facing all the solder bump forming openings, and the solder bump formation is performed using a piston press-fitting type printing machine. A solder paste was printed on the opening for forming a solder paste layer for forming solder bumps.
Thereafter, the solder paste layer was reflowed at 250 ° C., and further flux cleaning was performed to obtain a multilayer printed wiring board having solder bumps.
The solder paste used was the same as that used in the step (18) of Example 1.
[0161]
(Comparative Example 2)
Instead of the steps (19) to (22) of Example 2, a solder paste layer is formed by one solder paste printing in all solder bump forming openings, and solder bumps are formed by reflowing. A multilayer printed wiring board was produced in the same manner as in Example 2. Specifically, the following steps were performed.
[0162]
That is, on the solder resist layer on which the solder pads are formed, a mask having an opening with a diameter of 100 μm is placed on the portion facing all the solder bump forming openings, and the solder bump formation is performed using a piston press-fitting type printing machine. A solder paste was printed on the opening for forming a solder paste layer for forming solder bumps.
Thereafter, a conductive pin is attached to one side of the substrate on which a solder paste layer of Sn: Sb = 95: 5 is formed, and further, the solder paste layer is reflowed at 260 ° C., and then flux cleaning is performed. The multilayer printed wiring board provided with was obtained.
The solder paste used was the same as that used in the step (21) of Example 2.
[0163]
Regarding the multilayer printed wiring boards obtained in Examples 1 to 4 and Comparative Examples 1 and 2, the presence or absence of contamination on the solder resist layer surface, the presence or absence of solder bump voids, and the observation and reliability of the solder bump shape and height The performance evaluation before and after the property test was performed using the following evaluation method. The results are shown in Table 1.
[0164]
Evaluation methods
(1) Presence / absence of voids in solder bumps, shape and height of solder bumps
The portion of the multilayer printed wiring board where the solder bumps were formed was observed with X-rays to evaluate the presence of voids, the height of the solder bumps from the solder resist layer was measured, and the shape was observed. In addition, about the shape, what was hemispherical was set to (circle), and what was not so was set to x.
[0165]
(2) Reliability test
After leaving for 1000 hours under conditions of 135 ° C. and 85% relative humidity, the following continuity test was performed, and the printed wiring board was cut at the portion where the solder bumps were formed, and the state of the solder bumps was observed. Those that were not different from those in the reliability test were marked with ◯, and those with cracks observed were marked with ×.
[0166]
(3) Continuity test
After the multilayer printed wiring board was manufactured, a continuity test was performed before and after the reliability test, and the continuity state was evaluated from the results displayed on the monitor. Those without short-circuiting and disconnection were marked with ◯, and those with short-circuiting and breaking were marked with ×.
[0167]
[Table 1]

[0168]
As shown in Table 1, in the multilayer printed wiring boards of Examples 1 to 4, no voids were observed in the solder bumps, the height and shape of the solder bumps were substantially uniform, and the surface of the solder resist layer was also solder paste. It was not contaminated with. Further, there was no short circuit between the solder bumps, and there was no problem in the continuity test conducted before and after the reliability test, and no cracks or peeling were found after the reliability test.
Also, when the solder paste printed in the second solder paste printing process is sequentially changed in the range of 150 to 350 Pa · s and solder bumps are formed using the same method as in Example 1, the desired shape is also obtained. Solder bumps could be formed.
[0169]
On the other hand, in the multilayer printed wiring board of Comparative Example 1, since only the solder paste having a low viscosity is printed in one printing process, no void is formed on the solder bump, but the height is also compared with Example 1. The variation was large and the shape was not uniform. Further, the surface of the solder resist layer was contaminated with the solder paste. This was presumed to be because the solder paste wraps around the back of the mask during printing.
Further, regarding the continuity test, there was no particular problem after the formation of the solder bumps, but disconnection or short circuit occurred after the reliability test. Moreover, when the cross section of the solder bump of the part confirmed to be disconnected was observed, cracking and peeling were caused.
[0170]
Further, in the multilayer printed wiring board of Comparative Example 2, only the solder paste having a high viscosity is printed in one printing process, so that the surface of the solder resist layer was hardly contaminated, but many of the solder bumps. These voids were formed, and the height was much more varied than in Example 2, and the shape was not uniform.
Further, regarding the continuity test, there was no particular problem after the formation of the solder bumps, but disconnection or short circuit occurred after the reliability test. Moreover, when the cross section of the solder bump of the part confirmed to be disconnected was observed, many cracks and peeling occurred as compared with Comparative Example 1. This was presumed to have been induced from voids in the solder bumps.
[0171]
【The invention's effect】
As described above, in the method for manufacturing a multilayer printed wiring board according to the present invention, the surface of the solder paste is flattened after the first solder paste printing step, and then the second solder paste printing step is performed. A solder bump having a simple shape and a height and having no short circuit between them can be formed, and a printed wiring board excellent in connectivity and reliability can be manufactured.
[Brief description of the drawings]
FIGS. 1A to 1C are partial cross-sectional views schematically showing steps (a) to (c) in a method for producing a multilayer printed wiring board according to the present invention.
FIGS. 2A to 2B are partial cross-sectional views schematically showing an example of a method of printing a solder paste in the method for manufacturing a multilayer printed wiring board of the present invention.
FIGS. 3A to 3D are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 4A to 4D are cross-sectional views showing a part of the steps of the method for manufacturing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 5A to 5D are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention. FIGS.
6A to 6C are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention.
7A to 7C are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention.
FIGS. 8A to 8E are cross-sectional views illustrating a part of the process of the method for producing a multilayer printed wiring board according to the present invention.
FIGS. 9A to 9E are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 10A to 10D are cross-sectional views illustrating a part of the process of the method for producing a multilayer printed wiring board according to the present invention.
FIGS. 11A to 11D are cross-sectional views illustrating a part of the steps of the method for producing a multilayer printed wiring board according to the present invention. FIGS.
FIGS. 12A to 12C are cross-sectional views showing a part of the steps of the method for producing a multilayer printed wiring board according to the present invention. FIGS.
FIG. 13 is a cross-sectional view schematically showing an example of a multilayer printed wiring board obtained by the manufacturing method of the present invention.
[Explanation of symbols]
1, 30 substrate
8, 32 Copper foil
4, 34 Lower layer conductor circuit
9, 36 Through hole
6, 52 Openings for via holes
12, 42 Thin film conductor layer (electroless plating film)
3, 43 Plating resist
13, 44 Electrolytic plating film
2, 50 interlayer resin insulation layer
10, 54 Resin filler
58 Lid plating layer
14, 70 Solder resist layer
17, 76 Solder bump
78 Conductive pin

Claims (5)

After the interlayer resin insulating layer and the conductor circuit are laminated on the substrate on which the conductor circuit is formed, a solder resist layer having a plurality of solder bump formation openings is provided on the uppermost conductor circuit, and the solder bump formation is performed. A method of manufacturing a multilayer printed wiring board in which a solder paste is printed on an opening for forming a solder bump,
When the solder paste is printed by performing the following steps (a) to (c) including at least the first solder paste printing step and the second solder paste printing step, printing is performed in the first solder paste printing step. A method for producing a multilayer printed wiring board , wherein the viscosity of the solder paste to be printed is lower than the viscosity of the solder paste printed in the second solder paste printing step .
(A) perform the printing of more than the solder paste once, the first solder paste printing step of filling the solder paste into concave openings for forming solder bumps,
(B) a solder paste flattening step for flattening the surface of the solder paste filled in the step (a), and
(C) the second solder paste printing step of performing printing of one or more solder paste.   The solder paste is printed on the solder resist layer in the first and second solder paste printing steps, after placing a mask having an opening in a portion facing the solder bump forming opening on the solder resist layer. The manufacturing method of the multilayer printed wiring board as described.   3. The multilayer according to claim 2, wherein an opening diameter of an opening of the mask used in the first solder paste printing step and an opening diameter of an opening of the mask used in the second solder paste printing step are the same. A method for manufacturing a printed wiring board.   3. The multilayer printed wiring according to claim 2, wherein an opening diameter of an opening of the mask used in the first solder paste printing process is smaller than an opening diameter of an opening of the mask used in the second solder paste printing process. A manufacturing method of a board. In the first solder paste printing step,
In the first printing of the solder paste, the solder paste is printed to such an extent that only the opening for forming the solder bump having the depression on the bottom surface is filled with the depression.
The method for manufacturing a multilayer printed wiring board according to any one of claims 1 to 4, wherein the solder paste is printed so that the concave solder bump forming openings are completely filled by the second solder paste printing.

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