JP2013021374A - Multilayer printed board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed board in which cracks hardly occur in an interlayer resin insulating layer and has excellent reliability.SOLUTION: In a multilayer printed board, conductor circuits and interlayer resin insulating layers are sequentially stacked on a substrate, the conductor circuits interposing the interlayer resin insulating layer therebetween are connected through via holes, and a solder resist layer is formed on the outermost layer. Among the via holes, the via holes in different layers are stacked to one another. Among the stacked via holes, at least one via hole is stacked on other via holes so that its center is shifted from the centers of other via holes, and the other via holes are stacked so that their centers are substantially overlapped to one another.

Description

The present invention relates to a multilayer printed wiring board.

A multilayer printed wiring board called a so-called multilayer build-up wiring board is manufactured by a semi-additive method or the like, on a resin board reinforced with a glass cloth of about 0.5 to 1.5 mm called a core, and copper It is produced by alternately laminating conductive circuits and interlayer resin insulation layers by the method described above. The connection between the conductor circuits through the interlayer resin insulating layer of the multilayer printed wiring board is made by via holes.

Conventionally, a build-up multilayer printed wiring board has been manufactured by, for example, a method disclosed in Patent Document 1 or the like.
That is, first, a through hole is formed in a copper clad laminate to which a copper foil is attached, and then a through hole is formed by performing an electroless copper plating process. Subsequently, the surface of the substrate is etched into a conductor pattern using a photolithographic technique to form a conductor circuit. Next, a roughened surface is formed on the surface of the formed conductor circuit by electroless plating or etching, and an insulating resin layer is formed on the conductor circuit having the roughened surface, followed by exposure and development. Via hole openings are formed, and then an interlayer resin insulation layer is formed through UV curing and main curing.

Further, after roughening the interlayer resin insulation layer with acid, oxidizing agent, etc., a thin electroless plating film is formed, a plating resist is formed on the electroless plating film, and then thickened by electrolytic plating. Etching is performed after the plating resist is peeled off to form a conductor circuit connected to the underlying conductor circuit by a via hole.
After repeating this process, a solder resist layer for protecting the conductor circuit is finally formed, and plating is applied to the exposed portions for connection to electronic components such as IC chips and motherboards, and soldering is performed. After forming the bump forming pads, a solder paste is printed on the electronic component side such as an IC chip to form solder bumps, thereby manufacturing a build-up multilayer printed wiring board. Further, if necessary, solder bumps are also formed on the mother board side.

JP-A-9-130050

In recent years, with the increase in frequency of IC chips, there has been a demand for higher speed and higher density of multilayer printed wiring boards. As a multilayer printed wiring board corresponding to this, a stacked via structure (a via directly above a via hole) is required. A multilayer printed wiring board having via holes having a structure in which holes are formed has been proposed.
In such a multilayer printed wiring board having a via hole having a stacked via structure, since the signal transmission time is shortened, it is easy to cope with the high speed of the multilayer printed wiring board and the degree of freedom in designing the conductor circuit is improved. Therefore, it is easy to cope with higher density of the multilayer printed wiring board.

However, in a multilayer printed wiring board having a via hole having such a stacked via structure, a crack may occur in the interlayer resin insulating layer in the vicinity of the via hole. In particular, when a stacked via structure in which three or more via holes are stacked is formed, a crack often occurs in the outermost interlayer resin insulation layer. Further, due to this crack, the outermost layer Separation or disconnection may occur in the conductor circuit around the interlayer resin insulation layer.

Therefore, the present inventors have examined the cause of the occurrence of cracks in the interlayer resin insulating layer (particularly, the outermost interlayer resin insulating layer) in the vicinity of the via hole when a via hole having a stacked via structure is formed.
As a result, the via hole having a stacked via structure has a structure in which the via holes are linearly arranged, so that stress is caused by the difference in the linear expansion coefficient between the interlayer resin insulating layer and the via hole. When this occurs, the stress is not easily relieved, and the uppermost via hole usually has an external connection terminal such as a solder bump formed on the upper part thereof, so that the stress is particularly difficult to relieve. In addition, it was found that stress tends to concentrate on this portion, and this was considered to be a cause of the cracks easily occurring in the interlayer resin insulating layer (particularly, the outermost interlayer resin insulating layer) in the vicinity of the via hole.

Therefore, the present inventors, in the multilayer printed wiring board in which the via holes of different layers are stacked, if the via holes are not arranged linearly, that is, the via holes are stacked with their centers shifted. As a result, the inventors have found that stress is less likely to concentrate in a part of the via hole, and that the above-described problems can be solved, and the present invention having the following contents has been achieved.

That is, in the multilayer printed wiring board of the present invention, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, and the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, A multilayer printed wiring board having a solder resist layer formed on the outermost layer,
Among the above via holes, via holes of different levels are stacked,
Among the stacked via holes, at least one via hole is stacked with the other via hole shifted in the center, and the remaining via holes are stacked so that the center of the via hole is almost overlapped with the other via hole. It is characterized by being.

In the multilayer printed wiring board of the present invention, among the interlayer resin insulation layers, at least the outermost interlayer resin insulation layer has a linear expansion coefficient of 100 ppm / ° C. or less.

In the multilayer printed wiring board, it is desirable that at least the outermost interlayer resin insulating layer of the interlayer resin insulating layers is blended with particles and a rubber component.
The particles are preferably at least one of inorganic particles, resin particles, and metal particles.

Moreover, in the multilayer printed wiring board, among the interlayer resin insulation layers, at least the outermost interlayer resin insulation layer is a thermosetting resin, a photosensitive resin, a resin composite of a thermosetting resin and a thermoplastic resin, And it is desirable to form with the resin composition containing at least 1 sort (s) of the resin complex of a thermosetting resin and a photosensitive resin.

In the multilayer printed wiring board according to the present invention, at least one of via holes of different levels is stacked on another via hole while shifting the center thereof, so that the linear expansion between the via hole and the interlayer resin insulating layer It is possible to disperse the stress generated due to the difference in the coefficients, and since there is no large concentration of stress in a part of the stacked via holes, particularly in the uppermost via hole, Due to the occurrence of cracks in the interlayer resin insulation layer, the reliability is excellent.

In the multilayer printed wiring board, via holes other than via holes stacked with their centers shifted are stacked on other via holes so that their centers substantially overlap, and the via holes stacked in this way are stacked. In the hall, since the wiring distance is shortened, the signal transmission time can be shortened and the degree of freedom in designing the conductor circuit is improved.

(A) is a fragmentary sectional view which shows typically one Embodiment of the multilayer printed wiring board of this invention, (b) is only the via hole of the multilayer printed wiring board shown to (a) typically. It is a perspective view shown. (A) is a partial sectional view schematically showing another embodiment of the multilayer printed wiring board of the present invention, and (b) schematically shows only the via hole of the multilayer printed wiring board shown in (a). FIG. (A)-(e) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(d) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(c) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(c) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A), (b) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(e) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(d) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(d) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(c) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A)-(c) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A), (b) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention. (A), (b) is sectional drawing which shows typically a part of process of manufacturing the multilayer printed wiring board of this invention.

In the multilayer printed wiring board of the present invention, a conductor circuit and an interlayer resin insulation layer are sequentially laminated on a substrate, the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, and the outermost layer A multilayer printed wiring board having a solder resist layer formed thereon,
Among the above via holes, via holes of different levels are stacked,
Among the stacked via holes, at least one via hole is stacked with the other via hole shifted in the center, and the remaining via holes are stacked so that the center almost overlaps with the other via holes. It is characterized by being stacked.

In the multilayer printed wiring board of the present invention, at least one of the via holes of different levels is stacked on the other via hole while shifting the center thereof, so that the linear expansion between the via hole and the interlayer resin insulating layer It is possible to disperse the stress generated due to the difference in the coefficients, and since there is no large concentration of stress in a part of the stacked via holes, particularly in the uppermost via hole, Due to the occurrence of cracks in the interlayer resin insulation layer, the multilayer printed wiring board is excellent in reliability.

In the multilayer printed wiring board, via holes other than via holes stacked with their centers shifted are stacked on other via holes so that their centers almost overlap, and the via holes stacked in this way are stacked. In the hall, since the wiring distance is shortened, the signal transmission time can be shortened, and the degree of freedom in designing the conductor circuit is improved.

The multilayer printed wiring board of the present invention will be described below with reference to the drawings.
1 and 2 are partial cross-sectional views schematically showing a part of an embodiment of the multilayer printed wiring board of the present invention, and FIG. 1 and FIG. 2 (b) are multilayer prints shown in FIG. It is the perspective view which showed only the via hole of the wiring board typically.

As shown in FIG. 1, in the multilayer printed wiring board 100, the conductor circuit 105 and the interlayer resin insulation layer 102 are sequentially laminated on the substrate 101, and the conductor circuits 105 via the interlayer resin insulation layer 102 are respectively separated. Connected via via holes.
A solder resist layer 114 having solder bumps 117 is formed on the outermost layer.

In the multilayer printed wiring board 100, the via holes 107a to 107d formed by stacking are the uppermost via holes (fourth via holes) 107d and the lower via holes (third via holes). The inner via holes (first to third solder bumps) 107a to 107c are stacked so that the centers thereof are substantially overlapped with each other.
Thus, by stacking the center of the uppermost via hole so as to be shifted from the center of the lower via hole, it is possible to suppress the concentration of a large stress on a part of the stacked via hole.
The via hole 107 (107a to 107d) has a field via shape. Field via-shaped via holes are suitable for stacking via holes because their upper surfaces are flat.

Further, as shown in FIG. 2, in the multilayer printed wiring board 200 of the present invention, the via holes 207a to 207d formed in a stacked manner are the uppermost via hole (fourth via hole) 207d and the lower via hole. The hole (third via hole) 207c is stacked so that the center thereof is almost overlapped, and the center is shifted to the lower via hole (second via hole) 207b, and the inner layer is further stacked. Via holes (first and second stage via holes) 207a and 207b may be stacked so that the centers thereof substantially overlap each other. Also in the multilayer printed wiring board 200 having such a configuration, an effect of suppressing the stress concentration described above can be obtained.

Further, in the multilayer printed wiring board of the present invention, the shape of the stacked via holes is not limited to the above-described shape, and when the via holes are stacked in four stages, for example, the second to fourth stages The via holes may be stacked so that the centers almost overlap, and this may be stacked with the center shifted to the first via hole, or each of the second to fourth via holes is centered with the lower via hole. They may be stacked in a staggered manner. Of course, the number of via holes to be stacked is not particularly limited, and may be two or three, or five or more.
In the present specification, the center of the via hole refers to the center of the non-land portion of the via hole when the via hole is viewed in plan.

Further, in this specification, the term “stacked so that the centers substantially overlap” means that the centers of the upper and lower via holes are of course horizontal when the centers of the upper and lower via holes are stacked. The case where the distance is 5 μm or less is included.
Therefore, in this specification, being stacked with the center shifted is the case where the horizontal distance between the centers of the stacked via holes exceeds 5 μm.

In the multilayer printed wiring board of the present invention, the via holes stacked with their centers shifted from each other are the outer edge portion (shown as A in FIG. 1) of the non-land portion of the lower via hole and the upper via hole. It is desirable that they are stacked so as not to overlap with the bottom surface (shown as B in FIG. 1).
When the outer edge of the non-land portion of the lower via hole and the bottom surface of the upper via hole are stacked, the stress generated in each via hole causes a part of the stacked via hole (for example, If the stack is made so that the outer edge of the non-land portion of the lower via hole and the bottom surface of the upper via hole do not overlap, The stress is dispersed in the holes, and the stress is less likely to concentrate in a part of the stacked via holes, and inconvenience due to the stress concentration is less likely to occur.

The distance between the outer edge of the non-land portion of the lower via hole and the outer edge of the bottom surface of the upper via hole (denoted by L in FIG. 1) is specifically, for example, the non-land portion of the via hole When the diameter is about 40 to 200 μm, it is preferably 5 to 70 μm.
This is because within this range, it is difficult for stress to concentrate on a part of the via holes stacked as described above, and a degree of freedom in design can be ensured.

Next, components constituting the multilayer printed wiring board of the present invention will be described.
In the multilayer printed wiring board of the present invention, the conductor circuit and the interlayer resin insulation layer are sequentially laminated on the substrate, the conductor circuits sandwiching the interlayer resin insulation layer are connected via via holes, and the outermost layer A solder resist layer is formed.

Examples of the substrate include insulating substrates such as a glass epoxy substrate, a polyimide substrate, a bismaleimide-triazine substrate, and a fluororesin substrate.
The conductor circuit is made of, for example, Cu, Ni, P, Pd, Co, W, an alloy thereof, or the like, and is formed by plating or the like. A specific method for forming a conductor circuit will be described in detail later.

The substrate may be formed with through holes for connecting the conductor circuits formed on both sides thereof. In this case, it is desirable that a resin filler layer is formed in the through holes.
In the multilayer printed wiring board, a via hole may be formed immediately above the through hole. In this case, a resin filler layer is formed in the through hole, and a lid plating is formed on the through hole. It is desirable that a layer is formed. This is because the connection reliability between the via hole and the through hole becomes more excellent by forming the lid plating layer.

Furthermore, in the multilayer printed wiring board of the present invention, a through hole penetrating the substrate and the interlayer resin insulating layer may be formed. By forming such a through hole, the conductor circuits sandwiching the substrate and the interlayer resin insulation layer can be electrically connected.

The interlayer resin insulation layer is, for example, a thermosetting resin, a photosensitive resin, a thermoplastic resin, a resin composite of a thermosetting resin and a thermoplastic resin, a resin composite of a thermosetting resin and a photosensitive resin, or the like. It is formed by the resin composition containing this.

Specific examples of the thermosetting resin include, for example, epoxy resins, phenol resins, polyimide resins, polyester resins, bismaleimide resins, polyolefin resins, polyphenylene ether resins, and the like.

Examples of the epoxy resin include cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenol F type epoxy resin, naphthalene type epoxy resin, Examples thereof include cyclopentadiene type epoxy resins, epoxidized products of condensates of phenols and aromatic aldehydes having a phenolic hydroxyl group, triglycidyl isocyanurate, and alicyclic epoxy resins. These may be used alone or in combination of two or more. Thereby, it will be excellent in heat resistance.

Examples of the polyolefin resin include polyethylene, polystyrene, polypropylene, polyisobutylene, polybutadiene, polyisoprene, cycloolefin resin, and copolymers of these resins.

As said photosensitive resin, an acrylic resin etc. are mentioned, for example.
Moreover, what provided the photosensitivity to the above-mentioned thermosetting resin can also be used as a photosensitive resin. Specific examples include those obtained by reacting methacrylic acid or acrylic acid with a thermosetting group (for example, epoxy group in an epoxy resin) of a thermosetting resin to give an acrylic group.
Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, and polysulfone.

Examples of the resin composite of the thermosetting resin and the thermoplastic resin include those containing the above-described thermosetting resin and the above-described thermoplastic resin. Especially, what contains an epoxy resin and / or a phenol resin as a thermosetting resin, and contains a phenoxy resin and / or polyether sulfone (PES) as a thermoplastic resin is desirable.
Moreover, as a composite_body | complex of the said photosensitive resin and a thermoplastic resin, what contains above-described photosensitive resin and above-mentioned thermoplastic resin is mentioned, for example.

Examples of the resin composition also include a roughened surface-forming resin composition.
Examples of the roughened surface-forming resin composition include, in an uncured heat-resistant resin matrix that is hardly soluble in a roughened liquid consisting of at least one selected from an acid, an alkali, and an oxidizing agent. And a material in which a substance soluble in a roughening liquid comprising at least one selected from oxidizing agents is dispersed.
As used herein, the terms “slightly soluble” and “soluble” refer to those having a relatively high dissolution rate as “soluble” for convenience when immersed in the same roughening solution for the same time. The slow one is called “slightly soluble” for convenience.

The heat resistant resin matrix is preferably one that can maintain the shape of the roughened surface when the roughened surface is formed on the interlayer resin insulating layer using the roughening liquid, for example, a thermosetting resin, a thermoplastic resin. Examples thereof include resins and composites thereof. Photosensitive resin may also be used. This is because when the via hole opening is formed, the opening can be formed by exposure and development processing.

Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. Further, resins obtained by imparting photosensitivity to these thermosetting resins, that is, resins obtained by (meth) acrylation reaction of thermosetting groups using methacrylic acid or acrylic acid may be used. Specifically, (meth) acrylate of an epoxy resin is desirable, and an epoxy resin having two or more epoxy groups in one molecule is more desirable.

Examples of the thermoplastic resin include phenoxy resin, polyether sulfone, polysulfone, polyphenylene sulfone, polyphenylene sulfide, polyphenyl ether, polyether imide, and the like. These may be used alone or in combination of two or more.

Examples of the soluble substance include inorganic particles, resin particles, metal particles, rubber particles, liquid phase resins, and liquid phase rubbers. These may be used alone or in combination of two or more.

Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide; potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate, and talc. And silicon compounds such as silica and zeolite. These may be used alone or in combination of two or more.
The alumina particles can be dissolved and removed with hydrofluoric acid, and calcium carbonate can be dissolved and removed with hydrochloric acid. Sodium-containing silica and dolomite can be dissolved and removed with an alkaline aqueous solution.

Examples of the resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When the resin particles are immersed in a roughening solution made of at least one selected from an acid, an alkali, and an oxidizing agent, the heat resistance It is not particularly limited as long as it has a faster dissolution rate than the resin matrix. Specifically, for example, amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, Examples include polyphenylene resin, polyolefin resin, fluororesin, and bismaleimide-triazine resin. These may be used alone or in combination of two or more.
The resin particles must be previously cured. If not cured, the resin particles are dissolved in a solvent that dissolves the resin matrix, so they are uniformly mixed, and only the resin particles cannot be selectively dissolved and removed with an acid or an oxidizing agent. is there.

Examples of the metal particles include gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead, and the like. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.

Moreover, when using the resin composition containing a thermosetting resin as such a resin composition, it is desirable to use a thing with a glass transition temperature of 180 degrees C or less.
This is because, in a resin composition having a glass transition temperature exceeding 180 ° C., the temperature at the time of heat curing exceeds 200 ° C., the substrate may be warped at the time of heating or inconvenience at the time of melting may occur.

In the multilayer printed wiring board, at least the outermost interlayer resin insulation layer preferably has a linear expansion coefficient of 100 ppm / ° C. or less, and all the interlayer resin insulation layers have a linear expansion coefficient of 100 ppm / ° C. or less. More desirable.
Thus, when the linear expansion coefficient of the interlayer resin insulation layer is small, stress due to the difference in the linear expansion coefficient is unlikely to occur between the interlayer resin insulation layer and the via hole, the substrate, and the conductor circuit. Peeling between the insulating layer and the via hole and cracking in the interlayer resin insulating layer are less likely to occur. Therefore, the multilayer printed wiring board on which the interlayer resin insulation layer having the linear expansion coefficient in the above range is formed is more reliable.

The linear expansion coefficient of the interlayer resin insulation layer is more preferably 30 to 90 ppm / ° C. When the linear expansion coefficient is less than 30 ppm / ° C., the rigidity is high. For example, when the roughened surface is formed on the surface, the unevenness of the roughened surface may not be retained, whereas the above range is acceptable. This is because it is more excellent in crack resistance and excellent in shape retention of the roughened surface.

Further, it is desirable that particles and a rubber component are blended in the interlayer resin insulation layer.
When the particles are blended, the shape retention of the interlayer resin insulation layer is further improved, and when the rubber component is blended, stress is applied to the interlayer resin insulation layer due to the flexibility and rebound resilience of the rubber component. This can absorb or relieve the stress when acting.

The particles are preferably at least one of inorganic particles, resin particles, and metal particles.
Examples of the inorganic particles include aluminum compounds such as alumina and aluminum hydroxide; calcium compounds such as calcium carbonate and calcium hydroxide; potassium compounds such as potassium carbonate; magnesium compounds such as magnesia, dolomite, basic magnesium carbonate, and talc. And those composed of silicon compounds such as silica and zeolite. These may be used alone or in combination of two or more.

Examples of the resin particles include amino resins (melamine resins, urea resins, guanamine resins, etc.), epoxy resins, phenol resins, phenoxy resins, polyimide resins, polyphenylene resins, polyolefin resins, fluororesins, bismaleimide-triazines, and the like. Things. These may be used alone or in combination of two or more.

As said metal particle, what consists of gold, silver, copper, tin, zinc, stainless steel, aluminum, nickel, iron, lead etc. is mentioned, for example. These may be used alone or in combination of two or more.
In addition, the metal particles may be coated with a resin or the like in order to ensure insulation.

Examples of the rubber component include acrylonitrile-butadiene rubber, polychloroprene rubber, polyisoprene rubber, acrylic rubber, polysulfur type rigid rubber, fluorine rubber, urethane rubber, silicone rubber, ABS resin, and the like.
Further, polybutadiene rubbers; various modified polybutadiene rubbers such as epoxy modification, urethane modification, (meth) acrylonitrile modification, (meth) acrylonitrile butadiene rubber containing a carboxyl group, and the like can also be used.

The blending amount of the particles and the rubber component is not particularly limited, but the blending amount after forming the interlayer resin insulation layer is desirably 1 to 25% by weight for the particles and 5 to 20% by weight for the rubber component. This is because, within this range, it is suitable for matching the thermal expansion coefficient with the substrate and the solder resist layer, and for relieving stress due to curing shrinkage when forming the interlayer resin insulation layer. More desirable amounts are 3 to 18% by weight for the particles and 7 to 18% by weight for the rubber component.

The via hole is made of, for example, Cu, Ni, Pd, Co, W, alloys thereof, or the like, as in the conductor circuit, and is formed by plating or the like. A specific method for forming a via hole will be described in detail later.
In the stacked via holes, at least one of the via holes preferably has a land diameter different from that of other via holes. When the stacked via holes have such a structure, the via hole having a large land diameter serves as a reinforcing material for the interlayer resin insulation layer, and the mechanical strength of the interlayer resin insulation layer is improved, and the via hole is improved. This is because cracks are less likely to occur in the nearby interlayer resin insulation layer.

The via hole shape of the multilayer printed wiring board is preferably a field via shape. This is because field via-shaped via holes are suitable for stacking via holes because their upper surfaces are flat.
In the multilayer printed wiring board of the present invention, via holes of different levels are not stacked, and there may be via holes in which other via holes are not stacked.

The solder resist layer is formed using a solder resist composition containing, for example, a polyphenylene ether resin, a polyolefin resin, a fluororesin, a thermoplastic elastomer, an epoxy resin, a polyimide resin, or the like.

Examples of solder resist compositions other than those described above include (meth) acrylates of novolak epoxy resins, imidazole curing agents, bifunctional (meth) acrylate monomers, and (meth) acrylate esters having a molecular weight of about 500 to 5,000. Examples include a polymer, a thermosetting resin composed of a bisphenol type epoxy resin, a photosensitive monomer such as a polyvalent acrylic monomer, a paste-like fluid containing a glycol ether solvent, and the viscosity is 1 to 25 ° C. It is desirable that the pressure is adjusted to 10 Pa · s.
The solder resist composition may contain an elastomer or an inorganic filler.
Moreover, as a soldering resist composition, a commercially available soldering resist composition can also be used.

Next, a method for producing the multilayer printed wiring board of the present invention will be described in the order of steps.
(1) First, a conductive circuit is formed on a substrate using the above-described resin substrate, a copper-clad laminate with copper foil attached to both sides thereof, or the like as a starting material.
Specifically, for example, after forming a solid conductor layer by performing electroless plating treatment on both surfaces of the substrate, an etching resist corresponding to the conductor circuit pattern is formed on the conductor layer, and then etching is performed. What is necessary is just to form by performing.
Moreover, you may use a copper clad laminated board as a board | substrate with which the solid conductor layer was formed.

In addition, when forming a through hole for connecting between conductor circuits formed on both sides of a substrate, a through hole is previously formed in the substrate, and an electroless plating process is also applied to the wall surface of the through hole. Thus, a through hole is formed to connect between conductor circuits sandwiching the substrate.

Further, after forming the through hole, it is desirable to fill the through hole with a resin filler. At this time, it is desirable to fill the resin filler in the conductor circuit non-formed portion.
Examples of the resin filler include a resin composition containing an epoxy resin, a curing agent, and inorganic particles.
Further, when the resin filler is filled in the through hole or in the conductor circuit non-forming portion, the wall surface of the through hole or the side surface of the conductor circuit may be roughened in advance. This is because the adhesion between the resin filler and the through-holes is improved.
In addition, as a roughening process method, the method similar to the method used at the process of (2) mentioned later can be used.

Moreover, when forming a cover plating layer on the said through hole, this cover plating layer can be formed by passing through the process of the following (a)-(c), for example.
That is, (a) after forming the through hole having the resin filler layer inside through the above-described steps, the surface of the substrate including the exposed surface of the resin filler layer is subjected to electroless plating treatment or sputtering. To form a thin film conductor layer. In addition, when using an electroless-plating process, a catalyst is previously provided to the to-be-plated surface.

(B) Next, a plating resist is formed on portions other than on the through holes (including the resin filler layer), and electrolytic plating is performed using the thin film conductor layer as a plating lead.

(C) Next, after the completion of electrolytic plating, the plating resist is peeled off and the thin film conductor layer under the plating resist is removed.

Through the steps (a) to (c), a lid plating layer composed of two layers of a thin film conductor layer and an electrolytic plating layer can be formed.
The steps (a) to (c) from application of the catalyst to removal of the thin film conductor layer are performed using the same method as used in the steps (6) to (8) described later. Can do.

In the case of forming a lid plating layer consisting of one layer, for example, after applying a catalyst to the surface of the substrate including the exposed surface of the resin filler layer, a plating resist is formed on portions other than on the through holes, Thereafter, electroless plating treatment and removal of the plating resist may be performed.

(2) Next, the surface of the conductor circuit is roughened as necessary. Examples of the roughening treatment method include blackening (oxidation) -reduction treatment, etching treatment using a mixed solution containing an organic acid and a cupric complex, treatment by Cu-Ni-P needle alloy plating, and the like. Can be used. The roughening treatment performed in this step is performed in order to ensure adhesion between the interlayer resin insulating layer formed through a subsequent step, and when the adhesion between the conductor circuit and the interlayer resin insulating layer is high, This step may not be performed.

(3) Next, an uncured resin layer made of a thermosetting resin, a photosensitive resin, or a resin composite is formed on the conductor circuit, or a resin layer made of a thermoplastic resin is formed.
The uncured resin layer may be formed by applying uncured resin with a roll coater, curtain coater, or the like, or may be formed by thermocompression bonding of an uncured (semi-cured) resin film. . Furthermore, you may affix the resin film in which metal layers, such as copper foil, were formed in the single side | surface of an uncured resin film.
The resin layer made of a thermoplastic resin is preferably formed by thermocompression bonding a resin molded body formed into a film shape.

(4) Next, in the case of forming an interlayer resin insulation layer using a thermosetting resin or a resin composite containing a thermosetting resin as the material, the uncured resin layer is subjected to a curing treatment, Openings for via holes are formed to form interlayer resin insulation layers.
The via hole opening is preferably formed by laser processing. The laser treatment may be performed before the curing treatment or after the curing treatment.
Moreover, when forming the interlayer resin insulation layer which consists of photosensitive resin or the resin composite containing photosensitive resin, you may provide the opening for via holes by performing exposure and image development processing. In this case, the exposure and development processes are performed before the curing process.

When an interlayer resin insulation layer using a thermoplastic resin as the material is formed, a via hole opening can be formed in the resin layer made of the thermoplastic resin by laser processing to form an interlayer resin insulation layer. .

At this time, examples of the laser to be used include a carbon dioxide laser, an excimer laser, a UV laser, and a YAG laser. These may be used properly in consideration of the shape of the via hole opening to be formed.

In the case of forming the via hole openings, a large number of via hole openings can be formed at a time by irradiating laser light with a hologram type excimer laser through a mask.
In addition, when a via hole opening is formed using a short pulse carbon dioxide laser, there is little resin residue in the opening, and damage to the resin at the periphery of the opening is small.

When laser light is irradiated through the optical system lens and the mask, a large number of via hole openings can be formed at one time.
This is because laser light having the same intensity and the same irradiation angle can be simultaneously irradiated to a plurality of portions through the optical system lens and the mask.

Moreover, the thickness of the interlayer resin insulation layer is not particularly limited, but normally 5 to 50 μm is desirable. Further, the opening diameter of the via hole opening is not particularly limited, but is usually preferably 40 to 200 μm.

Further, when forming a through hole for connecting between the conductor circuits sandwiching the substrate and the interlayer resin insulation layer, a through hole penetrating the interlayer resin insulation layer and the substrate is formed in this step. The through hole can be formed using drilling, laser processing, or the like.

(5) Next, a roughened surface is formed on the surface of the interlayer resin insulating layer including the inner wall of the opening for the via hole using an acid or an oxidizing agent as necessary.
This roughened surface is formed in order to improve the adhesion between the interlayer resin insulation layer and the thin film conductor layer formed thereon, and provides sufficient adhesion between the interlayer resin insulation layer and the thin film conductor layer. If there is a property, it may not be formed. Moreover, when the through-hole which penetrates a board | substrate and an interlayer resin insulation layer is formed, you may form a roughening surface in the wall surface.

Examples of the acid include sulfuric acid, nitric acid, hydrochloric acid, phosphoric acid, formic acid, and examples of the oxidizing agent include permanganates such as chromic acid, chromium sulfuric acid, and sodium permanganate.
In addition, after the roughened surface is formed, it is desirable to neutralize the surface of the interlayer resin insulation layer using an aqueous solution such as an alkali or a neutralizing solution. This is because the influence of an acid or an oxidizing agent can be prevented in the next step.
In addition, the roughened surface may be formed using plasma treatment or the like.

(6) Next, a thin film conductor layer is formed on the surface of the interlayer resin insulation layer provided with the via hole opening.
The thin film conductor layer can be formed using a method such as electroless plating, sputtering, or vapor deposition. When the roughened surface is not formed on the surface of the interlayer resin insulating layer, the thin film conductor layer is preferably formed by sputtering.
In addition, when forming a thin film conductor layer by electroless plating, the catalyst is previously provided to the to-be-plated surface. Examples of the catalyst include palladium chloride.

The thickness of the thin film conductor layer is not particularly limited, but when the thin film conductor layer is formed by electroless plating, 0.6 to 1.2 μm is desirable, and when formed by sputtering, 0.1 to 0.1 μm is preferable. 1.0 μm is desirable.

Further, when a through hole penetrating the substrate and the interlayer resin insulating layer is formed in the step (4), a thin film conductor layer is also formed in the through hole to form a through hole. In this case, it is desirable to form a resin filler layer in the through hole, and then a lid plating layer may be formed on the through hole. In particular, when a via hole is formed in a post process on the through hole formed here, it is desirable to form a lid plating layer.

The through hole formed in this way connects the conductor circuit between the substrate and the interlayer resin insulation layer, as well as the two layers formed on both surfaces of the two-layer conductor circuit and the substrate. A total of four conductor circuits may be connected to the other conductor circuit.

(7) Next, a plating resist is formed on a part of the thin film conductor layer by using a dry film or the like, and then electrolytic plating is performed using the thin film conductor layer as a plating lead. A plating layer is formed.
Here, the plating resist is formed so that a via hole having a desired land diameter can be formed. That is, if a via hole having a large land diameter is to be formed at this level, the width of the plating resist non-forming portion may be increased.

In this step, the via hole opening may be filled with electrolytic plating, and the shape of the via hole formed through the subsequent step may be a field via shape.
This is because a via hole having a field via shape is easily stacked on the via hole.
In this step, once the electrolytic plating layer having a depression on the upper surface is formed, the depression may be filled with a conductive paste to flatten the upper surface, or once the depression is formed on the upper surface. After forming the electrolytic plating layer, the recess may be filled with a resin filler or the like, and a lid plating layer may be formed thereon to flatten the upper surface.

When the via hole opening is filled with electrolytic plating, for example, an electrolytic plating treatment may be performed using an electrolytic plating solution having the following composition.
That is, it contains 50 to 300 g / l of copper sulfate, 30 to 200 g / l of sulfuric acid, 25 to 90 mg / l of chlorine ions, and 1 to 1000 mg / l of an additive comprising at least a leveling agent and a brightener. An electroplating process may be performed using an electroplating solution.

The electrolytic plating solution having such a composition can fill the via hole opening regardless of the opening diameter of the via hole, the material and thickness of the resin insulating layer, and the presence or absence of the roughened surface of the interlayer resin insulating layer. .
In addition, since the electrolytic plating solution contains copper ions at a high concentration, the copper ions are sufficiently supplied to the opening for the via hole, and the opening for the via hole is plated at a plating rate of 40 to 100 μm / hour. This leads to an increase in the speed of the electrolytic plating process.

The electrolytic plating solution is 100 to 250 g / l copper sulfate, 50 to 150 g / l sulfuric acid, 30 to 70 mg / l chloride ion, and 1 to 600 mg / l consisting of at least a leveling agent and a brightener. It is desirable that the composition contains the additive.

Moreover, in the said electroplating liquid, the said additive should just consist of a leveling agent and a brightener at least, and may contain the other component.
Here, examples of the leveling agent include polyethylene, gelatin, and derivatives thereof.
Examples of the brightener include sulfur oxides and related compounds, hydrogen sulfide and related compounds, and other sulfur compounds.

The blending amount of the leveling agent is desirably 1 to 1000 mg / l, and the blending amount of the brightener is desirably 0.1 to 100 mg / l. Moreover, as for the mixture ratio of both, 2: 1-10: 1 are desirable.

(8) Next, the plating resist is peeled off, and the thin film conductor layer existing under the plating resist is removed by etching to form an independent conductor circuit. Examples of the etchant include sulfuric acid-hydrogen peroxide aqueous solution, persulfate aqueous solution such as ammonium persulfate, ferric chloride, cupric chloride, hydrochloric acid and the like. Moreover, you may use the mixed solution containing a cupric complex and an organic acid as etching liquid.

Moreover, it may replace with the method described in said (7) and (8), and may form a conductor circuit by using the following method.
That is, after an electrolytic plating layer is formed on the entire surface of the thin film conductor layer, an etching resist is formed on a part of the electrolytic plating layer using a dry film, and then the electrolytic plating layer under the etching resist non-forming portion and An independent conductor circuit may be formed by removing the thin film conductor layer by etching and further removing the etching resist.

(9) Thereafter, the steps (3) to (8) are repeated once or twice or more, thereby producing a substrate on which the uppermost conductor circuit is formed on the interlayer resin insulation layer. In addition, what is necessary is just to select suitably how many times the said process of (3)-(8) is repeated according to the design of a multilayer printed wiring board.
Here, when the via hole is formed by repeating the steps (3) to (8), the via hole whose center is shifted from the center of the lower via hole is formed in at least one repeated step. Specifically, when the via hole opening is formed, the formation position may be shifted from the center of the lower via hole.

Further, in the steps (7) and (8), when a through hole is formed through the substrate and the interlayer resin insulating layer, a via hole may be formed immediately above the through hole.

(10) Next, a solder resist layer having a plurality of solder bump forming openings is formed on the substrate including the uppermost conductor circuit.
Specifically, after applying an uncured solder resist composition with a roll coater or curtain coater, or after crimping a solder resist composition formed into a film, solder bumps are formed by laser processing or exposure development processing. A solder resist layer is formed by forming an opening for use and, if necessary, performing a curing treatment.

Further, examples of the laser used when forming the solder bump forming opening include the same lasers as those used when forming the above-described via hole opening.

Next, if necessary, solder pads are formed on the surface of the conductor circuit exposed at the bottom surface of the solder bump forming opening.
The solder pad can be formed by coating the surface of the conductor circuit with a corrosion-resistant metal such as nickel, palladium, gold, silver, or platinum.
Specifically, it is desirable to form with a metal such as nickel-gold, nickel-silver, nickel-palladium, nickel-palladium-gold.
The solder pad can be formed by using, for example, a method such as plating, vapor deposition, or electrodeposition. Among these, plating is preferable because the uniformity of the coating layer is excellent.

(11) Next, the solder bump forming openings are filled with a solder paste and subjected to a reflow process, or after being filled with a solder paste, a conductive pin is attached, and a reflow process is further performed. BGA (Ball Grid Array) and PGA (Pin Grid Array) are formed.
In addition, plasma treatment with oxygen, carbon tetrachloride, or the like may be performed in a timely manner for a character printing process for forming product recognition characters or the like or for modifying the solder resist layer.
The multilayer printed wiring board of the present invention can be manufactured through such steps.

Hereinafter, the present invention will be described in more detail.

Example 1
A. Preparation of photosensitive resin composition A (i) Resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) in diethylene glycol dimethyl ether (DMDG) at a concentration of 80% by weight 35 parts by weight, photosensitive monomer (Toa Gosei Co., Ltd., Aronix M315) 3.15 parts by weight, antifoaming agent (Sannopco S-65) 0.5 part by weight and N-methylpyrrolidone (NMP) 3.6 parts by weight A mixed composition was prepared by taking a portion in a container and stirring and mixing.

(Ii) 12 parts by weight of polyethersulfone (PES), 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd., polymer pole) having an average particle diameter of 1.0 μm and an average particle diameter of 0.5 μm 09 parts by weight was put in another container and stirred and mixed, and then 30 parts by weight of NMP was further added and stirred and mixed by a bead mill to prepare another mixed composition.

(Iii) Imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) 2 parts by weight, photopolymerization initiator (manufactured by Ciba Specialty Chemicals, Irgacure I-907), 2 parts by weight, photosensitizer (Nipponization) A mixed composition was prepared by further taking 0.2 parts by weight of DETX-S (manufactured by Yakuhin Co., Ltd.) and 1.5 parts by weight of NMP in another container and stirring and mixing them.
And the photosensitive resin composition A was obtained by mixing the mixed composition prepared by (i), (ii), and (iii).

B. Preparation of photosensitive resin composition B (i) Resin solution prepared by dissolving 25% acrylate of cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight: 2500) in diethylene glycol dimethyl ether (DMDG) at a concentration of 80% by weight 35 parts by weight, photosensitive monomer (Toa Gosei Co., Ltd., Aronix M315) 4 parts by weight, antifoaming agent (Sannopco S-65) 0.5 part by weight and N-methylpyrrolidone (NMP) 3.6 parts by weight The mixture composition was prepared by taking into a container and stirring and mixing.

(Ii) 12 parts by weight of polyethersulfone (PES) and 14.49 parts by weight of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., polymer pole) having an average particle size of 0.5 μm were put in another container and stirred and mixed. Thereafter, 30 parts by weight of NMP was further added and stirred and mixed with a bead mill to prepare another mixed composition.

(Iii) Imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) 2 parts by weight, photopolymerization initiator (manufactured by Ciba Specialty Chemicals, Irgacure I-907), 2 parts by weight, photosensitizer (Nipponization) A mixed composition was prepared by further taking 0.2 parts by weight of DETX-S (manufactured by Yakuhin Co., Ltd.) and 1.5 parts by weight of NMP in another container and stirring and mixing them.
And the photosensitive resin composition B was obtained by mixing the mixed composition prepared by (i), (ii), and (iii).

C. Preparation of resin filler 100 parts by weight of bisphenol F-type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U), the average particle diameter coated with a silane coupling agent on the surface is 1.6 μm, and the maximum particle diameter In a container, 72 parts by weight of SiO ₂ spherical particles (manufactured by Adtech Co., CRS 1101-CE) and 1.5 parts by weight of a leveling agent (Sennopco Perenol S4) are stirred and mixed to give a viscosity of 25 A resin filler of 30 to 80 Pa · s at ± 1 ° C. was prepared.
As the curing agent, 6.5 parts by weight of an imidazole curing agent (manufactured by Shikoku Kasei Co., Ltd., 2E4MZ-CN) was used.

D. Manufacturing method of printed wiring board (1) Starting from a copper-clad laminate in which 18 μm copper foil 8 is laminated on both sides of a substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm (See FIG. 3A). First, the copper-clad laminate was drilled, subjected to electroless plating, and etched into a pattern to form the lower conductor circuit 4 and the through hole 9 on both surfaces of the substrate 1 (FIG. 3 (b) )reference).

(2) An aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), and Na ₃ PO ₄ (6 g / l) after the substrate on which the through hole 9 and the lower conductor circuit 4 are formed is washed with water and dried. A lower layer including the through-hole 9 by performing a blackening treatment using a blackening bath (oxidation bath) and a reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath. A roughened surface (not shown) was formed on the entire surface of the conductor circuit 4.

(3) Next, after preparing the resin filler described in C above, within 24 hours after adjustment by the following method, the conductor circuit non-formed portion of the substrate 1 and the lower conductor circuit 4 within the through hole 9 A layer 10 ′ of resin filler was formed on the outer edge of each.
That is, first, a resin filler was pushed into a through hole using a squeegee, and then dried under conditions of 100 ° C. and 20 minutes. Next, a mask having an opening corresponding to the conductor circuit non-forming portion is placed on the substrate, and a resin filler layer 10 'is formed on the conductor circuit non-forming portion, which is a recess, using a squeegee. The film was dried at 20 ° C. for 20 minutes (see FIG. 3C).

(4) One side of the substrate after the processing of (3) above is applied to the surface of the lower conductor circuit 4 or the land surface of the through hole 9 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Polishing was performed so that the resin filler did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate.
Next, a heat treatment was performed at 100 ° C. for 1 hour and 150 ° C. for 1 hour to form the resin filler layer 10.

In this way, the surface layer portion of the resin filler layer 10 and the surface of the lower conductor circuit 4 formed in the through hole 9 and the conductor circuit non-forming portion are flattened, and the side surface 4a of the resin filler layer 10 and the lower conductor circuit 4 is flattened. And an insulative substrate in which the inner wall surface 9a of the through hole 9 and the resin filler layer 10 are firmly adhered through the roughened surface (FIG. 3D). )reference). That is, by this step, the surface of the resin filler layer 10 and the surface of the lower conductor circuit 4 are flush.

(5) The substrate is washed with water, acid degreased, soft-etched, and then an etching solution is sprayed on both sides of the substrate to etch the surface of the lower conductor circuit 4 and the land surface of the through hole 9. Thus, a roughened surface (not shown) was formed on the entire surface of the lower conductor circuit 4. As an etchant, an etchant (MEC Etch Bond, manufactured by MEC Co., Ltd.) comprising 10 parts by weight of imidazole copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used.

(6) Next, the photosensitive resin composition B prepared in B above (viscosity: 1.5 Pa · s) was applied to both sides of the substrate using a roll coater within 24 hours after preparation, and 20 in a horizontal state. After standing for a minute, drying (prebaking) was performed at 60 ° C. for 30 minutes. Next, the photosensitive resin composition A prepared in A above (viscosity: 7 Pa · s) was applied using a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes in the same manner, and then at 60 ° C. Drying (prebaking) for 30 minutes was performed to form two-layered resin layers 2a and 2b in a semi-cured state (see FIG. 3 (e)).

(7) Next, the semi-cured resin layer 2a, on both sides of the substrate formed with 2b, is adhered a photomask film black circle having a diameter of 80μm are printed, an ultrahigh-pressure mercury lamp at an intensity of 500 mJ / cm ² After exposure, spray development was performed with a DMDG solution. Thereafter, the substrate is further exposed to an intensity of 3000 mJ / cm ² with an ultrahigh pressure mercury lamp, and subjected to heat treatment at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and 150 for 3 hours, which corresponds to a photomask film. An interlayer resin insulation layer 2 having a via hole opening 6 with a diameter of 80 μm and excellent in dimensional accuracy was formed (see FIG. 4A).

(8) Furthermore, the substrate on which the via hole opening 6 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes to dissolve the epoxy resin particles present on the surface of the interlayer resin insulation layer 2 By removing the surface, the surface of the interlayer resin insulating layer 2 including the inner wall of the via-hole opening 6 was made rough (not shown).

(9) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Further, a palladium catalyst (manufactured by Atotech Co., Ltd.) is applied to the surface of the roughened substrate (roughening depth: 3 μm), whereby a catalyst is formed on the surface of the interlayer resin insulation layer 2 and the inner wall surface of the via hole opening 6. Nuclei were attached.

(10) Next, the substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a thin-film conductor layer 12 having a thickness of 0.6 to 3.0 μm over the entire rough surface (FIG. 4B). reference).
[Electroless plating aqueous solution]
NiSO ₄ 0.003 mol / l
Tartaric acid 0.200 mol / l
Copper sulfate 0.030 mol / l
HCHO 0.050 mol / l
NaOH 0.100 mol / l
α, α'-bipyridyl 40 mg / l
Polyethylene glycol (PEG) 0.10 g / l
[Electroless plating conditions]
40 minutes at 35 ° C liquid temperature

(11) Next, by attaching a commercially available photosensitive dry film to the thin film conductor layer 12, placing a mask, exposing at 100 mJ / cm ² , and developing with a 0.8% aqueous sodium carbonate solution, A plating resist 3 was provided (see FIG. 4C).

(12) Next, the substrate is washed with 50 ° C. water, degreased, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic copper plating under the following conditions. It formed (refer FIG.4 (d)).
(Electrolytic plating aqueous solution)
_{CuSO 4 · 5H 2 O 210 g} / l
Sulfuric acid 150 g / l
Cl ^- 40 mg / l
Polyethylene glycol 300 mg / l
Bisdisulfide 100 mg / l
[Electrolytic plating conditions]
Current density 1.0 A / dm ²
Time 60 minutes Temperature 25 ° C

(13) Subsequently, the plating resist 3 was peeled and removed in a 40 g / l NaOH aqueous solution at 50 ° C. Thereafter, the substrate is heated at 150 ° C. for 1 hour, and the thin film conductor layer existing under the plating resist is removed by using an etching solution containing sulfuric acid-hydrogen peroxide aqueous solution. A via hole 7 having a shape was formed (see FIG. 5A). The diameter of the non-land portion of the via hole 7 formed through this process (indicated as d in FIG. 5A) is 80 μm.

(14) Next, by repeating the steps (5) to (13), an upper interlayer resin insulation layer 2 and an independent conductor circuit 5 and a via-shaped via hole 7 are formed ( FIG. 5B to FIG. 6A).
In this process, the via hole was stacked so that the center of the lower via hole and the center of the lower via hole were substantially overlapped by adjusting the formation position of the via hole opening.

(15) Further, by repeating the steps (5) to (13), an upper interlayer resin insulation layer 2 and independent conductor circuits 5 and field via-shaped via holes 7 are formed (FIG. 6 (b) to FIG. 6 (c)).
In this step, the via holes were stacked while being shifted from the center of the lower via hole by adjusting the formation position of the via hole opening. The distance between the outer edge of the bottom surface of the via hole (third via hole) formed in this step and the outer edge of the non-land portion of the lower via hole (second via hole) is 5 μm. It is.

(16) Further, by repeating the steps (5) to (13) again, an upper interlayer resin insulation layer 2 and independent conductor circuits 5 and field via-shaped via holes 7 were formed ( FIG. 7 (a)).
In this step, the via hole was stacked so that the center of the lower via hole and the center thereof substantially overlapped by adjusting the formation position of the via hole opening.

(17) Next, the photosensitizing property obtained by acrylated 50% of an epoxy group of a cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) to a concentration of 60% by weight. 46.67 parts by weight of oligomer (molecular weight: 4000), 80% by weight of bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) dissolved in methyl ethyl ketone, 15.0 parts by weight, imidazole curing agent (Shikoku 1.6 parts by weight manufactured by Kasei Co., Ltd., trade name: 2E4MZ-CN), 3.0 parts by weight of polyvalent acrylic monomer (Nippon Kayaku Co., Ltd., trade name: R604), which is a photosensitive monomer, Kyoei Chemical Co., Ltd., trade name: DPE6A) 1.5 parts by weight, dispersion antifoam (San Nopco, S-65) 0.7 Part by weight is placed in a container, and a mixture composition is prepared by stirring and mixing. 2.0 parts by weight of benzophenone (manufactured by Kanto Chemical Co., Inc.) as a photopolymerization initiator and Michler's ketone as a photosensitizer are mixed with this mixture composition. (Kanto Chemical Co., Ltd.) 0.2 parts by weight was added to obtain a solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. The viscosity measurements, B-type viscometer (Tokyo Keiki Co., DVL-B type) when at ^60min -1 of (rpm) Rotor No. In the case of 4, 6 min ⁻¹ (rpm), the rotor No. 3 according.

(18) Next, the solder resist composition is applied to both surfaces of the multilayer wiring board to a thickness of 20 μm, and after drying at 70 ° C. for 20 minutes and 70 ° C. for 30 minutes, the solder pad A photomask having a thickness of 5 mm on which the above pattern was drawn was brought into close contact with the solder resist layer, exposed to 1000 mJ / cm ² of ultraviolet light, and developed with a DMTG solution to form an opening having a diameter of 80 μm.
Further, the solder resist layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. Then, a solder resist layer 14 having a thickness of 20 μm was formed.

(19) Next, the substrate on which the solder resist layer 14 is formed is immersed in an etching solution mainly composed of sodium persulfate for 1 minute, and a roughened surface having an average roughness (Ra) of 1 μm or less on the surface of the conductor circuit. (Not shown) was formed.
Furthermore, this substrate was made of nickel chloride (2.3 × 10 ⁻¹ mol / l), sodium hypophosphite (2.8 × 10 ⁻¹ mol / l), sodium citrate (1.6 × 10 ^−1). The nickel plating layer 15 having a thickness of 5 μm was formed in the opening by immersing in an electroless nickel plating solution having a pH of 4.5 containing 1 mol / l). Furthermore, the substrate gold potassium cyanide ^{(7.6 × 10 -3 mol / l} ), ammonium chloride ^{(1.9 × 10 -1 mol / l} ), sodium citrate (1.2 × ¹⁰ -1 mol / l) Immersion in an electroless gold plating solution containing sodium hypophosphite (1.7 × 10 ⁻¹ mol / l) at 80 ° C. for 7.5 minutes to form a thickness on the nickel plating layer 15 A 0.03 μm gold plating layer 16 was formed and used as a solder pad.

(20) Thereafter, a mask was placed on the solder resist layer 14, and a solder paste was printed on the solder bump forming openings using a piston-type press-fitting printer. Thereafter, the solder paste was reflowed at 250 ° C., and further flux cleaning was performed to obtain a multilayer printed wiring board having solder bumps 17 (see FIG. 7B).
In addition, the linear expansion coefficient of the interlayer resin insulation layer in the multilayer printed wiring board produced in this example is 70 ppm / ° C.

(Example 2)
A. Preparation of resin film for interlayer resin insulation layer 30 parts by weight of bisphenol A type epoxy resin (epoxy equivalent 469, Epicoat 1001 manufactured by Yuka Shell Epoxy), cresol novolac type epoxy resin (epoxy equivalent 215, manufactured by Dainippon Ink and Chemicals, Inc.) N-673) 40 parts by weight, triazine structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, Phenolite KA-7052 made by Dainippon Ink & Chemicals) 20 parts by weight ethyl diglycol acetate, 20 parts by weight of solvent naphtha The mixture was dissolved by heating with stirring, and 12 parts by weight of terminal epoxidized polybutadiene rubber (Denalex R-45EPT, manufactured by Nagase Kasei Kogyo Co., Ltd.) and 1.5-phenyl-4,5-bis (hydroxymethyl) imidazole pulverized product 1.5 Part by weight, fine Crushed silica 4 parts by weight, it was added 0.5 part by weight of silicon antifoaming agent to prepare an epoxy resin composition.
The obtained epoxy resin composition was applied on a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes, whereby an interlayer resin was obtained. A resin film for an insulating layer was produced.

B. Preparation of Resin Filler A resin filler was prepared in the same manner as in Example 1.

C. Manufacture of multilayer printed wiring board (1) A copper-clad laminate in which 18 μm copper foil 28 is laminated on both surfaces of an insulating substrate 21 made of glass epoxy resin or BT resin having a thickness of 0.8 mm was used as a starting material ( (See FIG. 8 (a)). First, this copper-clad laminate was etched into a lower conductor circuit pattern to form lower conductor circuits 24 on both surfaces of the substrate (see FIG. 8B).

(2) The substrate 21 on which the lower conductor circuit 24 is formed is washed with water and dried, and then an aqueous solution containing NaOH (10 g / l), NaClO ₂ (40 g / l), and Na ₃ PO ₄ (6 g / l) is blackened. A blackening treatment using a bath (oxidation bath) and a reduction treatment using an aqueous solution containing NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath are performed, and the surface of the lower conductor circuit 24 is roughened. (Not shown) was formed.

(3) Next, the resin film for an interlayer resin insulation layer produced in A is laminated by vacuum pressure bonding at 0.5 MPa while raising the temperature to 50 to 150 ° C. to form an interlayer resin insulation layer 22 (See FIG. 8C).
Further, a through hole 39 having a diameter of 300 μm was formed by drilling in the substrate 21 on which the interlayer resin insulating layer 22 was formed.

(4) Next, a mask on which a through hole having a thickness of 1.2 mm is formed is placed on the interlayer resin insulation layer 22, and the beam diameter is 4.0 mm and the top hat is irradiated with a CO ₂ gas laser having a wavelength of 10.4 μm. A via hole opening 26 having a diameter of 80 μm was formed in the interlayer resin insulation layer 22 under the conditions of mode, pulse width 8.0 μsec, mask through-hole diameter 1.0 mm, and one shot (see FIG. 8D). .

(5) Next, the substrate on which the via hole opening 26 is formed is immersed in an 80 ° C. solution containing 60 g / l of permanganic acid for 10 minutes, and the wall surface of the through-hole 39 is subjected to desmear treatment and an interlayer resin. By dissolving and removing the epoxy resin particles present on the surface of the insulating layer 22, a roughened surface (not shown) was formed on the surface including the inner wall surface of the via hole opening 26.

(6) Next, the substrate after the above treatment was immersed in a neutralization solution (manufactured by Shipley Co., Ltd.) and washed with water.
Furthermore, the surface of the interlayer resin insulating layer 22 (including the inner wall surface of the via hole opening 26) is provided by applying a palladium catalyst to the surface of the substrate that has been roughened (roughening depth 3 μm), and Catalyst nuclei were attached to the wall surface of the through hole 39 (not shown).
That is, the substrate was immersed in a catalyst solution containing palladium chloride (PdCl ₂ ) and stannous chloride (SnCl ₂ ), and the catalyst was applied by depositing palladium metal.

(7) Next, the substrate is immersed in an electroless copper plating aqueous solution at 34 ° C. for 40 minutes, the surface of the interlayer resin insulation layer 22 (including the inner wall surface of the via hole opening 26), and the wall surface of the through hole 39 A thin film conductor layer 32 having a thickness of 0.6 to 3.0 μm was formed (see FIG. 8E). In addition, as an electroless copper plating aqueous solution, the aqueous solution similar to the electroless copper plating aqueous solution used at the process of (1) of Example 1 was used.

(8) Next, a commercially available photosensitive dry film is attached to the substrate on which the thin film conductor layer 32 is formed, and a mask is placed, exposed at 100 mJ / cm ² , and developed with a 0.8% aqueous sodium carbonate solution. Thus, a plating resist 23 was provided (see FIG. 9A).

(9) Next, the substrate is washed with 50 ° C. water for degreasing, washed with 25 ° C. water and further washed with sulfuric acid, and then electroplated under the same conditions as in the step (12) of Example 1. Then, an electrolytic copper plating film 33 was formed on the portion where the plating resist 23 was not formed (see FIG. 9B).

(10) Further, after removing the plating resist 23 with 5% KOH, the electroless plating film under the plating resist 23 is etched using an etching solution containing sulfuric acid and hydrogen peroxide, and through holes 29, and The conductor circuit 25 (including the via hole 27) was used.

(11) Next, the substrate on which the through holes 29 and the like are formed is immersed in an etching solution to form a roughened surface (not shown) on the surfaces of the through holes 29 and the conductor circuits 25 (including the via holes 27). did. As an etchant, MEC Etch Bond manufactured by MEC was used.

(12) Next, after preparing the resin filler described in the above B, within 24 hours after preparation by the following method, the conductor circuit non-forming part in the through hole 29 and on the interlayer resin insulating layer 22 A resin filler layer was formed on the outer edge of the conductor circuit 25.
That is, first, a resin filler was pushed into a through hole using a squeegee, and then dried under conditions of 100 ° C. and 20 minutes. Next, using a mask and a squeegee having an opening corresponding to the conductor circuit non-forming portion, a resin filler layer is formed on the conductor circuit non-forming portion which is a recess, and the condition is 100 ° C. for 20 minutes. Dried.

Subsequently, in the same manner as in the step (4) of Example 1, the surface layer portion of the resin filler layer formed in the through hole or in the conductor circuit non-forming portion and the surface of the conductor circuit 25 are further flattened. By performing the heat treatment, a resin filler layer 30 having a surface flush with the surface of the conductor circuit 25 was formed (see FIG. 9C).

(13) Next, a palladium catalyst (not shown) was applied to the surface of the interlayer resin insulation layer 22 and the exposed surface of the resin filler layer 30 by performing the same treatment as in the above (6).
Next, an electroless plating process was performed under the same conditions as in (7) above, and a thin film conductor layer 32 was formed on the exposed surface of the resin filler layer 30 and the upper surface of the conductor circuit 25.

(14) Next, the plating resist 23 was provided on the thin-film conductor layer 32 using the method similar to said (8) (refer FIG.9 (d)). Subsequently, the substrate is washed with 50 ° C. water and degreased, washed with 25 ° C. water, and further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions. A copper plating film 33 was formed (see FIG. 10A).
[Electrolytic plating solution]
Sulfuric acid 2.24 mol / l
Copper sulfate 0.26 mol / l
Additive 19.5 ml / l
(Manufactured by Atotech Japan, Kaparaside GL)
[Electrolytic plating conditions]
Current density 1 A / dm ²
Time 65 minutes Temperature 22 + 2 ° C

(15) Next, after removing the plating resist 23 with 5% KOH, the electroless plating film under the plating resist 23 is removed by dissolution treatment by etching with a mixed solution of sulfuric acid and hydrogen peroxide. It was set as the layer 31 (refer FIG.10 (b)).

(16) Next, a roughened surface (not shown) was formed on the surface of the lid plating layer 31 using an etching solution (MEC etch bond).

(17) Next, by repeating the steps (3) to (11), an upper interlayer resin insulation layer 22 and a conductor circuit 25 (including via holes 27) are formed (FIG. 10C). To FIG. 11 (c)). The diameter of the non-land portion of the via hole 27 formed through this process is 80 μm. In this step, a via hole was formed immediately above the lid plating layer 31.
In this step, no through hole was formed.

(18) Next, by repeating the steps (3) to (11) twice, an upper interlayer resin insulation layer 22 and a conductor circuit 25 (including via holes 27) are formed (FIG. 12 ( a) to FIG. 13 (a)). The diameter of the non-land portion of the via hole 27 formed through this process is 80 μm.
Further, in this step, the via holes were stacked so that the center of the lower via hole and the center thereof were substantially overlapped by adjusting the formation position of the via hole opening.
In this step, no through hole was formed.

(19) Further, by repeating the steps (3) to (11) again, the outermost interlayer resin insulation layer 22a and the conductor circuit 25 (including the via hole 27) are formed, and the multilayer wiring board is formed. Obtained (see FIG. 13B). The diameter of the non-land portion of the via hole 27 formed through this process is 80 μm.
Further, in this step, the via holes were stacked while being shifted from the center of the lower via hole by adjusting the formation position of the via hole opening. The distance between the outer edge of the bottom surface of the via hole (fourth via hole) formed in this step and the outer edge of the non-land portion of the lower via hole (third via hole) is 8 μm. It is.
In this step, no through hole was formed.

(20) Next, a multilayer printed wiring board provided with solder bumps was obtained in the same manner as in Steps (17) to (20) of Example 1 (see FIGS. 14A and 14B).
In addition, the linear expansion coefficient of the interlayer resin insulation layer in the multilayer printed wiring board produced in this example is 60 ppm / ° C.

(Example 3)
In the step (15) of Example 1, the distance between the outer edge of the bottom surface of the third via hole and the outer edge of the non-land portion of the lower via hole (second via hole) is 20 μm. A multilayer printed wiring board was produced in the same manner as in Example 1 except that the via holes were stacked.

Example 4
In the step (19) of Example 2, the distance between the outer edge of the bottom surface of the fourth via hole and the outer edge of the non-land portion of the lower via hole (third via hole) is 40 μm. A multilayer printed wiring board was produced in the same manner as in Example 2 except that the via holes were stacked.

(Example 5)
In the step (15) of Example 1, the distance between the outer edge of the bottom surface of the third via hole and the outer edge of the non-land portion of the lower via hole (second via hole) is 70 μm. A multilayer printed wiring board was produced in the same manner as in Example 1 except that the via holes were stacked.

About the multilayer printed wiring board manufactured in Examples 1-5, the heat cycle test was done, the shape observation of the interlayer resin insulation layer and the via hole before and behind that, and the conduction test were done.

〔Evaluation method〕
(1) Heat cycle test-A cycle of leaving at 65 ° C for 3 minutes and 130 ° C for 3 minutes was repeated 1000 cycles.

(2) After observing the shape observation multilayer printed wiring board, before and after the heat cycle test, the multilayer printed wiring board was cut so as to pass through the stacked via holes, and the cross section was optical microscope with a magnification of 100 to 400 times Was observed.

(3) Continuity test After producing a multilayer printed wiring board, a continuity test was performed using a checker before and after the heat cycle test, and the continuity state was evaluated from the results displayed on the monitor.

As a result, in the multilayer printed wiring boards of Examples 1 to 5, in the cross-sectional shape observation before and after the heat cycle test, in all interlayer resin insulating layers including the outermost interlayer resin insulating layer, occurrence of cracks and interlayer resin Generation of peeling between the insulating layer and the via hole was not observed. In addition, before and after the heat cycle test, no short circuit or disconnection occurred, and the conduction state was good.

1, 21 Substrate 2, 22 Interlayer resin insulation layer 3, 23 Plating resist 4, 24 Lower conductor circuit 5, 25 Conductor circuit 6, 26 Via hole opening 7, 27 Via hole 8, 28 Copper foil 9, 29 Through hole 10 , 30 Resin filler layer 12, 32 Thin film conductor layer 13, 33 Electrolytic plating film 14, 34 Solder resist layer 17, 37 Solder bump 31 Cover plating layer

Claims (7)

A multilayer in which a conductor circuit and an interlayer resin insulating layer are sequentially laminated on a substrate, the conductor circuits sandwiching the interlayer resin insulating layer are connected via via holes, and a solder resist layer is formed on the outermost layer A printed wiring board,
Among the via holes, via holes of different levels are stacked,
Among the stacked via holes, at least one via hole is stacked with the other via hole shifted in the center, and the remaining via holes are stacked so that the center of the via hole is almost overlapped with the other via hole. And
Of the interlayer resin insulation layers, at least the outermost interlayer resin insulation layer has a coefficient of linear expansion of 100 ppm / ° C. or less. The multilayer printed wiring board according to claim 1, wherein particles and a rubber component are blended in at least the outermost interlayer resin insulating layer among the interlayer resin insulating layers. The multilayer printed wiring board according to claim 2, wherein the particles are at least one of inorganic particles, resin particles, and metal particles. Among the interlayer resin insulation layers, at least the outermost interlayer resin insulation layer includes a thermosetting resin, a photosensitive resin, a resin composite of a thermosetting resin and a thermoplastic resin, and a thermosetting resin and a photosensitive resin. The multilayer printed wiring board in any one of Claims 1-3 currently formed with the resin composition containing at least 1 sort (s) of the resin complex with resin. The multilayer printed wiring board according to any one of claims 1 to 4, wherein the interlayer resin insulation layer has a linear expansion coefficient of 30 to 90 ppm / ° C. The multilayer printed wiring board according to any one of claims 1 to 5, wherein the remaining via holes are stacked such that a horizontal distance between centers of upper and lower via holes is 5 µm or less. The multilayer printed wiring board according to claim 1, wherein the via hole is made of plating and has a field via shape.

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