JPH09266274A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH09266274A JPH09266274A JP8074119A JP7411996A JPH09266274A JP H09266274 A JPH09266274 A JP H09266274A JP 8074119 A JP8074119 A JP 8074119A JP 7411996 A JP7411996 A JP 7411996A JP H09266274 A JPH09266274 A JP H09266274A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- package
- forming portion
- semiconductor
- package substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップのパ
ッケージングに関する。TECHNICAL FIELD The present invention relates to packaging of semiconductor chips.
【０００２】[0002]
【従来の技術】周知のように、半導体パッケージは、半
導体チップを機械的に補強すると共に湿気等の外的環境
から保護し、さらに回路基板等への実装を容易にするた
め、半導体チップの電極と外部リードとを電気的に接続
した後、通常は全体的に樹脂封止したものである。この
ような半導体パッケージにおいては、小型化の模索が急
速に進んでいる。2. Description of the Related Art As is well known, a semiconductor package is an electrode of a semiconductor chip in order to mechanically reinforce the semiconductor chip, protect it from an external environment such as moisture, and facilitate mounting on a circuit board or the like. After being electrically connected to the external lead, it is usually entirely resin-sealed. In such a semiconductor package, the search for miniaturization is rapidly progressing.
【０００３】例えば、パッケージ形状としては、薄型Ｓ
ＯＰ(Small Outline Package) や薄型ＱＦＰ(Quad Flat
Package) 等がある。また、パッケージング構造として
は、半導体チップ上にリードの先端を固着し、そのチッ
プ上で電極とリード部分とをボンディングワイヤによっ
て接続する、いわゆるＬＯＣ(Lead On Chip)等がある。
これらによって、モールドパッケージでの小型化は限界
が近いと考えられる。しかしながら、ＬＯＣ構造の薄型
ＳＯＰでも、モールド部に占める半導体チップの体積
は、最大でも２４％程度（面積占有率８０％、厚み占有
率３０％）にしかすぎない。For example, the package shape is a thin S
OP (Small Outline Package) and thin QFP (Quad Flat)
Package) etc. Further, as a packaging structure, there is a so-called LOC (Lead On Chip) or the like in which the tips of the leads are fixed on the semiconductor chip and the electrodes and the lead portions are connected on the chip by bonding wires.
From these, it is considered that the miniaturization of the molded package is near the limit. However, even in the thin SOP having the LOC structure, the volume of the semiconductor chip occupying the mold portion is only about 24% at maximum (area occupancy rate 80%, thickness occupancy rate 30%).
【０００４】また、従来のモールドパッケージでは、半
導体チップからの放熱性も悪く、例えば、放熱性が比較
的に良いとされるＱＦＰ（４２アロイ材リード、１００
ピン、一般モールド構造、基板実装時、無風状態）で
も、熱抵抗θja＝９０℃／Ｗも多くの検討がなされてい
るのが現状である。ところで最近、高速動作性や小型化
等の利点を有する実装技術として、高密度配線基板に複
数のベアチップを搭載するＭＣＭ(Multichip Module)が
注目されている。このＭＣＭにおいては、ベアチップを
用いることによって、前述のモールドパッケージと比較
して小型化及び放熱性の点では有利となる。Further, in the conventional mold package, the heat dissipation from the semiconductor chip is poor, and for example, the QFP (42 alloy material lead, 100, which is considered to have relatively good heat dissipation).
At present, many studies have been made on the thermal resistance θja = 90 ° C./W even for pins, general mold structures, and when mounted on a board in a windless state. By the way, recently, an MCM (Multichip Module) in which a plurality of bare chips are mounted on a high-density wiring substrate has attracted attention as a mounting technique having advantages such as high-speed operability and miniaturization. In this MCM, the use of the bare chip is advantageous in terms of downsizing and heat dissipation compared with the above-mentioned mold package.
【０００５】ところが、このＭＣＭでは、搭載されるベ
アチップの全てが信頼性を含め良品（いわゆるKnown Go
od Die）であることが必須事項である。しかしながら、
ベアチップでの特性評価や信頼性評価は、半導体チップ
自体のハンドリングとなるので、ハンドリング中におけ
る半導体チップの破損や表面回路の破損等、困難な点が
多いという問題がある。However, in this MCM, all of the bare chips mounted are non-defective (including so-called Known Go).
od Die) is a must. However,
Since the characteristic evaluation and the reliability evaluation of the bare chip are handling of the semiconductor chip itself, there is a problem that there are many difficulties such as damage of the semiconductor chip and surface circuit during the handling.
【０００６】この課題を解決するために、電極部に相当
する部位に開口部を設け、機械的強度を有した絶縁体
（パッケージ基板）で、半導体チップ表面を保護し、Ｃ
ＯＢ実装する方法（本発明者による先願「特願平６−３
０５５７４」参照）が考えられる（図３参照）。In order to solve this problem, an opening is provided at a portion corresponding to the electrode portion, and the surface of the semiconductor chip is protected by an insulator (package substrate) having mechanical strength, and C
OB mounting method (previous application “Japanese Patent Application No. 6-3
05574 ") (see FIG. 3).
【０００７】[0007]
【発明が解決しようとする課題】上記方法は、小型化、
放熱性の確保には優れるが、チップの小型化、薄型化が
進んでくるとハンドリング面での強度を十分に考慮に入
れなければならない。このパッケージ基板では開口部の
外側の肉厚（図３の「ａ」）が、実際には例えば０．０
３ｍｍ〜０．１ｍｍ程度と非常に薄く機械的強度に限界
があり、該パッケージ基板製作時（樹脂成形時の樹脂の
流動問題，多数個取りの板上成型物からの分断時の問
題）やハンドリング時（テストハンドラー，ダイボン
ド，回路基板への実装）に破損する確率が課題がチップ
の小型化、薄型化とともに高くなる。SUMMARY OF THE INVENTION The above-mentioned method is for miniaturization,
Although it is excellent in securing heat dissipation, the strength of the handling surface must be fully taken into consideration as the chip becomes smaller and thinner. In this package substrate, the thickness outside the opening (“a” in FIG. 3) is actually 0.0
It has a very thin mechanical strength of about 3 mm to 0.1 mm, and its mechanical strength is limited. During the manufacturing of the package substrate (problem of resin flow during resin molding, problem when cutting from multiple molded products on board) and handling. The problem is that the probability of damage at the time (test handler, die bond, mounting on a circuit board) becomes higher as the chip becomes smaller and thinner.
【０００８】本発明は、機械的強度を高めた半導体パッ
ケージを提供する事を目的とする。An object of the present invention is to provide a semiconductor package having improved mechanical strength.
【０００９】[0009]
【課題を解決するための手段】そこでこの発明のパッケ
ージでは、パッケージ基板の形状及び配置を工夫し、半
導体チップの中央部に設けられた回路パターン形成部と
半導体チップの外周部に設けられた電極形成部を有する
半導体チップを封止する半導体パッケージにおいて、回
路パターン形成部を覆いかつ電極形成部を露出させる位
置にパッケージ基板を接合している。Therefore, in the package of the present invention, the shape and arrangement of the package substrate are devised, and the circuit pattern forming portion provided in the central portion of the semiconductor chip and the electrodes provided in the outer peripheral portion of the semiconductor chip. In a semiconductor package that seals a semiconductor chip having a formation portion, a package substrate is bonded to a position that covers the circuit pattern formation portion and exposes the electrode formation portion.
【００１０】また、パッケージ基板として電極形成部の
電極列に平行な辺を少なくとも１辺持つ矩形状基板を用
いる事も出来る。更に、電極形成部として、半導体チッ
プの４辺のそれぞれに直線上に配置されたボンディング
パッド列を設け、パッケージ基板はパッケージ基板の４
辺がボンディングパッド列に平行かつ回路パターン形成
部を覆うように配置する事も出来る。Further, as the package substrate, a rectangular substrate having at least one side parallel to the electrode array of the electrode forming portion can be used. Further, as the electrode forming portion, a bonding pad row arranged linearly is provided on each of the four sides of the semiconductor chip.
It is also possible to arrange the sides so as to be parallel to the bonding pad row and cover the circuit pattern forming portion.
【００１１】また、電極形成部として、半導体チップの
中央部に直線上に配置されたボンディングパッド列を設
け、パッケージ基板はボンディングパッド列を挟んで半
導体チップ上で対向する２つの基板で構成する事も出来
る。また、電極形成部として、半導体チップの対向する
２つの縁に沿って直線上に配置された２列のボンディン
グパッド列を設け、パッケージ基板はボンディングパッ
ド列に挟まれた回路パターン形成部を覆うように配置す
る事も出来る。As the electrode forming portion, a linearly arranged bonding pad row is provided in the central portion of the semiconductor chip, and the package substrate is composed of two substrates facing each other on the semiconductor chip with the bonding pad row sandwiched therebetween. You can also Further, as the electrode forming portion, two rows of bonding pad rows arranged linearly along two opposing edges of the semiconductor chip are provided, and the package substrate covers the circuit pattern forming portion sandwiched between the bonding pad rows. It can also be placed in.
【００１２】以上の構造により、パッケージ基板から機
械的強度が極端に脆弱な部位を無くすることが可能とな
る。With the above structure, it is possible to eliminate a portion of the package substrate having extremely weak mechanical strength.
【００１３】[0013]
【発明の実施の形態】本発明の実施の形態を図面を用い
て説明する。図１は、本発明の第１の実施の形態を示す
平面図（同図（ａ））及び断面図（同図（ｂ））であ
り、符号１は半導体チップ、１２は半導体チップ１の電
極（ボンディングパッド）、２は接着層、３１は平板の
絶縁物（エポキシ樹脂等）から成るパッケージ基板を示
す。パッケージ基板３１は半導体チップ１の電極部より
一回り小さいパッケージ基板である。符号４はボンディ
ングワイヤー、符号５は例えばＡｇペースト等のダイボ
ンド材、符号６は実装基板を示す。Embodiments of the present invention will be described with reference to the drawings. 1A and 1B are a plan view (FIG. 1A) and a cross-sectional view (FIG. 1B) showing a first embodiment of the present invention. Reference numeral 1 is a semiconductor chip, and 12 is an electrode of the semiconductor chip 1. (Bonding pad), 2 is an adhesive layer, 31 is a package substrate made of a flat insulator (epoxy resin or the like). The package substrate 31 is a package substrate that is slightly smaller than the electrode portion of the semiconductor chip 1. Reference numeral 4 indicates a bonding wire, reference numeral 5 indicates a die bonding material such as Ag paste, and reference numeral 6 indicates a mounting substrate.
【００１４】ボンディングパッド１２は半導体チップ１
の４つの辺に沿って設置され、ボンディングパッド１２
に囲まれた半導体チップ１の中央部には半導体回路パタ
ーン形成部が形成されている。矩形のパッケージ基板３
１の各辺はそれぞれボンディングパッド１２列に平行に
なるように位置決めされる。これによりチップ中央部の
回路パターン形成部はパッケージ基板３１によって完全
に覆われかつボンディングパッド１２が形成される部分
はボンディングに十分な余裕をもって露出させる事が出
来る。The bonding pad 12 is the semiconductor chip 1.
The bonding pads 12 are installed along the four sides of the
A semiconductor circuit pattern forming portion is formed in the central portion of the semiconductor chip 1 surrounded by. Rectangular package substrate 3
Each side of 1 is positioned so as to be parallel to the row of 12 bonding pads. As a result, the circuit pattern forming portion at the center of the chip is completely covered by the package substrate 31, and the portion where the bonding pad 12 is formed can be exposed with a sufficient margin for bonding.
【００１５】このパッケージを組み立てるには、半導
体チップ１と接着層２（または接着層２と該パッケージ
基板３１）を接合させ、半導体チップ１のいずれの電
極のワイヤーボンドをも妨げない様な待遇で、半導体チ
ップ１の表面と、パッケージ基板３１とを接合し、こ
れを実装基板６（最終の回路基板）にダイボンディング
し、該半導体チップ１の電極と実装基板６の所定の位
置とをワイヤリングし実用となるパッケージができあが
る。When assembling this package, the semiconductor chip 1 and the adhesive layer 2 (or the adhesive layer 2 and the package substrate 31) are bonded together so that wire bonding of any electrode of the semiconductor chip 1 is not hindered. , The surface of the semiconductor chip 1 and the package board 31 are joined, and this is die-bonded to the mounting board 6 (final circuit board), and the electrodes of the semiconductor chip 1 and predetermined positions of the mounting board 6 are wired. A practical package is completed.
【００１６】ここで該パッケージ基板３１の大きさは、
ワイヤーボンディング時のキャピラリー７の外形と位置
ずれ量（図４の「ｂ」）を考慮して決定すべきである。
例えば、該キャピラリー７の位置ずれ量ｂを±０．１ｍ
ｍ（用いる装置の精度に依存する）、該キャピラリー７
の外径をｄ＝φ１．６ｍｍ（該パッケージ基板３１の厚
さと該キャピラリー７のテーパ部の長さによっても異な
る）、該パッケージ基板の位置ずれ量ｅを±０．２ｍｍ
とすると、電極１２の中心から該パッケージ基板３１の
端までの距離Ｃは、Ｃ≧１．１ｍｍ（ｂ＋ｄ／２＋ｅ）
となる。Here, the size of the package substrate 31 is
It should be determined in consideration of the outer shape of the capillary 7 and the amount of positional deviation (“b” in FIG. 4) at the time of wire bonding.
For example, the positional displacement amount b of the capillary 7 is ± 0.1 m
m (depending on the precision of the device used), the capillary 7
Has an outer diameter of d = φ1.6 mm (it also depends on the thickness of the package substrate 31 and the length of the taper portion of the capillary 7), and the displacement amount e of the package substrate is ± 0.2 mm.
Then, the distance C from the center of the electrode 12 to the end of the package substrate 31 is C ≧ 1.1 mm (b + d / 2 + e)
Becomes
【００１７】図２は、本発明の第２の実施の形態を示す
平面図であり、符号１は半導体チップ、１２は半導体チ
ップ１の電極を示す。３２は平板の絶縁物（エポキシ樹
脂等）で構成され、半導体チップ１の電極が存在する部
位においては電極列より内側に縁を有し、電極が存在し
ない部位においては半導体チップ１の縁とほぼ同等な位
置に縁を有するパッケージ基板である。図１の実施形態
との違いは図１は４角形のパッケージ基板を用いていた
のに対しこの実施形態ではボンディングパッド１２が図
の上下の辺では等間隔に並んでおらずボンディングパッ
ド１２間に間隔の広い部分が存在する点である。この間
隔の広い部分をパッケージ基板３２が覆うようにはみ出
し部３２ａ，３２ｂを設けている。従って半導体回路パ
ターン形成部のパターンによっては本実施形態の形状の
パッケージ基板３２を用いた方が良い場合がある。FIG. 2 is a plan view showing a second embodiment of the present invention. Reference numeral 1 is a semiconductor chip, and 12 is an electrode of the semiconductor chip 1. Reference numeral 32 is made of a flat insulator (epoxy resin or the like), has an edge inside the electrode array in the portion of the semiconductor chip 1 where the electrode is present, and is almost the same as the edge of the semiconductor chip 1 in the portion where no electrode is present. It is a package substrate having edges at equivalent positions. 1 differs from the embodiment of FIG. 1 in that a square package substrate is used in this embodiment, but in this embodiment the bonding pads 12 are not arranged at equal intervals on the upper and lower sides of the drawing, and therefore, between the bonding pads 12. This is the point where there are wide intervals. The projecting portions 32a and 32b are provided so that the package substrate 32 covers this wide interval. Therefore, depending on the pattern of the semiconductor circuit pattern forming portion, it may be better to use the package substrate 32 having the shape of this embodiment.
【００１８】これを組み立てるには、上述の図１の場合
と同様である。次に本発明の第３の実施の形態を図５を
用いて説明する。この実施形態は、半導体チップ１の電
極列（ボンディングパッド１２）が半導体チップ１の中
央部に１列に配置され、チップをプリント基板に実装す
る場合にはボンディングワイヤ、やリードフレームがチ
ップ上をまたいで接合されるＬＯＣ（リード・オン・チ
ップ）タイプのパッケージの場合に使用される実施の形
態である。This is assembled in the same manner as in the case of FIG. 1 described above. Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, the electrode rows (bonding pads 12) of the semiconductor chip 1 are arranged in one row in the central portion of the semiconductor chip 1, and when mounting the chip on a printed circuit board, bonding wires and lead frames are mounted on the chip. This is an embodiment used in the case of a LOC (lead-on-chip) type package joined together.
【００１９】図５は、本発明の第３の実施の形態を示す
平面図（同図（ａ））、及び断面図（同図（ｂ））、側
面図（同図（ｃ））であり、符号１は半導体チップ、１
２は半導体チップ１の電極を示す。３４は平板の絶縁物
（エポキシ樹脂等）で構成されたパッケージ基板であ
る。パッケージ基板３４ａ，３４ｂはボンディングパッ
ド列１２を挟んで半導体チップ１の上下両側の位置に接
着層２を介して接着される。パッケージ基板３４ａ，３
４ｂの向かい合う縁とボンディングパッド列１２は互い
にほぼ平行になる。FIG. 5 is a plan view (the same figure (a)), a sectional view (the same figure (b)) and a side view (the same figure (c)) showing a third embodiment of the present invention. Reference numeral 1 is a semiconductor chip, 1
Reference numeral 2 denotes an electrode of the semiconductor chip 1. Reference numeral 34 is a package substrate made of a flat insulator (epoxy resin or the like). The package substrates 34a and 34b are adhered to the upper and lower sides of the semiconductor chip 1 with the bonding layer 2 interposed therebetween with the bonding pad row 12 interposed therebetween. Package substrates 34a, 3
The opposing edges of 4b and the bonding pad row 12 are substantially parallel to each other.
【００２０】次に本発明の第４の実施の形態を図６を用
いて説明する。この実施形態は、半導体チップ１の電極
列（ボンディングパッド１２）が半導体チップ１の両端
部にそれぞれ配置され、回路パターン形成部はボンディ
ングパッド１２に挟まれた半導体チップ１の中央部に形
成される。パッケージ基板３５はこの回路パターン形成
部を覆うように接着される。Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the electrode rows (bonding pads 12) of the semiconductor chip 1 are arranged at both ends of the semiconductor chip 1, and the circuit pattern forming portion is formed in the central portion of the semiconductor chip 1 sandwiched between the bonding pads 12. . The package substrate 35 is bonded so as to cover the circuit pattern forming portion.
【００２１】上記の全ての実施形態において、最終的に
はボンディングワイヤーごとモールド樹脂等で保護され
る。In all of the above-mentioned embodiments, the bonding wire is finally protected with a molding resin or the like.
【００２２】[0022]
【発明の効果】以上の様に本発明によれば、電極部に相
当する部位に開口部を有し、かつ機械的強度を有した絶
縁体（パッケージ基板）で半導体チップ表面を保護し、
ＣＯＢ実装する方法において、パッケージ基板の機械的
強度の問題点を無くし、より確実なパッケージ基板によ
る実装が可能となる。As described above, according to the present invention, the surface of a semiconductor chip is protected by an insulator (package substrate) having an opening portion at a portion corresponding to an electrode portion and having mechanical strength,
In the COB mounting method, the problem of mechanical strength of the package substrate is eliminated, and more reliable package substrate mounting is possible.
【図１】本発明の第１の実施形態の平面図（ａ）及び断
面図（ｂ）である。FIG. 1 is a plan view (a) and a sectional view (b) of a first embodiment of the present invention.
【図２】本発明の第２の実施形態の平面図である。FIG. 2 is a plan view of a second embodiment of the present invention.
【図３】先願にて提案するところのパッケージの断面図
である。FIG. 3 is a sectional view of a package proposed in the prior application.
【図４】図１における部分的拡大図である。FIG. 4 is a partially enlarged view of FIG.
【図５】本発明の第３の実施形態の平面図（ａ）及び断
面図（ｂ）、側面図（ｃ）である。FIG. 5 is a plan view (a), a sectional view (b), and a side view (c) of a third embodiment of the present invention.
【図６】本発明の第４の実施形態の平面図である。FIG. 6 is a plan view of a fourth embodiment of the present invention.
１ 半導体チップ ２ 接着層 ４ ボンディングワイヤー ５ ダイボンド材 ６ 実装基板 ７ キャピラリー １２ 半導体チップの電極 ３１，３２，３３ パッケージ基板 1 Semiconductor Chip 2 Adhesive Layer 4 Bonding Wire 5 Die Bonding Material 6 Mounting Substrate 7 Capillary 12 Semiconductor Chip Electrodes 31, 32, 33 Package Substrate
Claims (5)
パターン形成部と半導体チップの外周部に設けられた電
極形成部を有する半導体チップを封止する半導体パッケ
ージにおいて、前記回路パターン形成部を覆いかつ前記
電極形成部を露出させる位置に接合されたパッケージ基
板を備える事を特徴とする半導体パッケージ。1. A semiconductor package for encapsulating a semiconductor chip having a circuit pattern forming portion provided in a central portion of a semiconductor chip and an electrode forming portion provided in an outer peripheral portion of the semiconductor chip, the circuit pattern forming portion being covered. A semiconductor package comprising a package substrate bonded to a position where the electrode forming portion is exposed.
電極列に平行な辺を少なくとも１辺持つ矩形状基板であ
る事を特徴とする請求項１に記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the package substrate is a rectangular substrate having at least one side parallel to an electrode array of the electrode forming portion.
辺のそれぞれに直線上に配置されたボンディングパッド
列を備え、前記パッケージ基板は前記パッケージ基板の
４辺が前記ボンディングパッド列に平行かつ前記回路パ
ターン形成部を覆うように配置される事を特徴とする請
求項１に記載の半導体パッケージ。3. The electrode forming portion is formed on the semiconductor chip 4 of the semiconductor chip.
A bonding pad row is arranged on each side in a straight line, and the package board is arranged such that four sides of the package board are parallel to the bonding pad row and cover the circuit pattern forming portion. The semiconductor package according to claim 1.
央部に直線上に配置されたボンディングパッド列を備
え、前記パッケージ基板は前記ボンディングパッド列を
挟んで前記半導体チップ上で対向する２つの基板で構成
される事を特徴とする請求項１に記載の半導体パッケー
ジ。4. The electrode forming part includes a bonding pad row arranged in a straight line at a central portion of the semiconductor chip, and the package substrate has two substrates facing each other on the semiconductor chip with the bonding pad row interposed therebetween. The semiconductor package according to claim 1, wherein the semiconductor package is formed of:
向する２つの縁に沿って直線上に配置された２列のボン
ディングパッド列を備え、前記パッケージ基板は前記ボ
ンディングパッド列に挟まれた前記回路パターン形成部
を覆うように配置される事を特徴とする請求項１に記載
の半導体パッケージ。5. The electrode forming portion includes two rows of bonding pad rows linearly arranged along two opposing edges of the semiconductor chip, and the package substrate is sandwiched between the bonding pad rows. The semiconductor package according to claim 1, wherein the semiconductor package is arranged so as to cover the circuit pattern forming portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07411996A JP3358697B2 (en) | 1996-03-28 | 1996-03-28 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07411996A JP3358697B2 (en) | 1996-03-28 | 1996-03-28 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09266274A true JPH09266274A (en) | 1997-10-07 |
| JP3358697B2 JP3358697B2 (en) | 2002-12-24 |
Family
ID=13538007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07411996A Expired - Fee Related JP3358697B2 (en) | 1996-03-28 | 1996-03-28 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3358697B2 (en) |
-
1996
- 1996-03-28 JP JP07411996A patent/JP3358697B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3358697B2 (en) | 2002-12-24 |
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